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Features
* Incorporates the ARM926EJ-STM ARM(R) Thumb(R) Processor
- DSP Instruction Extensions, Jazelle(R) Technology for Java(R) Acceleration - 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer - 220 MIPS at 200 MHz - Memory Management Unit - EmbeddedICETM, Debug Communication Channel Support - Mid-level Implementation Embedded Trace MacrocellTM Bus Matrix - Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth - Boot Mode Select Option, Remap Command Embedded Memories - One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed - One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed - One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed Dual External Bus Interface (EBI0 and EBI1) - EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash(R) - EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash DMA Controller (DMAC) - Acts as one Bus Matrix Master - Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control Twenty Peripheral DMA Controller Channels (PDC) LCD Controller - Supports Passive or Active Displays - Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode - Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers 2D Graphics Accelerator - Line Draw, Block Transfer, Polygon Fill, Clipping, Commands Queuing Image Sensor Interface - ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate - 12-bit Data Interface for Support of High Sensibility Sensors - SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format USB 2.0 Full Speed (12 Mbits per second) Host Double Port - Dual On-chip Transceivers - Integrated FIFOs and Dedicated DMA Channels USB 2.0 Full Speed (12 Mbits per second) Device Port - On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM Ethernet MAC 10/100 Base-T - Media Independent Interface or Reduced Media Independent Interface - 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Fully-featured System Controller, including - Reset Controller, Shutdown Controller - Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes - Clock Generator and Power Management Controller - Advanced Interrupt Controller and Debug Unit
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AT91 ARM Thumb Microcontrollers AT91SAM9263 Preliminary
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6249B-ATARM-14-Dec-06
- Periodic Interval Timer, Watchdog Timer and Double Real-time Timer
* Reset Controller (RSTC) * *
- Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) - Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) - 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities - Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) - Individually Maskable, Eight-level Priority, Vectored Interrupt Sources - Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) - 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) - 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) - Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Two Real-time Timers (RTT) - 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE) - 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os - Input Change Interrupt Capability on Each I/O Line - Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output One Part 2.0A and Part 2.0B-compliant CAN Controller - 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two Multimedia Card Interface (MCI) - SDCard/SDIO and MultiMediaCardTM Compliant - Automatic Protocol Control and Fast Automatic Data Transfers with PDC - Two SDCard Slots Support on eAch Controller Two Synchronous Serial Controllers (SSC) - Independent Clock and Frame Sync Signals for Each Receiver and Transmitter - IS Analog Interface Support, Time Division Multiplex Support - High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) - 6-channel Single AC97 Analog Front End Interface, Slot Assigner Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) - Individual Baud Rate Generator, IrDA(R) Infrared Modulation/Demodulation, Manchester Encoding/Decoding - Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) - 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects - Synchronous Communications at Up to 90Mbits/sec One Three-channel 16-bit Timer/Counters (TC) - Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel - Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) One Two-wire Interface (TWI) - Master Mode Support, All Two-wire Atmel(R) EEPROMs Supported
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AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
* IEEE(R) 1149.1 JTAG Boundary Scan on All Digital Pins * Required Power Supplies
- 1.08V to 1.32V for VDDCORE and VDDBU - 3.0V to 3.6V for VDDOSC and VDDPLL - 2.7V to 3.6V for VDDIOP0 (Peripheral I/Os) - 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) - Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os) * Available in a 324-ball BGA Green Package
1. Description
The AT91SAM9263 32-bit microcontroller, based on the ARM926-EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent bottlenecks, thus guaranteeing maximum performance. The AT91SAM9263 embeds an LCD Controller supported by a 2D Graphics Controller and a 2channel DMA Controller, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multimedia Card interface and one CAN Controller. When coupled with an external GPS engine, the AT91SAM9263 provides the ideal solution for navigation systems.
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Figure 2-1.
2. AT91SAM9263 Block Diagram
N T TDRS T TDI O TM S TC K
RT JT CK AG SE
L
MASTER
SLAVE
TC TS LK TPYN C TPS0 K -TP BM 0-T S2 S PK1 5 LC LCDD 0LCDV LC S LCDH YN DD S LCDD YNC 23 O LCDD TCC EN K D C ET C ETXCK ECXEN-ER R-X ER S- ETX CK E ERXE CO ER ERE RL FC ET X0- -ER K XE X EM 0-E RX DV 3 EMDC TX 3 EF DIO 10 0 H D H PA D M HA D H PB D M B
IS
MCI0_, MCI_1
D B0 -D DA C B3 0- DB DA C3 DA C K TW C TW D T C RTS0- K C SC S0- TS R2 R K0- TS DS2 X TX 0- CK2 D RD 0- X TX 2 D 2 CA NT C AN X R NX P N CS PC 3 NS P2 N CS PC 1 SP S0 C MK O M SI PW IS O M 0PW TC M L 3 TI K0OT A0 CL TI O -T K2 B0 IO -T A2 AC IOB 2 AC97C AC 97 K FS AC97R 9X TK 7TX TF0-T TD 0-TK1 R 0-T F1 D DD M AR RF0-R 1 Q R 0- D1 0_ K R D 0-R F1 MK AR 1 Q 3 D D DP D M
SPI0_, SPI1_
I_ IS D I_ 0P IS -IS CK I I_ IS _HS D1 I_ Y 1 VN IS SYNC I_ C M C K
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AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Block Diagram
TST
System Controller AIC DBGU
PDC
JTAG Boundary Scan
Transc. Transc.
EBI0
In-Circuit Emulator
FIQ IRQ0-IRQ1 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT PLLA PLLB OSC WDT VDDCORE VDDBU XIN32 XOUT32 SHDN WKUP POR OSC
ARM926EJ-S Processor
ETM
ICache 16K bytes MMU DCache 16K bytes
LCD Controller
LUT FIFO
10/100 Ethernet MAC
FIFO DMA FIFO
USB OHCI
CompactFlash NAND Flash
TCM Interface ITCM DTCM
PMC
Bus Interface
DMA D
DMA SDRAM Controller Static Memory Controller ECC Controller DMA
I
Fast SRAM 80 Kbytes PIT
9-layer Bus Matrix
PIOA PIOB PIOC PIOD SRAM 16 Kbytes Peripheral Bridge 20-channel Peripheral DMA
20GPREG RTT0 RTT1 SHDWC
2-channel
DMA
RSTC VDDCORE NRST POR
PIOE
ROM 128 Kbytes APB
2D Graphics Controller
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 NCS3/NANDCS A25/CFRNW CFCE1-CFCE2 D16-D31 NCS2 D0-D15 A0/NBS0 A1/NWR2 A2-A15/A18-A20 A16/BA0 A17/BA1 NCS0 NRD NWR0/NWE NWR1/NBS1 SDCK A21/NANDALE A22/NANDCLE NWAIT NWR3/NBS3 NCS1/SDCS NCS2/NANDCS D16-D31 SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE
EBI0_
EBI1_
EBI1
NAND Flash
SDRAM Controller PDC DMA USB Device Port Static Memory Controller ECC Controller
PDC MCI0 MCI1 TWI
PDC USART0 USART1 USART2 CAN
PDC SPI0 SPI1 PWMC TC0 TC1 TC2
PDC AC97C
SSC0 SSC1
Image Sensor Interface
Transc.
AT91SAM9263 Preliminary
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral. Table 3-1.
Signal Name
Signal Description List
Function Power Supplies Type Active Level Comments
VDDIOM0 VDDIOM1 VDDIOP0 VDDIOP1 VDDBU VDDPLL VDDOSC VDDCORE GND GNDPLL GNDBU
EBI0 I/O Lines Power Supply EBI1 I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply Ground PLL Ground Backup Ground
Power Power Power Power Power Power Power Power Ground Ground Ground
1.65V to 3.6V 1.65V to 3.6V 2.7V to 3.6V 1.65V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V
Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL A Filter PLL B Filter Programmable Clock Output Input Output Input Output Input Input Output
Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input ICE and JTAG NTRST TCK TDI TDO TMS JTAGSEL RTCK Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Input Input Input Output Input Input Output No pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. Low Pull-up resistor No pull-up resistor No pull-up resistor Output Input Driven at 0V only. Do not tie over VDDBU. Accepts between 0V and VDDBU.
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Table 3-1.
Signal Name
Signal Description List (Continued)
Function Type Embedded Trace Module - ETM Active Level Comments
TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15
Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Reset/Test
Output Output Output Output
NRST TST BMS
Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit - DBGU
I/O Input Input
Low
Pull-up resistor Pull-down resistor
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
Advanced Interrupt Controller - AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input
PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD31 PE0 - PE31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E I/O I/O I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset
Direct Memory Access Controller - DMA DMARQ0-DMARQ3 DMA Requests Input
External Bus Interface - EBI0 - EBI1 EBIx_D0 - EBIx_D31 EBIx_A0 - EBIx_A25 EBIx_NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset 0 at reset
Static Memory Controller - SMC EBI0_NCS0 - EBI0_NCS5, EBI1_NCS0 - EBI1_NCS2 EBIx_NWR0 -EBIx_NWR3 EBIx_NRD EBIx_NWE EBIx_NBS0 - EBIx_NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output CompactFlash Support EBI0_CFCE1 - EBI0_CFCE2 CompactFlash Chip Enable Output Low Low Low Low Low Low
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AT91SAM9263 Preliminary
Table 3-1.
Signal Name EBI0_CFOE EBI0_CFWE EBI0_CFIOR EBI0_CFIOW EBI0_CFRNW EBI0_CFCS0 - EBI0_CFCS1
Signal Description List (Continued)
Function CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Support Type Output Output Output Output Output Output Low Active Level Low Low Low Low Comments
EBIx_NANDCS EBIx_NANDOE EBIx_NANDWE
NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller
Output Output Output
Low Low Low
EBIx_SDCK EBIx_SDCKE EBIx_SDCS EBIx_BA0 - EBIx_BA1 EBIx_SDWE EBIx_RAS - EBIx_CAS EBIx_SDA10
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line
Output Output Output Output Output Output Output Low Low High Low
Multimedia Card Interface MCIx_CK MCIx_CDA MCIx_CDB MCIx_DA0 - MCIx_DA3 MCIx_DB0 - MCIx_DB3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot B A Command Multimedia Card Slot A Data Multimedia Card Slot B Data Output I/O I/O I/O I/O
Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O I/O Input Output Input
Synchronous Serial Controller SSC TDx RDx TKx RKx SSCx Transmit Data SSCx Receive Data SSCx Transmit Clock SSCx Receive Clock Output Input I/O I/O
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Table 3-1.
Signal Name TFx RFx
Signal Description List (Continued)
Function SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller - AC97C Type I/O I/O Active Level Comments
AC97RX AC97TX AC97FS AC97CK
AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer/Counter - TC
Input Output Output Input
TCLKx TIOAx TIOBx
TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B
Input I/O I/O
Pulse Width Modulation Controller- PWMC PWMx Pulse Width Modulation Output Output
Serial Peripheral Interface - SPI SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1 - SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock CAN Controllers CANRX CANTX CAN Input CAN Output Input Output LCD Controller - LCDC LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control Ethernet 10/100 ETXCK ERXCK Transmit Clock or Reference Clock Receive Clock Input Input MII only, REFCK in RMII MII only Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O Output Low Low
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AT91SAM9263 Preliminary
Table 3-1.
Signal Name ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100
Signal Description List (Continued)
Function Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. USB Device Port Type Output Output Output Input Input Input Input Input Output I/O Output High RMII only MII only MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII Active Level Comments
DDM DDP
USB Device Port Data USB Device Port Data + USB Host Port
Analog Analog
HDPA HDMA HDPB HDMB
USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data -
Analog Analog Analog Analog
Image Sensor Interface - ISI ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data Clock Input Output Input Input Input
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4. Package and Pinout
The AT91SAM9263 is available in a 324-ball Green BGA package, 15 x 15 mm, 0.8mm ball pitch.
4.1
324-ball LFBGA Package Outline
Figure 4-1 shows the orientation of the 324-ball BGA package. A detailed mechanical description is given in the section "AT91SAM9263 Mechanical Characteristics" in the product datasheet.
Figure 4-1.
324-ball BGA Pinout (Top View)
TOP VIEW
V U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
BALL A1
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AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
4.2
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14
324-ball BGA Package Pinout
AT91SAM9263 Pinout for 324-ball BGA Package
Pin E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 Signal Name PC31 PC22 PC15 PC11 PC4 PB30 PC0 PB31 HDPA PD7 EBI0_D13 EBI0_D9 EBI0_D11 EBI0_D12 EBI0_NCS0 EBI0_A16_BA0 EBI0_A12 EBI0_A6 PD3 PC27 PC18 PC13 PB26 PB25 PB29 PB27 HDMA PD17 PD12 PD6 EBI0_D14 PD5 PD8 PD10 GND NC(1) GND GND GND PB21 PB20 PB23 PB28 PB22 PB18 PD24 PD13 PD15 PD9 PD11 Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 Signal Name PE6 PD28 PE0 PE1 PD27 PD31 PD29 PD25 GND VDDIOM0 GND VDDIOM0 PB3/BMS PA14 PA15 PB1 PB0 PB2 PE10 PE4 PE9 PE7 PE5 PE2 PE3 VDDIOP1 VDDIOM1 VDDIOM0 VDDIOP0 GNDBU PA13 PB4 PA9 PA12 PA10 PA11 PE18 PE14 PE15 PE11 PE13 PE12 PE8 VDDBU EBI1_A21 VDDIOM1 GND GND VDDIOM1 PA6 Pin P10 P11 P12 P13 P14 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 Signal Name EBI1_NCS0 EBI1_NWE_NWR0 EBI1_D4 EBI1_D10 PA3 PA2 PE28 TDI PLLRCB XOUT32 TST PA18 PA25 PA30 EBI1_A2 EBI1_A14 EBI1_A13 EBI1_A17_BA1 EBI1_D1 EBI1_D8 EBI1_D12 EBI1_D15 PE26 EBI1_SDCK PE30 TCK XOUT VDDOSC VDDIOM1 PA19 PA21 PA26 PA31 EBI1_A7 EBI1_A12 EBI1_A18 EBI1_D0 EBI1_D7 EBI1_D14 PE23 PE25 PE29 PE31 GNDPLL XIN PA17 PA20 PA23 PA24 PA28 Signal Name EBI0_D2 EBI0_SDCKE EBI0_NWE_NWR0 EBI0_NCS1_SDCS EBI0_A19 EBI0_A11 EBI0_A10 EBI0_A5 EBI0_A1_NBS2_NWR2 PD4 PC30 PC26 PC24 PC19 PC12 VDDCORE VDDIOP0 DDP EBI0_D4 EBI0_NANDOE EBI0_CAS EBI0_RAS EBI0_NBS3_NWR3 EBI0_A22 EBI0_A15 EBI0_A7 EBI0_A4 PD0 PC28 PC21 PC17 PC9 PC7 PC5 PB16 DDM EBI0_D6 EBI0_D0 EBI0_NANDWE EBI0_SDWE EBI0_SDCK EBI0_A21 EBI0_A13 EBI0_A8 EBI0_A3 PD2 PC29 PC23 PC14 PC8
Table 4-1.
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Table 4-1.
Pin C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 PC3 GND
AT91SAM9263 Pinout for 324-ball BGA Package
Pin H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 Signal Name PD14 PD16 VDDIOM0 GND VDDCORE GND PB19 PB17 PB15 PB13 PB24 PB14 PB12 PD30 PD26 PD22 PD19 PD18 PD23 PD21 PD20 GND GND GND PB11 PB9 PB10 PB5 PB6 PB7 PB8 Pin M15 M16 M17 M18 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 Signal Name PA4 PA7 PA5 PA8 NC NC PE19 NC(1) PE17 PE16 EBI1_A6 EBI1_A11 EBI1_A22 EBI1_D2 EBI1_D6 EBI1_D9 GND GNDPLL PA1 PA0 TMS TDO XIN32 SHDN PA16 WKUP JTAGSEL PE20 EBI1_A8 EBI1_A4 EBI1_A19 Pin U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name EBI1_A0_NBS0 EBI1_A5 EBI1_A10 EBI1_A16_BA0 EBI1_NRD EBI1_D3 EBI1_D13 PE22 PE27 RTCK NTRST VDDPLLA PLLRCA VDDCORE PA22 PA27 PA29 EBI1_A1_NWR2 EBI1_A3 EBI1_A9 EBI1_A15 EBI1_A20 EBI1_NBS1_NWR1 EBI1_D5 EBI1_D11 PE21 PE24 NRST GND GND VDDPLLB
Signal Name
VDDIOP0 HDPB EBI0_D10 EBI0_D3 NC(1) EBI0_D1 EBI0_A20 EBI0_A17_BA1 EBI0_A18 EBI0_A9 EBI0_A2 PD1 PC25 PC20 PC6 PC16 PC10 PC2 PC1 HDMB EBI0_D15 EBI0_D7 EBI0_D5 EBI0_D8 EBI0_NBS1_NWR1 EBI0_NRD EBI0_A14 EBI0_SDA10 EBI0_A0_NBS0
Note:
1. NC pins must be left unconnected.
5. Power Considerations
5.1 Power Supplies
AT91SAM9263 has several types of power supply pins: * VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V to 1.32V, 1.2V nominal. * VDDIOM0 and VDDIOM1 pins: Power the External Bus Interface 0 I/O lines and the External Bus Interface 1 I/O lines, respectively; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). * VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V to 3.6V, 3.3V nominal. * VDDIOP1 pins: Power the Peripheral I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. * VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V to 1.32V, 1.2V nominal. 12
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
* VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V to 3.6V, 3.3V nominal. * VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V to 3.6V, L3.3V nominal. The power supplies VDDIOM0, VDDIOM1 and VDDIOP0, VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDOSC, VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0 and VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU and VDDPLL. These ground pins are respectively GNDBU and GNDPLL.
5.2
Power Consumption
The AT91SAM9263 consumes about 700 A of static current on VDDCORE at 25C. This static current rises at up to 7 mA if the temperature increases to 85C. On VDDBU, the current does not exceed 3 A @25C, but can rise at up to 20 A @85C. A software-controllable switch to VDDCORE guarantees zero power consumption on the battery when the system is on. For dynamic power consumption, the AT91SAM9263 consumes a maximum of 70 mA on VDDCORE at maximum conditions (1.2V, 25C, processor running full-performance algorithm).
5.3
Programmable I/O Lines Power Supplies
The power supply pins VDDIOM0 and VDDIOM1 accept two voltage ranges. This allows the device to reach its maximum speed, either out of 1.8V or 3.0V external memories. The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power supply at 1.8V and 50pF for power supply at 3.3V. The other signals (control, address and data signals) do not go over 50MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. However, the device cannot reach its maximum speed if the voltage supplied to the pins is only 1.8V without reprogramming the EBI0 voltage range. The user must be sure to program the EBI0 voltage range before getting the device out of its Slow Clock Mode.
6. I/O Line Considerations
6.1 JTAG Port Pins
TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (VDDBU). It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3. All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0.
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6.2
Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 k to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU.
6.3
Reset Pins
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manage the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 k minimum to VDDIOP0. The NRST signal is inserted in the Boundary Scan.
6.4
PIO Controllers
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor of 100 k minimum. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing tables on page 34 and following.
6.5
Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
7. Processor and Architecture
7.1 ARM926EJ-S Processor
* RISC Processor based on ARM v5TEJ Harvard Architecture with Jazelle technology for Java acceleration * Two Instruction Sets - ARM High-performance 32-bit Instruction Set - Thumb High Code Density 16-bit Instruction Set * DSP Instruction Extensions * 5-stage Pipeline Architecture - Instruction Fetch (F) - Instruction Decode (D)
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- Execute (E) - Data Memory (M) - Register Write (W) * 16 Kbyte Data Cache, 16 Kbyte Instruction Cache - Virtually-addressed 4-way Associative Cache - Eight words per line - Write-through and Write-back Operation - Pseudo-random or Round-robin Replacement * Write Buffer - Main Write Buffer with 16-word Data Buffer and 4-address Buffer - DCache Write-back Buffer with 8-word Entries and a Single Address Entry - Software Control Drain * Standard ARM v4 and v5 Memory Management Unit (MMU) - Access Permission for Sections - Access Permission for large pages and small pages can be specified separately for each quarter of the page - 16 embedded domains * Bus Interface Unit (BIU) - Arbitrates and Schedules AHB Requests - Separate Masters for both instruction and data access providing complete Matrix system flexibility - Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface - On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words)
7.2
Bus Matrix
* 9-layer Matrix, handling requests from 9 masters * Programmable Arbitration strategy - Fixed-priority Arbitration - Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master * Burst Management - Breaking with Slot Cycle Limit Support - Undefined Burst Length Support * One Address Decoder provided per Master - Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap * Boot Mode Select - Non-volatile Boot Memory can be internal or external - Selection is made by BMS pin sampled at reset * Remap Command
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- Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory - Allows Handling of Dynamic Exception Vectors
7.3
Matrix Masters
The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with others to an available slave peripheral or memory. Each master has its own decoder, which is defined specifically for each master. Table 7-1.
Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8
List of Bus Matrix Masters
ARM926TM Instruction ARM926 Data Peripheral DMA Controller LCD Controller 2D Graphic Controller Image Sensor Interface DMA Controller Ethernet MAC OHCI USB Host Controller
7.4
Matrix Slaves
The Bus Matrix of the AT91SAM9263 manages eight slaves. Each slave has its own arbiter, thus allowing to program a different arbitration per slave. The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a slave on the Matrix. They share the same layer, as programming them does not require a high bandwidth. Table 7-2.
Slave 0 Slave 1 Slave 2 Slave 3
List of Bus Matrix Slaves
Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM Bank Reserved Internal ROM LCD Controller User Interface
Slave 4
DMA Controller User Interface USB Host User Interface
Slave 5 Slave 6 Slave 7
External Bus Interface 0 External Bus Interface 1 Peripheral Bridge
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7.5 Master to Slave Access
In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and are shown as "-" in Table 7-3. Table 7-3. Masters to Slaves Access
0&1 ARM926 Instruction & Data X X 2 Peripheral DMA Controller X X 3 LCD Controller X X 4 2D Graphics Controller X X 5 Image Sensor Interface X X 6 DMA Controller X X 7 Ethernet MAC X X 8 OHCI USB Host Controller X X
Master Slave Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM Bank
0 1 2 3
Internal ROM LCD Controller User Interface
X X X X X X X
X X X X
X X X -
X X X -
X X X -
X X X X
X X X -
X X X -
4
DMA Controller User Interface USB Host User Interface
5 6 7
External Bus Interface 0 External Bus Interface 1 Peripheral Bridge
7.6
Peripheral DMA Controller
* Acts as one Matrix Master * Allows data transfers between a peripheral and memory without any intervention of the processor * Next Pointer support, removes heavy real-time constraints on buffer management. * Twenty channels - Two for each USART - Two for the Debug Unit - Two for each Serial Synchronous Controller - Two for each Serial Peripheral Interface - Two for the AC97 Controller - One for each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (low to high priorities): - DBGU Transmit Channel - USART2 Transmit Channel
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- USART1 Transmit Channel - USART0 Transmit Channel - AC97 Transmit Channel - SPI1 Transmit Channel - SPI0 Transmit Channel - SSC1 Transmit Channel - SSC0 Transmit Channel - DBGU Receive Channel - USART2 Receive Channel - USART1 Receive Channel - USART0 Receive Channel - AC97 Receive Channel - SPI1 Receive Channel - SPI0 Receive Channel - SSC1 Receive Channel - SSC0 Receive Channel - MCI1 Transmit/Receive Channel - MCI0 Transmit/Receive Channel
7.7
DMA Controller
* Acts as one Matrix Master * Embeds 2 unidirectional channels with programmable priority * Address Generation - Source/destination address programming - Address increment, decrement or no change - DMA chaining support for multiple non-contiguous data blocks through use of linked lists - Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory. - Gather support for extracting fields from a system memory area into a contiguous transfer - User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer - Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode - Unaligned system address to data transfer width supported in hardware * Channel Buffering - Two 8-word FIFOs - Automatic packing/unpacking of data to fit FIFO width * Channel Control - Programmable multiple transaction size for each channel - Support for cleanly disabling a channel without data loss
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- Suspend DMA operation - Programmable DMA lock transfer support. * Transfer Initiation - Supports four external DMA Requests - Support for software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface * Interrupt - Programmable interrupt generation on DMA transfer completion, Block transfer completion, Single/Multiple transaction completion or Error condition
7.8
Debug and Test Features
* ARM926 Real-time In-circuit Emulator - Two real-time Watchpoint Units - Two Independent Registers: Debug Control Register and Debug Status Register - Test Access Port Accessible through JTAG Protocol - Debug Communications Channel * Debug Unit - Two-pin UART - Debug Communication Channel Interrupt Handling - Chip ID Register * Embedded Trace Macrocell: ETM9TM - Medium+ Level Implementation - Half-rate Clock Mode - Four Pairs of Address Comparators - Two Data Comparators - Eight Memory Map Decoder Inputs - Two 16-bit Counters - One 3-stage Sequencer - One 45-byte FIFO * IEEE1149.1 JTAG Boundary-scan on All Digital Pins
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8. Memories
Figure 8-1. AT91SAM9263 Memory Mapping
Address Memory Space 0x0000 0000 Internal Memories
0x0FFF FFFF
Internal Memory Mapping
0x0000 0000 0x0010 0000 0x0020 0000 Boot Memory (1) ITCM (2) DTCM (2) SRAM (2) ROM 16K SRAM0 Notes: (1) Can be ROM, EBI0_NCS0 or SRAM depending on BMS and REMAP (2) Software programmable
256M Bytes
0x1000 0000 EBI0 Chip Select 0
0x1FFF FFFF 0x0030 0000
256M Bytes
0x0040 0000 0x0050 0000
0x2000 0000 EBI0 Chip Select 1/ EBI0 SDRAMC 256M Bytes
0x0060 0000 0x0070 0000
Reserved LCD Controller
0x2FFF FFFF
0x3000 0000 EBI0 Chip Select 2
0x3FFF FFFF
256M Bytes
0x0080 0000 DMAC 0x0090 0000 Reserved USB HOST 0x00B0 0000 Reserved
0x4000 0000
EBI0 Chip Select 3/ NANDFlash EBI0 Chip Select 4/ Compact Flash Slot 0 EBI0 Chip Select 5/ Compact Flash Slot 1 EBI1 Chip Select 0
0x00A0 0000
256M Bytes
0x4FFF FFFF
0x5000 0000
256M Bytes
0xF000 0000
Peripheral Mapping
Reserved 0xFFF7 8000 UDP 0xFFF7 C000 TCO, TC1, TC2 0xFFF8 0000 MCI0 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF EE00 AC97C 0xFFFA 4000 SPI0 0xFFFA 8000 SPI1 16K Bytes 16K Bytes 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 8000 PWMC 0xFFFB C000 EMAC 0xFFFC 0000 Reserved 0xFFFC 4000 ISI 0xFFFC 8000 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FC00 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 16K Bytes 0xFFFF FDB0 Reserved 0xFFFF FFFF PMC RSTC SHDWC RTT0 PIT WDT RTT1 GPBR 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 80 Bytes 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD PIOE 512 bytes 512 bytes 512 bytes 16K Bytes 0xFFFF F200 0xFFFF F400 PIOB 512 Bytes 16K Bytes DBGU 0xFFFF F000 AIC PIOA 512 bytes 512 bytes 0xFFFF E000 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 SDRAMC1 0xFFFF EA00 0xFFFF EC00 0xFFFF ED10 SSC1 0xFFFA 0000 CCFG 512 Bytes SMC1 MATRIX 512 Bytes 512 Bytes 512 Bytes 16K Bytes 16K Bytes 16K Bytes
0x5FFF FFFF
0x6000 0000
System Controller Mapping
0xFFFF C000 Reserved ECC0 SDRAMC0 SMC0 ECC1 512 Bytes 512 Bytes 512 Bytes 512 bytes
256M Bytes
0x6FFF FFFF
0x7000 0000 256M Bytes
0xFFF8 4000 MCI1 0xFFF8 8000
0x7FFF FFFF
0x8000 0000 EBI1 Chip Select 1/ EBI1 SDRAMC
0x8FFF FFFF
TWI
256M Bytes
0xFFF8 C000 USART0 0xFFF9 0000 USART1
0x9000 0000 EBI1 Chip Select 2/ NANDFlash
0x9FFF FFFF
256M Bytes
0xFFF9 4000 USART2 0xFFF9 8000 SSC0 0xFFF9 C000
0xA000 0000
Undefined (Abort)
1,280M Bytes
0xEFFF FFFF
2DGE 0xFFFC C000 Reserved
0xF000 0000 Internal Peripherals
0xFFFF FFFF
256M Bytes
0xFFFF C000 SYSC 0xFFFF FFFF
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A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its master and slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 9 are directed to the EBI0 that associates these banks to the external chip selects EBI0_NCS0 to EBI0_NCS5 and EBI1_NCS0 to EBI1_NCS2. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M bytes of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each master has its own bus and its own decoder, thus allowing a different memory mapping for each master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot and one after remap. Refer to Table 8-1, "Internal Memory Mapping," on page 21 for details. A complete memory map is presented in Figure 8-1 on page 20.
8.1
Embedded Memories
* 128 Kbyte ROM - Single Cycle Access at full matrix speed * One 80 Kbyte Fast SRAM - Single Cycle Access at full matrix speed - Supports ARM926EJ-S TCM interface at full processor speed - Allows internal Frame Buffer for up to 1/4 VGA 8 bpp screen * 16 Kbyte Fast SRAM - Single Cycle Access at full matrix speed
8.1.1
Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap status and the BMS state at reset. Table 8-1. Internal Memory Mapping
REMAP = 0 Address 0x0000 0000 BMS = 1 ROM BMS = 0 EBI0_NCS0 SRAM C REMAP = 1
8.1.1.1
Internal 80 Kbyte Fast SRAM The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split into three areas. Its memory mapping is presented in Figure 8-1 on page 20. * Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
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configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. * Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. * Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes as shown in Table 8-2. This table provides the size of the Internal SRAM C according to the size of the internal SRAM A and the internal SRAM B. Table 8-2. Internal SRAM Block Size
Internal SRAM A (ITCM) Size Internal SRAM C Internal SRAM B (DTCM) size 0 16 Kbytes 32 Kbytes 0 80 Kbytes 64 Kbytes 48 Kbytes 16 Kbytes 64 Kbytes 48 Kbytes 32 Kbytes 32 Kbytes 48 Kbytes 32 Kbytes 16 Kbytes
Note that among the five 16 Kbyte blocks making up the Internal SRAM, one is permanently assigned to Internal SRAM C. At reset, the whole memory (80 Kbytes) is assigned to Internal SRAM C. The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software point of view. Table 8-3 illustrates different configurations and the related 16 Kbyte blocks assignments (RB0 to RB4). Table 8-3. 16 Kbyte Block Allocation
Configuration examples and related 16 Kbyte block assignments Decoded Area Internal SRAM A (ITCM) Internal SRAM B (DTCM)
ITCM = 0 Kbyte DTCM = 0 Kbyte AHB = 80 Kbytes (1) ITCM = 32 Kbytes DTCM = 32 Kbytes AHB = 16 Kbytes ITCM = 16 Kbytes DTCM = 32 Kbytes AHB = 32 Kbytes ITCM = 32 Kbytes DTCM = 16 Kbytes AHB = 32 Kbytes ITCM = 16 Kbytes DTCM = 16 Kbytes AHB = 48 Kbytes
Address 0x0010 0000 0x0010 4000 0x0020 0000 0x0020 4000
RB1 RB0 RB3 RB2
RB1
RB1 RB0
RB1
RB3 RB2
RB3
RB3
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Table 8-3. 16 Kbyte Block Allocation (Continued)
Configuration examples and related 16 Kbyte block assignments Decoded Area
ITCM = 0 Kbyte DTCM = 0 Kbyte AHB = 80 Kbytes (1) ITCM = 32 Kbytes DTCM = 32 Kbytes AHB = 16 Kbytes ITCM = 16 Kbytes DTCM = 32 Kbytes AHB = 32 Kbytes ITCM = 32 Kbytes DTCM = 16 Kbytes AHB = 32 Kbytes ITCM = 16 Kbytes DTCM = 16 Kbytes AHB = 48 Kbytes
Address 0x0030 0000
RB4 RB3 RB2 RB1 RB0
RB4
RB4 RB0
RB4 RB2
RB4 RB2 RB0
Internal SRAM C (AHB)
0x0030 4000 0x0030 8000 0x0030 C000 0x0031 0000
Note:
1. Configuration after reset.
When accessed from the Bus Matrix, the internal 80 Kbytes of Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor's TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal 16 Kbyte Fast SRAM The AT91SAM9263 integrates a 16 Kbyte SRAM, mapped at address 0x0050 0000. This SRAM is single cycle accessible at full Bus Matrix speed. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once the system has booted. When REMAP = 1, BMS is ignored. Refer to the section "AT91SAM9263 Bus Matrix" in the product datasheet for more details. When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is done via hardware at reset.
Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 20.
8.1.2
The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, Boot on Embedded ROM The system boots on Boot Program. * Boot at slow clock * Auto baudrate detection * Downloads and runs an application from external storage media into internal SRAM * Downloaded code size depends on embedded SRAM size * Automatic detection of valid application * Bootloader on a non-volatile memory
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- SPI DataFlash(R) connected on NPCS0 of the SPI0 * Interface with SAM-BATM Graphic User Interface to enable code loading via: - Serial communication on a DBGU - USB Bulk Device Port 8.1.2.2 BMS = 0, Boot on External Memory * Boot at slow clock * Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI0 CS0 (BMS=0) the user must: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and Start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. 4. Switch the main clock to the new value.
8.2
External Memories
The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to Figure 8-1 on page 20.
8.2.1
External Bus Interfaces The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. External Bus Interface 0 * Optimized for Application Memory Space support * Integrates three External Memory Controllers: - Static Memory Controller - SDRAM Controller - ECC Controller * Additional logic for NANDFlash and CompactFlash * Optional Full 32-bit External Data Bus * Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select) * Up to 6 Chip Selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3, Optional NAND Flash support - Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support
8.2.1.1
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8.2.1.2 External Bus Interface 1 * Allows supporting an external Frame Buffer for the embedded LCD Controller without impacting processor performance * Integrates three External Memory Controllers: - Static Memory Controller - SDRAM Controller - ECC Controller * Additional logic for NANDFlash * Optional Full 32-bit External Data Bus * Up to 23-bit Address Bus (up to 8 Mbytes linear) * Up to 3 Chip Selects, Configurable Assignment: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2, Optional NAND Flash support 8.2.2 Static Memory Controller * 8-, 16- or 32-bit Data Bus * Multiple Access Modes supported - Byte Write or Byte Select Lines - Asynchronous read in Page Mode supported (4- up to 32-byte page size) * Multiple device adaptability - Compliant with LCD Module - Control signals programmable setup, pulse and hold time for each Memory Bank * Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time * Slow Clock mode supported 8.2.3 SDRAM Controller * Supported devices - Standard and Low-power SDRAM (Mobile SDRAM) * Numerous configurations supported - 2K, 4K, 8K Row Address Memory Parts - SDRAM with two or four Internal Banks - SDRAM with 16- or 32-bit Data Path * Programming facilities - Word, half-word, byte access - Automatic page break when Memory Boundary has been reached - Multibank Ping-pong Access - Timing parameters specified by software - Automatic refresh operation, refresh rate is programmable 25
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* Energy-saving capabilities - Self-refresh, power down and deep power down modes supported * Error detection - Refresh Error Interrupt * SDRAM Power-up Initialization by software * CAS Latency of 1, 2 and 3 supported * Auto Precharge Command not used 8.2.4 Error Corrected Code Controller * Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select * Single-bit error correction and two-bit random detection * Automatic Hamming Code Calculation while writing - ECC value available in a register * Automatic Hamming Code Calculation while reading - Error Report, including error flag, correctable error flag and word address being detected erroneous - Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages
9. System Controller
The System Controller is a set of peripherals that allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds registers that are used to configure the Bus Matrix and a set of registers for the chip configuration. The chip configuration registers can be used to configure: - EBI0 and EBI1 chip select assignment and voltage range for external memories - ARM Processor Tightly Coupled Memories The System Controller peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of the System Controller are mapped on the top of the address space. This allows all the registers of the System Controller to be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instructions have an indexing mode of 4 Kbytes. Figure 9-1 on page 27 shows the System Controller block diagram. Figure 8-1 on page 20 shows the mapping of the User Interfaces of the System Controller peripherals.
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9.1 System Controller Block Diagram
AT91SAM9263 System Controller Block Diagram
System Controller VDDCORE Powered irq0-irq1 fiq periph_irq[2..29] pit_irq rtt0_irq rtt1_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Timer 0 Real-Time Timer 1 rtt0_irq rtt0_alarm rtt1_irq rtt1_alarm UDPCK periph_clk[24] periph_nreset periph_irq[24] Shut-Down Controller backup_nreset XIN32 XOUT32 SLOW CLOCK OSC rtt0_alarm rtt1_alarm SLCK int XIN XOUT PLLRCA PLLRCB MAIN OSC PLLA PLLB MAINCK Power Management Controller 20 General-Purpose Backup Registers Voltage Controller battery_save UHPCK periph_clk[29] periph_nreset periph_irq[29] USB Host Port USB Device Port Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq
Figure 9-1.
Debug Unit
dbgu_irq dbgu_txd
proc_nreset PCK debug
pit_irq jtag_nreset wdt_irq MCK periph_nreset Bus Matrix Boundary Scan TAP Controller
VDDCORE VDDBU
VDDBU POR battery_save
SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP
periph_clk[2..29] pck[0-3] PCK OTGCK UDPCK
periph_clk[26] periph_nreset periph_irq[26] LCD Controller
PLLACK PLLBCK
MCK pmc_irq
periph_nreset idle
periph_clk[7..27] periph_nreset
periph_nreset periph_clk[2..6] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 PE0-PE31
PIO Controllers
periph_irq[2..6] irq0-irq1 fiq dbgu_txd
Embedded Peripherals periph_irq[7..27] in out enable
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9.2
Reset Controller
* Based on two Power-on-Reset cells - One on VDDBU and one on VDDCORE * Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset * Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices
9.3
Shutdown Controller
* Shutdown and Wake-up logic - Software programmable assertion of the SHDN open-drain pin - Deassertion programmable on a WKUP pin level change or on alarm
9.4
Clock Generator
* Embeds the low-power 32768 Hz Slow Clock Oscillator - Provides the permanent Slow Clock SLCK to the system * Embeds the Main Oscillator - Oscillator bypass feature - Supports 3 to 20 MHz crystals * Embeds 2 PLLs - Output 80 to 240 MHz clocks - Integrates an input divider to increase output accuracy - 1 MHz Minimum input frequency
Figure 9-2.
Clock Generator Block Diagram
Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK
PLLRCA
PLL and Divider A PLL and Divider B Status Control
PLLA Clock PLLACK PLLB Clock PLLBCK
PLLRCB
Power Management Controller
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9.5 Power Management Controller
* Provides: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces - the USB Device Clock UDPCK - the USB Host Clock UHPCK - independent peripheral clocks, typically at the frequency of MCK - four programmable clock outputs: PCK0 to PCK3 * Five flexible operating modes: - Normal Mode with processor and peripherals running at a programmable frequency - Idle Mode with processor stopped while waiting for an interrupt - Slow Clock Mode with processor and peripherals running at low frequency - Standby Mode, mix of Idle and Backup Mode, with peripherals running at low frequency, processor stopped waiting for an interrupt - Backup Mode with Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9263 Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/3,/4 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int
periph_clk[..]
Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..]
USB Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UDPCK UHPCK
9.6
Periodic Interval Timer
* Includes a 20-bit Periodic Counter, with less than 1 s accuracy * Includes a 12-bit Interval Overlay Counter * Real-time OS or Linux(R)/WindowsCE(R) compliant tick generator
9.7
Watchdog Timer
* 16-bit key-protected Counter, programmable only once
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* Windowed, prevents the processor deadlocking on the watchdog access
9.8
Real-time Timer
* Two Real-time Timers, allowing backup of time with different accuracies - 32-bit Free-running back-up counter - Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz oscillator - Alarm Register capable of generating a wake-up of the system through the Shutdown Controller
9.9
General-purpose Backup Registers
* Twenty 32-bit general-purpose backup registers
9.10
Backup Power Switch
* Automatic switch of VDDBU to VDDCORE guaranteeing very low power consumption on VDDBU while VDDCORE is present
9.11
Advanced Interrupt Controller
* Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor * Thirty-two individually maskable and vectored interrupt sources - Source 0 is reserved for the Fast Interrupt Input (FIQ) - Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) - Programmable Edge-triggered or Level-sensitive Internal Sources - Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive * Four External Sources plus the Fast Interrupt signal * 8-level Priority Controller - Drives the Normal Interrupt of the processor - Handles priority of the interrupt sources 1 to 31 - Higher priority interrupts can be served during service of lower priority interrupt * Vectoring - Optimizes Interrupt Service Routine Branch and Execution - One 32-bit Vector Register per interrupt source - Interrupt Vector Register reads the corresponding current Interrupt Vector * Protect Mode - Easy debugging by preventing automatic operations when protect models are enabled * Fast Forcing - Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
9.12
Debug Unit
* Composed of two functions - Two-pin UART
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- Debug Communication Channel (DCC) support * Two-pin UART - Implemented features are 100% compatible with the standard Atmel USART - Independent receiver and transmitter with a common programmable Baud Rate Generator - Even, Odd, Mark or Space Parity Generation - Parity, Framing and Overrun Error Detection - Automatic Echo, Local Loopback and Remote Loopback Channel Modes - Support for two PDC channels with connection to receiver and transmitter * Debug Communication Channel Support - Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor's ICE Interface
9.13
Chip Identification
* Chip ID: 0x019607A0 * JTAG ID: 0x05B0C03F * ARM926 TAP ID: 0x0792603F
9.14
PIO Controllers
* Five PIO Controllers, PIOA to PIOE, controlling a total of 160 I/O Lines * Each PIO Controller controls up to 32 programmable I/O Lines - PIOA has 32 I/O Lines - PIOB has 32 I/O Lines - PIOC has 32 I/O Lines - PIOD has 32 I/O Lines - PIOE has 32 I/O Lines * Fully programmable through Set/Clear Registers * Multiplexing of two peripheral functions per I/O Line * For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O) - Input change interrupt - Glitch filter - Multi-drive option enables driving in open drain - Programmable pull-up on each I/O line - Pin data status register, supplies visibility of the level on the pin at any time * Synchronous output, provides Set and Clear of several I/O lines in a single write
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10. Peripherals
10.1 User Interface
The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 20.
10.2
Identifiers
Table 10-1 defines the Peripheral Identifiers. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller.
Table 10-1.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
AT91SAM9263 Peripheral Identifiers
Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC to PIOE reserved reserved US0 US1 US2 MCI0 MCI1 CAN TWI SPI0 SPI1 SSC0 SSC1 AC97C TC0, TC1, TC2 PWMC EMAC reserved 2DGE UDP ISI LCDC DMA reserved UHP AIC AIC USB Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 2D Graphic Engine USB Device Port Image Sensor Interface LCD Controller DMA Controller USART 0 USART 1 USART 2 Multimedia Card Interface 0 Multimedia Card Interface 1 CAN Controller Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 AC97 Controller Timer/Counter 0, 1 and 2 Pulse Width Modulation Controller Ethernet MAC Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C, D and E External Interrupt FIQ
Peripheral ID
Note:
Setting AIC, SYSC, UHP and IRQ0 - 1 bits in the clock set/clear registers of the PMC has no effect.
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10.2.1 10.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: * the SDRAM Controller * the Debug Unit * the Periodic Interval Timer * the Real-Time Timer * the Watchdog Timer * the Reset Controller * the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. Timer Counter Interrupts The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine. The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19 disables the clock of the 3 channels.
10.2.1.3
10.3
Peripherals Signals Multiplexing on I/O Lines
The AT91SAM9263 device features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns "Function" and "Comments" have been inserted in this table for the user's own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only may be duplicated within both tables. The column "Reset State" indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is specified, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is specified in the "Reset State" column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case.
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10.3.1
PIO Controller A Multiplexing Multiplexing on PIO Controller A
PIO Controller A Application Usage Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PCK0 IRQ0 IRQ1 EBI1_D16 EBI1_D17 EBI1_D18 EBI1_D19 EBI1_D20 EBI1_D21 EBI1_D22 EBI1_D23 EBI1_D24 EBI1_D25 EBI1_D26 EBI1_D27 EBI1_D28 EBI1_D29 EBI1_D30 EBI1_D31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments
Table 10-2.
I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
Peripheral A MCI0_DA0 MCI0_CDA
Peripheral B SPI0_MISO SPI0_MOSI SPI0_SPCK
MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI1_CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI0_CK CANTX CANRX TCLK2 MCI0_CDB MCI0_DB0 MCI0_DB1 MCI0_DB2 MCI0_DB3 MCI1_CDB MCI1_DB0 MCI1_DB1 MCI1_DB2 MCI1_DB3 TXD0 RXD0 RTS0 CTS0 SCK0 DMARQ0
SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS0 PCK2
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10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B
PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PWM2 TCLK0 PWM3 DMARQ3 Peripheral A AC97FS AC97CK AC97TX AC97RX TWD TWCK TF1 TK1 TD1 RD1 RK1 RF1 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 PCK1 TIOA2 TIOB2 Peripheral B TF0 TK0 TD0 RD0 RK0 RF0 DMARQ1 PWM0 PWM1 LCDCC PCK1 SPI0_NPCS3 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Application Usage Function Comments
Table 10-3.
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10.3.3
PIO Controller C Multiplexing Multiplexing on PIO Controller C
PIO Controller C Application Usage Reset State I/O I/O I/O PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ERXDV ECOL ERXCK TCLK1 PWM2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments
Table 10-4.
I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31
Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD
Peripheral B
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10.3.4 PIO Controller D Multiplexing Multiplexing on PIO Controller D
PIO Controller D I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 EBI0_NCS2 EBI0_A23 EBI0_A24 EBI0_A25_CFRNW EBI0_NCS3/NANDCS EBI0_D16 EBI0_D17 EBI0_D18 EBI0_D19 EBI0_D20 EBI0_D21 EBI0_D22 EBI0_D23 EBI0_D24 EBI0_D25 EBI0_D26 EBI0_D27 EBI0_D28 EBI0_D29 EBI0_D30 EBI0_D31 Peripheral A TXD1 RXD1 TXD2 RXD2 FIQ EBI0_NWAIT EBI0_NCS4/CFCS0 EBI0_NCS5/CFCS1 EBI0_CFCE1 EBI0_CFCE2 Peripheral B SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS2 SPI1_NPCS3 DMARQ2 RTS2 CTS2 RTS1 CTS1 SCK2 SCK1 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 Application Usage Function Comments
Table 10-5.
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10.3.5
PIO Controller E Multiplexing Multiplexing on PIO Controller E
PIO Controller E Application Usage Reset State I/O I/O I/O I/O I/O I/O I/O I/O TIOA1 TIOB1 PWM3 PCK3 ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TIOA0 TIOB0 EBI1_NWAIT ETXCK ECRS ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO EF100 EBI1_SDCKE EBI1_RAS EBI1_CAS EBI1_SDWE EBI1_SDA10 EBI1_NANDWE EBI1_NCS2/NANDCS EB1_NANDOE EBI1_NWR3/NBS3 EBI1_NCS1/SDCS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments
Table 10-6.
I/O Line PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31
Peripheral A ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC ISI_MCK
Peripheral B
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10.4
10.4.1
System Resource Multiplexing
LCD Controller The LCD Controller can interface with several LCD panels. It supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without limitation. Interfacing 24 bpp TFT panels prevents using the Ethernet MAC. 16 bpp TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD10. Using the peripheral B does not prevent using MAC lines. 16 bpp STN panels are interfaced through peripheral A and color data is output on LCDD0 to LCDD15, thus MAC lines can be used on peripheral B. Mapping the LCD signals on peripheral A and peripheral B makes is possible to use 24 bpp TFT panels in 24 bits (peripheral A) or 16 bits (peripheral B) by reprogramming the PIO controller and thus without hardware modification.
10.4.2
ETMTM Using the ETM prevents the use of the EBI0 in 32-bit mode. Only 16-bit mode (EBI0_D0 to EBI0_D15) is available, makes EBI0 unable to interface CompactFlash and NandFlash cards, reduces EBI0's address bus width which makes it unable to address memory ranges bigger than 0x7FFFFF and finally it makes impossible to use EBI0_NCS2.
10.4.3
EBI1 Using the following features prevents using EBI1 in 32-bit mode: * the second slots of MCI0 and/or MCI1 * USART0 * DMA request 0 (DMARQ0)
10.4.4
SSC Using SSC0 prevents using the AC97 Controller and Two-wire Interface. Using SSC1 prevents using DMA Request 1, PWM0, PWM1, LCDCC and PCK1.
10.4.5
USART Using USART2 prevents using EBI0's NWAIT signal, Chip Select 4 and CompactFlash Chip Enable 2. Using USART1 prevents using EBI0's Chip Select 5 and CompactFlash Chip Enable1.
10.4.6
NAND Flash Using the NAND Flash interface prevents using NCS3, NCS6 and NCS7 to access other parallel devices.
10.4.7
CompactFlash Using the CompactFlash interface prevents using NCS4 and/or NCS5 to access other parallel devices.
10.4.8
SPI0 and MCI Interface SPI0 signals and MCI0 signals are multiplexed, as the DataFlash Card is hardware-compatible with the SDCard. Only one can be used at a time.
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10.4.9
Interrupts Using IRQ0 prevents using the CAN controller. Using FIQ prevents using DMA Request 2.
10.4.10
Image Sensor Interface Using ISI in 8-bit data mode prevents using timers TIOA1, TIOB1. Using ISI in extended mode (up to 12 bits) prevents using keyboard row lines.
10.4.11
Timers Using TC0 prevents using columns 1 and 2 of the Keyboard Interface. Using TIOA2 and TIOB2, in this order, prevents using SPI1's Chip Selects [2-3].
10.5
10.5.1
Embedded Peripherals Overview
Serial Peripheral Interface * Supports communication with serial external devices - Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to MCK - The chip select line may be left active to speed up transfers on the same device
10.5.2
Two-wire Interface * Master Mode only * Compatibility with standard two-wire serial memory * One, two or three bytes for slave address * Sequential read/write operations
10.5.3
USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
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- Parity generation and error detection - Framing error detection, overrun error detection - MSB- or LSB-first - Optional break generation and detection - By 8 or by-16 over-sampling receiver frequency - Hardware handshaking RTS-CTS - Receiver time-out and transmitter timeguard - Optional Multi-drop Mode with address generation and detection - Optional Manchester Encoding * RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * IrDA modulation and demodulation - Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo 10.5.4 Serial Synchronous Controller * Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) * Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.5.5 AC97 Controller * Compatible with AC97 Component Specification V2.2 * Can interface with a single analog front end * Three independent RX Channels and three independent TX Channels - One RX and one TX channel dedicated to the AC97 analog front end control - One RX and one TX channel for data transfers, associated with a PDC - One RX and one TX channel for data transfers with no PDC * Time Slot Assigner that can assign up to 12 time slots to a channel * Channels support mono or stereo up to 20-bit sample length - Variable sampling rate AC97 Codec Interface (48 kHz and below) 10.5.6 Timer Counter * Three 16-bit Timer Counter Channels * Wide range of functions including: - Frequency Measurement
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- Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels 10.5.7 Pulse Width Modulation Controller * 4 channels, one 16-bit counter per channel * Common clock generator, providing thirteen different clocks - Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs * Independent channel programming - Independent Enable Disable commands - Independent clock selection - Independent period and duty cycle, with double bufferization - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform 10.5.8 Multimedia Card Interface * Two double-channel Multimedia Card Interfaces, allowing concurrent transfers with 2 cards * Compatibility with MultiMediaCard Specification Version 2.2 * Compatibility with SD Memory Card Specification Version 1.0 * Compatibility with SDIO Specification Version V1.0. * Cards clock rate up to Master Clock divided by 2 * Embedded power management to slow down clock rate when not used * Each MCI has two slots, each supporting - One slot for one MultiMediaCard bus (up to 30 cards) or - One SD Memory Card * Support for stream, block and multi-block data read and write 10.5.9 CAN Controller * Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers * Bit rates up to 1Mbit/s. * Object-oriented mailboxes, each with the following properties: - CAN Specification 2.0 Part A or 2.0 Part B programmable for each message - Object Configurable as receive (with overwrite or not) or transmit
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- Local Tag and Mask Filters up to 29-bit Identifier/Channel - 32 bits access to Data registers for each mailbox data object - Uses a 16-bit time stamp on receive and transmit message - Hardware concatenation of ID unmasked bitfields to speedup family ID processing - 16-bit internal timer for Time Stamping and Network synchronization - Programmable reception buffer length up to 16 mailbox object - Priority Management between transmission mailboxes - Autobaud and listening mode - Low power mode and programmable wake-up on bus activity or by the application - Data, Remote, Error and Overload Frame handling 10.5.10 USB Host Port * Compliant with Open HCI Rev 1.0 Specification * Compliant with USB V2.0 full-speed and low-speed specification * Supports both low-speed 1.5 Mbps and full-speed 12 Mbps devices * Root hub integrated with two downstream USB ports * Two embedded USB transceivers * Supports power management * Operates as a master on the matrix 10.5.11 USB Device Port * USB V2.0 full-speed compliant, 12 Mbits per second * Embedded USB V2.0 full-speed transceiver * Embedded 2,432-byte dual-port RAM for endpoints * Suspend/Resume logic * Ping-pong mode (two memory banks) for isochronous and bulk endpoints * Six general-purpose endpoints - Endpoint 0 and 3: 64 bytes, no ping-pong mode - Endpoint 1 and 2: 64 bytes, ping-pong mode - Endpoint 4 and 5: 512 bytes, ping-pong mode 10.5.12 LCD Controller * Single and Dual scan color and monochrome passive STN LCD panels supported * Single scan active TFT LCD panels supported * 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported * Up to 24-bit single scan TFT interfaces supported * Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays * 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN * 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN * 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT * Single clock domain architecture * Resolution supported up to 2048x2048
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* 2D DMA Controller for management of virtual Frame Buffer - Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer * Automatic resynchronization of the frame buffer pointer to prevent flickering 10.5.13 2D Graphics Controller * Acts as one Matrix Master * Commands are passed through the APB User Interface * Operates directly in the frame buffer of the LCD Controller - Line draw - Block transfer - Polygon fill - Clipping * Commands queuing through a FIFO 10.5.14 Ethernet 10/100 MAC * Compatibility with IEEE Standard 802.3 * 10 and 100 Mbits per second data throughput capability * Full- and half-duplex operations * MII or RMII interface to the physical layer * Register Interface to address, data, status and control registers * DMA Interface, operating as a master on the Memory Controller * Interrupt generation to signal receive and transmit completion * 28-byte transmit and 28-byte receive FIFOs * Automatic pad and CRC generation on transmitted frames * Address checking logic to recognize four 48-bit addresses * Support promiscuous mode where all valid frames are copied to memory * Support physical layer management through MDIO interface control of alarm and update time/calendar data in 10.5.15 Image Sensor Interface * ITU-R BT. 601/656 8-bit mode external interface support * Support for ITU-R BT.656-4 SAV and EAV synchronization * Vertical and horizontal resolutions up to 2048 x 2048 * Preview Path up to 640*480 * Support for packed data formatting for YCbCr 4:2:2 formats * Preview scaler to generate smaller size image * Programmable frame capture rate
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11. ARM926EJ-S Processor Overview
11.1 Overview
The ARM926EJ-S processor is a member of the ARM9s family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: * an ARM9EJ-STM integer core * a Memory Management Unit (MMU) * separate instruction and data AMBATM AHB bus interfaces * separate instruction and data TCM interfaces
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11.2
Block Diagram
Figure 11-1. ARM926EJ-S Internal Functional Block Diagram
ARM926EJ-S
TCM Interface Coprocessor Interface ETM Interface DEXT
Droute
Data AHB Interface
AHB
DCACHE Bus Interface Unit
WDATA
RDATA
ARM9EJ-S
DA
MMU
EmbeddedICE -RT
Processor
IA
Instruction AHB Interface
AHB
INSTR ICE Interface
ICACHE Iroute
IEXT
11.3
11.3.1
ARM9EJ-S Processor
ARM9EJ-STM Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: * ARM state: 32-bit, word-aligned ARM instructions. * THUMB state: 16-bit, halfword-aligned Thumb instructions. * Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words.
11.3.2
Switching State The operating state of the ARM9EJ-S core can be switched between: * ARM state and THUMB state using the BX and BLX instructions, and loads to the PC
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* ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 11.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 11.3.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 11.3.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 11.3.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: * User mode is the usual ARM program execution state. It is used for executing most application programs * Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process
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* Interrupt (IRQ) mode is used for general-purpose interrupt handling * Supervisor mode is a protected mode for the operating system * Abort mode is entered after a data or instruction prefetch abort * System mode is a privileged user mode for the operating system * Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 11.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers: * 31 general-purpose 32-bit registers * 6 32-bit status registers Table 11-1 shows all the registers in all modes. Table 11-1.
User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC
ARM9TDMI(R) Modes and Registers Layout
Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABORT
CPSR SPSR_UNDEF
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
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The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are generalpurpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: * constraints on the use of registers * stack conventions * argument passing and result return The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: * Eight general-purpose registers r0-r7 * Stack pointer, SP * Link register, LR (ARM r14) * PC * CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 11.3.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: * hold information about the most recently performed ALU operation * control the enabling and disabling of interrupts * set the processor operation mode
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Figure 11-2. Status Register Format
31 30 29 28 27 24 765 0
NZCVQ
J
Reserved
I FT
Mode
Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than
Mode bits Thumb state bit FIQ disable IRQ disable
Figure 11-2 shows the status register format, where: * N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags * The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. * The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: - J = 0: The processor is in ARM or Thumb state, depending on the T bit - J = 1: The processor is in Jazelle state. * Mode: five bits to encode the current processor mode 11.3.7.2 Exceptions Exception Types and Priorities
The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are:
* Fast interrupt (FIQ) * Normal interrupt (IRQ) * Data and Prefetched aborts (Abort) * Undefined instruction (Undefined) * Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: * Reset (highest priority) * Data Abort * FIQ * IRQ * Prefetch Abort * BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) 50
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The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: - ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). - THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place.
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11.3.8
ARM Instruction Set Overview The ARM instruction set is divided into: * Branch instructions * Data processing instructions * Status register transfer instructions * Load and Store instructions * Coprocessor instructions * Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 11-2 gives the ARM instruction mnemonic list. Table 11-2.
Mnemonic
MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP
ARM Instruction Mnemonic List
Operation
Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word STRH STRB STRBT STRT STM SWPB Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte
Mnemonic
MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR
Operation
Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word
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Table 11-2.
Mnemonic
MCR LDC CDP
ARM Instruction Mnemonic List (Continued)
Operation
Move To Coprocessor Load To Coprocessor Coprocessor Data Processing
Mnemonic
MRC STC
Operation
Move From Coprocessor Store From Coprocessor
11.3.9
New ARM Instruction Set . Table 11-3.
Mnemonic
BXJ BLX (1) SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB
New ARM Instruction Mnemonic List
Operation
Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double
Mnemonic
MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ
Operation
Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes
Notes:
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
11.3.10
Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: * Branch instructions * Data processing instructions * Load and Store instructions * Load and Store multiple instructions * Exception-generating instruction
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Table 5 shows the Thumb instruction set. Table 11-4 gives the Thumb instruction mnemonic list. Table 11-4.
Mnemonic
MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC
Thumb Instruction Mnemonic List
Operation
Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch
Mnemonic
MVN ADC SBC CMN NEG BIC ORR LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT
Operation
Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint
11.4
CP15 Coprocessor
Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: * ARM9EJ-S * Caches (ICache, DCache and write buffer) * TCM * MMU * Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5.
Table 11-5.
Register 0 0 0
CP15 Registers
Name ID Code
(1) (1)
Read/Write Read/Unpredictable Read/Unpredictable Read/Unpredictable
Cache type
TCM status(1)
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Table 11-5.
Register 1 2 3 4 5 5 6 7 8 9 9 10 11 12 13 13 14 Notes:
CP15 Registers
Name Control Translation Table Base Domain Access Control Reserved Data fault Status(1) Instruction fault status Fault Address Cache Operations TLB operations cache lockdown TCM region TLB lockdown Reserved Reserved FCSE PID
(1) (2) (1)
Read/Write Read/write Read/write Read/write None Read/write Read/write Read/write Read/Write Unpredictable/Write Read/write Read/write Read/write None None Read/write Read/Write None
Context ID(1) Reserved
15 Test configuration Read/Write 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field.
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11.4.1
CP15 Registers Access CP15 registers can only be accessed in privileged mode by: * MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. * MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is:
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
The MCR, MRC instructions bit pattern is shown below:
31
30
29
28
27
26
25
24
cond
23 22 21 20
1
19
1
18
1
17
0
16
opcode_1
15 14 13
L
12 11 10
CRn
9 8
Rd
7 6 5 4
1
3
1
2
1
1
1
0
opcode_2
1
CRm
* CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. * opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. * Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. * CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. * L: Instruction Bit 0 = MCR instruction 1 = MRC instruction * opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. * cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B.
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11.5 Memory Management Unit (MMU)
The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS(R), WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. Table 11-6. Mapping Details
Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte -
Mapping Name Section Large Page Small Page Tiny Page
The MMU consists of: * Access control logic * Translation Look-aside Buffer (TLB) * Translation table walk hardware 11.5.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page).
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11.5.2
Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory.
11.5.3
Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B.
11.5.4
MMU Faults The MMU generates an abort on the following types of faults: * Alignment faults (for data accesses only) * Translation faults * Domain faults * Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B.
11.6
Caches and Write Buffer
The ARM926EJ-S contains a 16 KB Instruction Cache (ICache), a 16 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement.
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A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 11.6.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 11.6.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables.
11.6.2.1
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The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 11.6.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory.
11.7
11.7.1
Tightly-Coupled Memory Interface
TCM Description The ARM926EJ-S processor features a Tightly-Coupled Memory (TCM) interface, which enables separate instruction and data TCMs (ITCM and DTCM) to be directly reached by the processor. TCMs are used to store real-time and performance critical code, they also provide a DMA support mechanism. Unlike AHB accesses to external memories, accesses to TCMs are fast and deterministic and do not incur bus penalties. The user has the possibility to independently configure each TCM size with values within the following ranges, [0KB, 64 KB] for ITCM size and [0KB, 64 KB] for DTCM size. TCMs can be configured by two means: HMATRIX TCM register and TCM region register (register 9) in CP15 and both steps should be performed. HMATRIX TCM register sets TCM size whereas TCM region register (register 9) in CP15 maps TCMs and enables them. The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools.
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11.7.2 Enabling and Disabling TCMs Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register. Then enabling TCMs is performed by using TCM region register (register 9) in CP15. The user should use the same sizes as those put in HMATRIX TCM register. For further details and programming tips, please refer to chapter 2.3 in ARM926EJ-S TRM, ref. DDI0222B. TCM Mapping The TCMs can be located anywhere in the memory map, with a single region available for ITCM and a separate region available for DTCM. The TCMs are physically addressed and can be placed anywhere in physical address space. However, the base address of a TCM must be aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is performed by using TCM region register (register 9) in CP15. The user should input the right mapping address for TCMs.
11.7.3
11.8
Bus Interface Unit
The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: * It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. * Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. * The arbitration becomes effective when more than one master wants to access the same slave simultaneously.
11.8.1
Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.
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Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 11-7.
HBurst[2:0]
Supported Transfers
Description Single transfer of word, half word, or byte:
* data write (NCNB, NCB, WT, or WB that has missed in DCache)
SINGLE Single transfer
* data read (NCNB or NCB) * NC instruction fetch (prefetched and non-prefetched) * page table walk read
Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill
INCR4 INCR8 WRAP8
Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst
11.8.2
Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries.
11.8.3
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12. AT91SAM9263 Debug and Test
12.1 Description
The AT91SAM9263 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, halfrate clock mode, counters, sequencer and FIFO. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.
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12.2
Block Diagram
Figure 12-1. Debug and Test Block Diagram
TMS TCK TDI
NTRST ICE/JTAG TAP JTAGSEL TDO
Boundary Port
RTCK
Reset and Test
POR TST
TPK0-TPK15
PIO
TPS0-TPS2 TSYNC
ARM9EJ-S
ICE-RT
ETM
2 ARM926EJ-S
TCLK
DTXD PDC DBGU DRXD
TAP: Test Access Port
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12.3
12.3.1
Application Examples
Debug Environment Figure 12-2 on page 65 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface.
Figure 12-2. Application Debug and Trace Environment Example
Host Debugger ICE/JTAG Interface Trace Port Interface
ICE/JTAG Connector
Trace Connector
NADIA2
RS232 Connector
Terminal
AT91SAM9263-based Application
12.3.2
Test Environment Figure 12-3 on page 65 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the "board in test" is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain.
Figure 12-3. Application Test Environment Example
Test Adaptor
Tester
JTAG Interface
ICE/JTAG Connector
Chip n
Chip 2
NADIA2
Chip 1
AT91SAM9263-based Application Board In Test
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12.4 Debug and Test Pin Description
Table 12-1.
Pin Name
Debug and Test Pin List
Function Reset/Test Type Active Level
NTRST NRST TST
Test Reset Signal Microcontroller Reset Test Mode Select ICE and JTAG
Input Input/Output Input
Low Low High
TCK TDI TDO TMS RTCK JTAGSEL
Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection ETM
Input Input Output Input Output Input
TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15
Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Debug Unit
Output Output Output Output
DRXD DTXD
Debug Receive Data Debug Transmit Data
Input Output
12.5
12.5.1
Functional Description
Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.
12.5.2
Embedded In-circuit Emulator The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system.
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There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the Embedded ICE-RT. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 12.5.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 12.5.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9263 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width.
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For further details on the Debug Unit, see the Debug Unit section. 12.5.5 Embedded Trace Macrocell The AT91SAM9263 features an Embedded Trace Macrocell (ETM), which is closely connected to the ARM926EJ-S Processor. The Embedded Trace is a standard Medium+ level implementation and contains the following resources: * Four pairs of address comparators * Two data comparators * Eight memory map decoder inputs * Two 16-bits counters * One 3-stage sequencer * Four external inputs * One external output * One 45-byte FIFO The Embedded Trace Macrocell of the AT91SAM9263 works in half-rate clock mode and thus integrates a clock divider. This allows the maximum frequency of all the trace port signals not to exceed one half of the ARM926EJ-S clock speed. The Embedded Trace Macrocell input and output resources are not used in the AT91SAM9263. The Embedded Trace is a real-time trace module with the capability of tracing the ARM9EJ-S instruction and data. For further details on Embedded Trace Macrocell, see the ARM documents: * ETM9 (Rev2p2) Technical Reference Manual (DDI 0157F) * Embedded Trace Macrocell Specification (IHI 0014J) 12.5.5.1 Trace Port The Trace Port is made up of the following pins: * TSYNC - the synchronization signal (Indicates the start of a branch sequence on the trace packet port.) * TCLK - the Trace Port clock, half-rate of the ARM926EJ-S processor clock. * TPS0 to TPS2 - indicate the processor state at each trace clock edge. * TPK0 to TPK15 - the Trace Packet data value. The trace packet information (address, data) is associated with the processor state indicated by TPS. Some processor states have no additional data associated with the Trace Packet Port (i.e. failed condition code of an instruction). The packet is 8-bits wide, and up to two packets can be output per cycle.
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Figure 12-4. ETM9 Block
TPS-TPS0 ARM926EJ-S Bus Tracker Trace Control FIFO TPK15-TPK0 TSYNC
Trace Enable, View Data
TAP Controller
Trigger, Sequencer, Counters
Scan Chain 6 ETM9
TMS TCK
12.5.5.2
Implementation Details This section gives an overview of the Embedded Trace resources.
Three-state Sequencer The sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. The sate transition is controlled with internal events. If the user needs multiple-stage trigger schemes, the trigger event is based on a sequencer state. Address Comparator In single mode, address comparators compare either the instruction address or the data address against the user-programmed address. In range mode, the address comparators are arranged in pairs to form a virtual address range resource. Details of the address comparator programming are: * The first comparator is programmed with the range start address. * The second comparator is programmed with the range end address. * The resource matches if the address is within the following range: - (address > = range start address) AND (address < range end address) * Unpredictable behavior occurs if the two address comparators are not configurated in the same way. Data Comparator Each full address comparator is associated with a specific data comparator. A data comparator is used to observe the data bus only when load and store operations occur. A data comparator has both a value register and a mask register, therefore it is possible to compare only certain bits of a preprogrammed value against the data bus.
TDO
TDI
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Memory Decoder Inputs The eight memory map decoder inputs are connected to custom address decoders. The address decoders divide the memory into regions of on-chip SRAM, on-chip ROM, and peripherals. The address decoders also optimize the ETM9 trace trigger. Table 12-2. ETM Memory Map Inputs Layout
Area Internal Internal Internal Internal External External Internal Internal Access Type Data Fetch Data Fetch Data Fetch Data Data Start Address 0x0000 0000 0x0000 0000 0x0040 0000 0x0040 0000 0x1000 0000 0x1000 0000 0xF000 0000 0xFFFF C000 End Address 0x002F FFFF 0x002F FFFF 0x004F FFFF 0x004F FFFF 0x9FFF FFFF 0x9FFF FFFF 0xFFFF BFFF 0xFFFF FFFF
Product Resource SRAM SRAM ROM ROM External Bus Interface External Bus Interface User Peripherals System Peripherals
FIFO A 45-byte FIFO is used to store data tracing. The FIFO is used to separate the pipeline status from the trace packet. So, the FIFO can be used to buffer trace packets. A FIFO overflow is detected by the embedded trace macrocell when the FIFO is full or when the FIFO has less bytes than the user-programmed number. Half-rate Clocking Mode The ETM9 is implemented in half-rate mode that allows both rising and falling edge data tracing of the trace clock. The half-rate mode is implemented to maintain the signal clock integrity of high speed systems (up to 100 MHz). Figure 12-5. Half-rate Clocking Mode
ARM920T Clock
Trace Clock
TraceData
Half-rate Clocking Mode
Care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality.
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12.5.5.3 Application Board Restriction The TCLK signal needs to be set with care, some timing parameters are required. See "ETM Timings" for more details. The specified target system connector is the AMP Mictor connector. The connector must be oriented on the application board as described below in Figure 12-6. The view of the PCB is shown from above with the trace connector mounted near the edge of the board. This allows the Trace Port Analyzer to minimize the physical intrusiveness of the interconnected target. Figure 12-6. AMP Mictor Connector Orientation
NADIA2-based Application Board 38 37
2
1
Pin 1Chamfer
12.5.6
IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.
12.5.6.1
JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 664 bits that correspond to active pins and associated control signals. Each AT91SAM9263 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-3.
Bit Number 663 662 661 PA19 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 660 659 658 657 656 655 654 653 652 651 650 649 648 647 646 645 644 643 642 641 640 639 638 637 636 635 634 633 632 631 630 629 628
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PA20 IN/OUT OUTPUT CONTROL INPUT PA21 IN/OUT OUTPUT CONTROL INPUT PA22 IN/OUT OUTPUT CONTROL INPUT PA23 IN/OUT OUTPUT CONTROL INPUT PA24 IN/OUT OUTPUT CONTROL INPUT PA25 IN/OUT OUTPUT CONTROL INPUT PA26 IN/OUT OUTPUT CONTROL INPUT PA27 IN/OUT OUTPUT CONTROL INPUT PA28 IN/OUT OUTPUT CONTROL INPUT PA29 IN/OUT OUTPUT CONTROL INPUT PA30 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 627 626 625 624 623 622 EBI1_A1_NWR2 621 620 619 618 617 616 615 614 613 612 611 610 609 608 607 606 605 604 603 602 601 600 599 598 597 596 595 594 EBI1_NWR_NWR0 593 IN/OUT OUTPUT EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A[15:8] EBI1_A9 EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15 EBI1_A16_BA0 EBI1_A[22:16] EBI1_A17 EBI1_A18 EBI1_A19 EBI1_A20 EBI1_A21 EBI1_A22 EBI1_NCS0 EBI1_NCS0/EBI1_NRD/EBI1_NWR_NWR0/ EBI1_NWR_NWR1 EBI1_NRD OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT IN/OUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT INPUT EBI1_A0_NBS0 EBI1_A[7:0] OUT PA31 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL OUTPUT CONTROL INPUT
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Table 12-3.
Bit Number 592
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name EBI1_NWR_NWR1 Pin Type IN/OUT OUTPUT INPUT EBI1_D0 IN/OUT OUTPUT CONTROL INPUT EBI1_D1 IN/OUT OUTPUT CONTROL INPUT EBI1_D2 IN/OUT OUTPUT CONTROL INPUT EBI1_D3 IN/OUT OUTPUT CONTROL INPUT EBI1_D4 IN/OUT OUTPUT CONTROL INPUT EBI1_D5 IN/OUT OUTPUT CONTROL INPUT EBI1_D6 IN/OUT OUTPUT CONTROL INPUT EBI1_D7 IN/OUT OUTPUT CONTROL INPUT EBI1_D8 IN/OUT OUTPUT CONTROL INPUT EBI1_D9 IN/OUT OUTPUT CONTROL INPUT EBI1_D10 IN/OUT OUTPUT CONTROL Associated BSR Cells INPUT
591 590 589 588 587 586 585 584 583 582 581 580 579 578 577 576 575 574 573 572 571 570 569 568 567 566 565 564 563 562 561 560 559 558
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Table 12-3.
Bit Number 557 556 555 554 553 552 551 550 549 548 547 546 545 544 543 542 541 540 539 538 537 536 535 534 533 532 531 530 529 528 527 526 525 PE26 IN/OUT PE24 IN/OUT PE23 IN/OUT PE22 IN/OUT PE21 IN/OUT PE20 IN/OUT EBI1_D15 IN/OUT EBI1_D14 IN/OUT EBI1_D13 IN/OUT EBI1_D12 IN/OUT EBI1_D11 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 524 523 522 521 520 519 518 517 516 515 514 513 512 511 510 509 508 507 506 505 504 503
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PE25 IN/OUT OUTPUT CONTROL INPUT PE27 IN/OUT OUTPUT CONTROL internal internal internal INPUT PE28 IN/OUT OUTPUT CONTROL INPUT PE29 IN/OUT OUTPUT CONTROL INPUT PE30 IN/OUT OUTPUT CONTROL INPUT PE31 IN/OUT OUTPUT CONTROL OUTPUT RTCK OUT CONTROL INPUT PA0 IN/OUT OUTPUT CONTROL INPUT PA1 IN/OUT OUTPUT CONTROL INPUT PA2 IN/OUT OUTPUT CONTROL INPUT PA3 IN/OUT OUTPUT CONTROL
502 501 500 499 498 497 496 495 494 493 492 491 490
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Table 12-3.
Bit Number 489 488 487 486 485 484 483 482 481 480 479 478 477 476 475 474 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 PA14 IN/OUT PA13 IN/OUT PA12 IN/OUT PA11 IN/OUT PA10 IN/OUT PA9 IN/OUT PA8 IN/OUT PA7 IN/OUT PA6 IN/OUT PA5 IN/OUT PA4 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 432 431 430 429 428 427 426 425 424
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PA15 IN/OUT OUTPUT CONTROL INPUT PB0 IN/OUT OUTPUT CONTROL INPUT PB1 IN/OUT OUTPUT CONTROL INPUT PB2 IN/OUT OUTPUT CONTROL INPUT PB3 IN/OUT OUTPUT CONTROL INPUT PB4 IN/OUT OUTPUT CONTROL INPUT PB5 IN/OUT OUTPUT CONTROL INPUT PB6 IN/OUT OUTPUT CONTROL INPUT PB7 IN/OUT OUTPUT CONTROL INPUT PB8 IN/OUT OUTPUT CONTROL INPUT PB9 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 404 403 402 401 400 399 398 397 396 395 394 393 392 391 PB20 IN/OUT PB19 IN/OUT PB18 IN/OUT PB17 IN/OUT PB16 IN/OUT PB15 IN/OUT PB14 IN/OUT PB13 IN/OUT PB12 IN/OUT PB11 IN/OUT PB10 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PB21 IN/OUT OUTPUT CONTROL INPUT PB22 IN/OUT OUTPUT CONTROL INPUT PB23 IN/OUT OUTPUT CONTROL INPUT PB24 IN/OUT OUTPUT CONTROL INPUT PB25 IN/OUT OUTPUT CONTROL INPUT PB26 IN/OUT OUTPUT CONTROL INPUT PB27 IN/OUT OUTPUT CONTROL INPUT PB28 IN/OUT OUTPUT CONTROL INPUT PB29 IN/OUT OUTPUT CONTROL INPUT PB30 IN/OUT OUTPUT CONTROL INPUT PB31 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 PC10 IN/OUT PC9 IN/OUT PC8 IN/OUT PC7 IN/OUT PC6 IN/OUT PC5 IN/OUT PC4 IN/OUT PC3 IN/OUT PC2 IN/OUT PC1 IN/OUT PC0 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PC11 IN/OUT OUTPUT CONTROL INPUT PC12 IN/OUT OUTPUT CONTROL INPUT PC13 IN/OUT OUTPUT CONTROL INPUT PC14 IN/OUT OUTPUT CONTROL INPUT PC15 IN/OUT OUTPUT CONTROL INPUT PC16 IN/OUT OUTPUT CONTROL INPUT PC17 IN/OUT OUTPUT CONTROL INPUT PC18 IN/OUT OUTPUT CONTROL INPUT PC19 IN/OUT OUTPUT CONTROL INPUT PC20 IN/OUT OUTPUT CONTROL INPUT PC21 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 PD0 IN/OUT PC31 IN/OUT PC30 IN/OUT PC29 IN/OUT PC28 IN/OUT PC27 IN/OUT PC26 IN/OUT PC25 IN/OUT PC24 IN/OUT PC23 IN/OUT PC22 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PD1 IN/OUT OUTPUT CONTROL INPUT PD2 IN/OUT OUTPUT CONTROL INPUT PD3 IN/OUT OUTPUT CONTROL INPUT PD4 IN/OUT OUTPUT CONTROL PPS EBI0_A0_NBS0 EBI0_A[7:0] EBI0_A1_NBS2_NWR2 IN/OUT OUTPUT EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 EBI0_A[15:8] EBI0_A9 EBI0_A10 EBI0_SDA10 EBI0_SDA10/SDCKE/RAS/CAS/ SDWE/NANDOE/NANDWE EBI0_A11 EBI0_A12 EBI0_A13 EBI0_A14 EBI0_A15 EBI0_A16_BA0 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUT OUT OUTPUT OUTPUT CONTROL INPUT
242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224
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Table 12-3.
Bit Number 223 222 221 220 219 218 217 216 215 214 213 212 EBI0_NWR_NWR0 211 210 EBI0_NBS1_NWR1 209 208 EBI0_NBS3_NWR3 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 EBI0_D2 IN/OUT EBI0_D1 IN/OUT EBI0_D0 IN/OUT EBI0_SDCK EBI0_RAS EBI0_CAS EBI0_SDWE EBI0_NANDOE EBI0_NANDWE internal internal internal OUT OUT OUT OUT OUT OUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL IN/OUT OUTPUT IN/OUT OUTPUT INPUT IN/OUT OUTPUT INPUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name EBI0_A[22:16] EBI0_A17_BA1 EBI0_A18 EBI0_A19 EBI0_A20 EBI0_A21 EBI0_A22 EBI0_NCS0 EBI0_NCS0/EBI0_NCS1_SDCS/EBI0_NRD/ EBI0_NWR_NWR0/EBI0_NBS1_NWR1/EBI0_NBS3_NWR3 EBI0_NCS1_SDCS EBI0_NRD OUT OUT OUT OUT OUT OUT OUT OUT OUT Pin Type Associated BSR Cells CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT INPUT
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Table 12-3.
Bit Number 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT EBI0_D3 IN/OUT OUTPUT CONTROL INPUT EBI0_D4 IN/OUT OUTPUT CONTROL INPUT EBI0_D5 IN/OUT OUTPUT CONTROL INPUT EBI0_D6 IN/OUT OUTPUT CONTROL INPUT EBI0_D7 IN/OUT OUTPUT CONTROL INPUT EBI0_D8 IN/OUT OUTPUT CONTROL INPUT EBI0_D9 IN/OUT OUTPUT CONTROL INPUT EBI0_D10 IN/OUT OUTPUT CONTROL INPUT EBI0_D11 IN/OUT OUTPUT CONTROL INPUT EBI0_D12 IN/OUT OUTPUT CONTROL INPUT EBI0_D13 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 PD13 IN/OUT PD11 IN/OUT PD10 IN/OUT PD9 IN/OUT PD8 IN/OUT PD7 IN/OUT PD12 IN/OUT PD6 IN/OUT PD5 IN/OUT EBI0_D15 IN/OUT EBI0_D14 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PD14 IN/OUT OUTPUT CONTROL INPUT PD15 IN/OUT OUTPUT CONTROL INPUT PD16 IN/OUT OUTPUT CONTROL INPUT PD17 IN/OUT OUTPUT CONTROL INPUT PD18 IN/OUT OUTPUT CONTROL INPUT PD19 IN/OUT OUTPUT CONTROL INPUT PD20 IN/OUT OUTPUT CONTROL INPUT PD21 IN/OUT OUTPUT CONTROL INPUT PD22 IN/OUT OUTPUT CONTROL INPUT PD23 IN/OUT OUTPUT CONTROL INPUT PD24 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 PE3 IN/OUT PE2 IN/OUT PE1 IN/OUT PE0 IN/OUT PD31 IN/OUT PD30 IN/OUT PD29 IN/OUT PD28 IN/OUT PD27 IN/OUT PD26 IN/OUT PD25 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 12-3.
Bit Number 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT PE4 IN/OUT OUTPUT CONTROL INPUT PE5 IN/OUT OUTPUT CONTROL INPUT PE6 IN/OUT OUTPUT CONTROL INPUT PE7 IN/OUT OUTPUT CONTROL INPUT PE8 IN/OUT OUTPUT CONTROL INPUT PE9 IN/OUT OUTPUT CONTROL INPUT PE10 IN/OUT OUTPUT CONTROL INPUT PE11 IN/OUT OUTPUT CONTROL INPUT PE12 IN/OUT OUTPUT CONTROL INPUT PE13 IN/OUT OUTPUT CONTROL INPUT PE14 IN/OUT OUTPUT CONTROL
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Table 12-3.
Bit Number 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 PA18 IN/OUT PA17 IN/OUT PA16 IN/OUT PE19 IN/OUT PE18 IN/OUT PE17 IN/OUT PE16 IN/OUT PE15 IN/OUT
AT91SAM9263 JTAG Boundary Scan Register (Continued)
Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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12.5.7
ID Code Register
Access: Read-only
31 30 29 28 27 26 25 24
VERSION
23 22 21 20 19
PART NUMBER
18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER
7 6 5 4 3
MANUFACTURER IDENTITY
2 1 0
MANUFACTURER IDENTITY
1
* MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0_C03F. * PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B0C * VERSION[31:28]: Product Version Number Set to 0x0.
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13. AT91SAM9263 Boot Program
13.1 Description
The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the SD Card is not formatted or if boot.bin file is not found, NANDFlash Boot program is then executed. First, as for SD Card Boot part, it looks for a boot.bin file in the root directory of a FAT12/16/32 formatted NANDFlash. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the NANDFlash is not formatted, the NANDFlash Boot program looks for a sequence of seven valid ARM exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, the DataFlash(R) Boot program is executed. It looks for a sequence of seven valid ARM exception vectors in a DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no boot.bin file is found, SAM-BATM Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port.
13.2
Flow Diagram
The Boot Program implements the algorithm in Figure 13-1.
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Figure 13-1. Boot Program Algorithm Flow Diagram
Start
Main Oscillator Bypass Yes
No
Enable Main Oscillator
Input Frequency Table
SD Card Boot
Yes
Download from SD Card (MCI)
Run
SD Card Boot
No
Timeout < 1 s
NandFlash Boot
Yes
Download from NandFlash
Run
NandFlash Boot
No
Timeout < 1 s
SPI DataFlash Boot
Yes
Download from DataFlash (NPCS0)
Run
DataFlash Boot
No
Timeout < 1 s
No
USB Enumeration Successful ?
No
Character(s) received on DBGU ? SAM-BA Boot
Yes Run SAM-BA Boot
Yes Run SAM-BA Boot
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13.3 Device Initialization
Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. External Clock Detection 3. Switch Master Clock on Main Oscillator 4. C variable initialization 5. Main oscillator frequency detection 6. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. Table 13-1 defines the crystals supported by the Boot Program. Table 13-1.
3.0 4.433619 6.0 7.3728 11.05920 14.7456
Crystals Supported by Software Auto-detection (MHz)
3.2768 4.608 6.144 7.864320 12.0 16.0 3.6864 4.9152 6.4 8.0 12.288 17.734470 3.84 5.0 6.5536 9.8304 13.56 18.432 4.0 5.24288 7.159090 10.0 14.31818 20.0
7. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) 8. Enable the User Reset 9. Jump to SD Card Boot sequence. If SD Card Boot succeeds, perform a remap and jump to 0x0. 10. Jump to NANDFlash Boot sequence. If NANDFlash Boot succeeds, perform a remap and jump to 0x0. 11. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 12. Activation of the Instruction Cache 13. Jump to SAM-BA Boot sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port Figure 13-2. Remap Action after Download Completion
0x0000_0000 Internal ROM REMAP 0x0030_0000 Internal SRAM Internal ROM 0x0040_0000 Internal SRAM 0x0000_0000
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13.4 DataFlash Boot
The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. After reset, the code in internal ROM is mapped at both addresses 0x0000_0000 and 0x0010_0000:
400000 400004 400008 40000c 400010 400014 400018 40001c ea000006 eafffffe ea00002f eafffffe eafffffe eafffffe eafffffe eafffffe B B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 0x1c 00 04 08 0c 10 14 18 1c ea000006 eafffffe ea00002f eafffffe eafffffe eafffffe eafffffe eafffffe B B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 0x1c
13.4.1
Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see "Structure of ARM Vector 6" on page 96).
Figure 13-3. LDR Opcode
31 1 1 1 28 27 0 1 1 I 24 23 P U 1 W 20 19 0 Rn 16 15 Rd 12 11 0
Figure 13-4. B Opcode
31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0
Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: - Rn = Rd = PC = 0xF - I==1 - P==1 - U offset added (U==1) or subtracted (U==0) - W==1 13.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below.
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Figure 13-5. Structure of the ARM Vector 6
31 Size of the code to download in bytes 0
13.4.2.1
Example An example of valid vectors follows:
00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18
<- Code size = 4660 bytes
The size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct vector for his application. 13.4.3 DataFlash Boot Sequence The DataFlash boot program performs device initialization followed by the download procedure. The DataFlash boot program supports all Atmel DataFlash devices. Table 13-2 summarizes the parameters to include in the ARM vector 6 for all devices. Table 13-2.
Device AT45DB011B AT45DB021B AT45DB041B AT45DB081B AT45DB161B AT45DB321B AT45DB642
DataFlash Device
Density 1 Mbit 2 Mbits 4 Mbits 8 Mbits 16 Mbits 32 Mbits 64 Mbits Page Size (bytes) 264 264 264 264 528 528 1056 Number of Pages 512 1024 2048 4096 4096 8192 8192
The DataFlash has a Status Register that determines all the parameters required to access the device. The DataFlash boot is configured to be compatible with the future design of the DataFlash.
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Figure 13-6. Serial DataFlash Download
Start
Send status command
Is status OK ?
No
Jump to next boot solution
Yes Read the first 7 instructions (28 bytes). Decode the sixth ARM vector
7 vectors (except vector 6) are LDR or Branch instruction
No
Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6)
Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application
End
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13.5 SD Card Boot
The SD Card Boot program searches for a valid application in the SD Card memory. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If a valid file is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a secondlevel bootloader.
13.6
NANDFlash Boot
The NANDFlash Boot program searches for a valid application in the NANDFlash memory. First, it looks for a boot.bin file in the root directory of a FAT12/16/32 formatted NANDFlash. If a valid file is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a secondlevel bootloader. If NANDFlash is not formatted, the NANDFlash Boot program searches for a valid application in the NANDFlash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See "DataFlash Boot" on page 96 for more information on Valid Image Detection.
13.6.1
Supported NANDFlash Devices Any 8 or 16-bit NANDFlash devices are supported.
13.7
SAM-BA Boot
If no valid DataFlash device has been found during the DataFlash boot sequence, the SAMBA boot program is performed. The SAM-BA boot principle is to: - Check if USB Device enumeration has occured. - Check if character(s) have been received on the DBGU. - Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as in Table 13-3. Table 13-3.
Command O o H h W w S R G V
Commands Available through the SAM-BA Boot
Action write a byte read a byte write a half word read a half word write a word read a word send a file receive a file go display version Argument(s) Address, Value# Address,# Address, Value# Address,# Address, Value# Address,# Address,# Address, NbOfBytes# Address# No argument Example O200001,CA# o200001,# H200002,CAFE# h200002,# W200000,CAFEDECA# w200000,# S200000,# R200000,1234# G200200# V#
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* Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. - Address: Address in hexadecimal. - Value: Byte, halfword or word to write in hexadecimal. - Output: `>'. * Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. - Address: Address in hexadecimal - Output: The byte, halfword or word read in hexadecimal following by `>' * Send a file (S): Send a file to a specified address - Address: Address in hexadecimal - Output: `>'.
Note: There is a time-out on this command which is reached when the prompt `>' appears before the end of the command execution.
* Receive a file (R): Receive data into a file from a specified address - Address: Address in hexadecimal - NbOfBytes: Number of bytes in hexadecimal to receive - Output: `>' * Go (G): Jump to a specified address and execute the code - Address: Address to jump in hexadecimal - Output: `>' * Get Version (V): Return the SAM-BA boot version - Output: `>' 13.7.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 13.7.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: <255-blk #><--128 data bytes--> in which: - = 01 hex - = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) - <255-blk #> = 1's complement of the blk#. - = 2 bytes CRC16 Figure 13-7 shows a transmission using this protocol.
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Figure 13-7. Xmodem Transfer Example
Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device
13.7.3
USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows(R), from Windows 98SE to Windows XP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel's vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document "USB Basic Application", literature number 6123, for more details.
13.7.3.1
Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 13-4.
Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION
Handled Standard Requests
Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value.
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Table 13-4.
Request GET_STATUS SET_FEATURE CLEAR_FEATURE
Handled Standard Requests (Continued)
Definition Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature.
The device also handles some class requests defined in the CDC class. Table 13-5.
Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE
Handled Class Requests
Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present.
Unhandled requests are STALLed. 13.7.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response.
13.8
Hardware and Software Constraints
* The SD Card, NANDFlash and DataFlash downloaded code size must be inferior to 72 K bytes. * The code is always downloaded from the DataFlash or NANDFlash device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). * The downloaded code must be position-independent or linked at address 0x0000_0000. * The DataFlash must be connected to NPCS0 of the SPI. * USB requirements: - Crystal or Input Frequencies supported by Software Auto-detection. See Table 131 on page 95 for more informations. The MCI, the SPI and NandFlash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between peripherals output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 13-6 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found.
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For the DataFlash driven by the SPCK signal at 8 MHz, the time to download 72 KBytes is reduced to 200 ms. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 13-6.
Peripheral MCI1 MCI1 MCI1 MCI1 MCI1 MCI1 SPI0 SPI0 SPI0 SPI0 PIOD DBGU DBGU
Pins Driven during Boot Program Execution
Pin MCCK MCCDA MCDA0 MCDA1 MCDA2 MCDA3 MOSI MISO SPCK NPCS0 NANDCS DRXD DTXD PIO Line PIOA6 PIOA7 PIOA8 PIOA9 PIOA10 PIOA11 PIOA1 PIOA0 PIOA2 PIOA5 PIOD15 PIOC30 PIOC31
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14. Reset Controller (RSTC)
14.1 Description
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.
14.2
Block Diagram
Figure 14-1. Reset Controller Block Diagram
Reset Controller
Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset
user_reset
NRST
nrst_out
NRST Manager
exter_nreset
periph_nreset
backup_neset WDRPROC wd_fault
SLCK
14.3
14.3.1
Functional Description
Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: * proc_nreset: Processor reset line. It also resets the Watchdog Timer. * backup_nreset: Affects all the peripherals powered by VDDBU. * periph_nreset: Affects the whole set of embedded peripherals. * nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
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The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 14.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager.
Figure 14-2. NRST Manager
RSTC_MR RSTC_SR
URSTIEN rstc_irq
RSTC_MR
URSTS NRSTL
Other interrupt sources user_reset
URSTEN
NRST
RSTC_MR
ERSTL nrst_out External Reset Timer exter_nreset
14.3.2.1
NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
14.3.2.2
NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the "nrst_out" signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 s and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.
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As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 14.3.3 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 14.3.3.1 General Reset A general reset occurs when VDDBU is powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remains valid for 2 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shut down. Figure 14-3 shows how the General Reset affects the reset signals. Figure 14-3. General Reset State
SLCK MCK Backup Supply POR output
Any Freq.
Startup Time
backup_nreset
Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset
XXX
0x0 = General Reset
XXX
NRST (nrst_out)
EXTERNAL RESET LENGTH = 2 cycles
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14.3.3.2
Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 2 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The "nrst_out" remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR.
Figure 14-4. Wake-up State
SLCK MCK Main Supply POR output
Any Freq.
backup_nreset
Resynch. 2 cycles Processor Startup = 3 cycles
proc_nreset
RSTTYP
XXX
0x1 = WakeUp Reset
XXX
periph_nreset
NRST (nrst_out)
EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1)
Figure 14-5. 14.3.3.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
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When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-6. User Reset State
SLCK MCK
Any Freq.
NRST
Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset
NRST (nrst_out)
>= EXTERNAL RESET LENGTH
14.3.3.4
Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: * PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. * PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. * EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.
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If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset
SLCK MCK
Any Freq.
Write RSTC_CR
Resynch. 1 cycle Processor Startup = 3 cycles
proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
Any
XXX
0x3 = Software Reset
SRCMP in RSTC_SR
14.3.3.5
Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: * If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. * If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
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Figure 14-8. Watchdog Reset
SLCK MCK
Any Freq.
wd_fault
Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
14.3.4
Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: * Backup Reset * Wake-up Reset * Watchdog Reset * Software Reset * User Reset Particular cases are listed below: * When in User Reset: - A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. - A software reset is impossible, since the processor reset is being activated. * When in Software Reset: - A watchdog event has priority over the current state. - The NRST has no effect. * When in Watchdog Reset: - The processor reset is active and so a Software Reset cannot be programmed. - A User Reset cannot be entered.
14.3.5
Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields:
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* RSTTYP field: This field gives the type of the last reset, as explained in previous sections. * SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. * NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. * URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-9. Reset Controller Status and Interrupt
MCK read RSTC_SR
Peripheral Access
2 cycle resynchronization NRST NRSTL
2 cycle resynchronization
URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1)
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14.4 Reset Controller (RSTC) User Interface
Reset Controller (RSTC) Register Mapping
Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Value
Table 14-1.
Offset 0x00 0x04 0x08 Note:
1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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14.4.1 Reset Controller Control Register Register Name: RSTC_CR Access Type:
31
Write-only
30 29 28 KEY 27 26 25 24
23 - 15 - 7 -
22 - 14 - 6 -
21 - 13 - 5 -
20 - 12 - 4 -
19 - 11 - 3 EXTRST
18 - 10 - 2 PERRST
17 - 9
16 - 8 - 0 PROCRST
1 -
* PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. * PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. * EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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14.4.2 Reset Controller Status Register Register Name: RSTC_SR Access Type:
31 - 23 - 15 - 7 -
Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 25 - 17 SRCMP 9 RSTTYP 1 24 - 16 NRSTL 8
2 -
0 URSTS
* URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. * RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low
* NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). * SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy.
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14.4.3 Reset Controller Mode Register Register Name: RSTC_MR Access Type:
31
Read/Write
30 29 28 KEY 27 26 25 24
23 - 15 - 7 -
22 - 14 - 6 -
21 - 13 - 5
20 - 12 - 4 URSTIEN
19 - 11
18 - 10 ERSTL
17 - 9
16
8
3 -
2 -
1 -
0 URSTEN
* URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. * URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. * ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 s and 2 seconds. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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15. Real-time Timer (RTT)
15.1 Overview
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value.
15.2
Block Diagram
Figure 15-1. Real-time Timer
RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm
15.3
Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.
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The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register).
Figure 15-2. RTT Counting
APB cycle APB cycle
MCK
RTPRES - 1 Prescaler 0
RTT
0
...
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface
read RTT_SR
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15.4
15.4.1
Real-time Timer (RTT) User Interface
Register Mapping Real-time Timer Register Mapping
Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000
Table 15-1.
Offset 0x00 0x04 0x08 0x0C
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15.4.2
Real-time Timer Mode Register RTT_MR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RTPRES 7 6 5 4 RTPRES 3 2 1 0 27 - 19 - 11 26 - 18 RTTRST 10 25 - 17 RTTINCIEN 9 24 - 16 ALMIEN 8
Register Name: Access Type:
31 - 23 - 15
* RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 RTPRES 0: The prescaler period is equal to RTPRES. * ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. * RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. * RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
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15.4.3 Real-time Timer Alarm Register RTT_AR Read/Write
30 29 28 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.4 Real-time Timer Value Register RTT_VR Read-only
30 29 28 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
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15.4.5
Real-time Timer Status Register RTT_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RTTINC 24 - 16 - 8 - 0 ALMS
Register Name: Access Type:
31 - 23 - 15 - 7 -
* ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occured since the last read of RTT_SR. 1 = The Real-time Alarm occured since the last read of RTT_SR. * RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
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16. Periodic Interval Timer (PIT)
16.1 Overview
The Periodic Interval Timer (PIT) provides the operating system's scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.
16.2
Block Diagram
Figure 16-1. Periodic Interval Timer
PIT_MR
PIV
=?
PIT_MR
PITIEN
set
0
PIT_SR
PITS
reset
pit_irq
0
0
1
0
1
12-bit Adder
read PIT_PIVR
MCK
20-bit Counter
Prescaler
MCK/16
CPIV
PIT_PIVR
PICNT
CPIV
PIT_PIIR
PICNT
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16.3
Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state.
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Figure 16-2. Enabling/Disabling PIT with PITEN
APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle
CPIV PICNT PITS (PIT_SR) APB Interface
0
1 0
PIV - 1
PIV 1
0 0
1
read PIT_PIVR
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16.4
Periodic Interval Timer (PIT) User Interface
Periodic Interval Timer (PIT) Register Mapping
Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000
Table 16-1.
Offset 0x00 0x04 0x08 0x0C
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16.4.1 Periodic Interval Timer Mode Register PIT_MR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PIV 7 6 5 4 PIV 3 2 1 0 27 - 19 26 - 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16
Register Name: Access Type:
31 - 23 - 15
* PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). * PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. * PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 16.4.2 Periodic Interval Timer Status Register PIT_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 PITS
Register Name: Access Type:
31 - 23 - 15 - 7 -
* PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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16.4.3
Periodic Interval Timer Value Register PIT_PIVR Read-only
30 29 28 PICNT 23 22 PICNT 15 14 13 12 CPIV 7 6 5 4 CPIV 3 2 1 0 11 10 21 20 19 18 CPIV 9 8 17 16 27 26 25 24
Register Name: Access Type:
31
Reading this register clears PITS in PIT_SR. * CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
16.4.4
Periodic Interval Timer Image Register PIT_PIIR Read-only
30 29 28 PICNT 23 22 PICNT 15 14 13 12 CPIV 7 6 5 4 CPIV 3 2 1 0 11 10 21 20 19 18 CPIV 9 8 17 16 27 26 25 24
Register Name: Access Type:
31
* CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. * PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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17. Watchdog Timer (WDT)
17.1 Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.
17.2
Block Diagram
Figure 17-1. Watchdog Timer Block Diagram
write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV
12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK
<= WDD WDT_MR WDRSTEN =0 wdt_fault (to Reset Controller) wdt_int
set set read WDT_SR or reset WDERR reset WDUNF reset WDFIEN WDT_MR
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17.3
Functional Description
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz). After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires. The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters. In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the "wdt_fault" signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR). To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR. Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the "wdt_fault" signal to the Reset Controller is asserted. Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal). The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal "wdt_fault" to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset. If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the "wdt_fault" signal to the reset controller is deasserted. Writing the WDT_MR reloads and restarts the down counter. While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.
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Figure 17-2. Watchdog Behavior
Watchdog Error Watchdog Underflow if WDRSTEN is 1 FFF Normal behavior WDV Forbidden Window WDD Permitted Window 0 WDT_CR = WDRSTT if WDRSTEN is 0
Watchdog Fault
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17.4
Watchdog Timer (WDT) User Interface
Watchdog Timer Registers
Register Control Register Mode Register Status Register Name WDT_CR WDT_MR WDT_SR Access Write-only Read/Write Once Read-only Reset Value 0x3FFF_2FFF 0x0000_0000
Table 17-1.
Offset 0x00 0x04 0x08
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17.4.1 Watchdog Timer Control Register Register Name: WDT_CR Access Type:
31 30
Write-only
29 28 KEY 27 26 25 24
23 - 15 - 7 -
22 - 14 - 6 -
21 - 13 - 5 -
20 - 12 - 4 -
19 - 11 - 3 -
18 - 10 - 2 -
17 - 9 - 1 -
16 - 8 - 0 WDRSTT
* WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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17.4.2 Watchdog Timer Mode Register Register Name: WDT_MR Access Type:
31 30
Read/Write Once
29 WDIDLEHLT 21 28 WDDBGHLT 20 WDD 27 26 WDD 19 18 17 16 25 24
23
22
15 WDDIS 7
14 WDRPROC 6
13 WDRSTEN 5
12 WDFIEN 4 WDV
11
10 WDV
9
8
3
2
1
0
* WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. * WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt. 1: A Watchdog fault (underflow or error) asserts interrupt. * WDRSTEN: Watchdog Reset Enable 0: A Watchdog fault (underflow or error) has no effect on the resets. 1: A Watchdog fault (underflow or error) triggers a Watchdog reset. * WDRPROC: Watchdog Reset Processor 0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets. 1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset. * WDD: Watchdog Delta Value Defines the permitted range for reloading the Watchdog Timer. If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer. If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error. * WDDBGHLT: Watchdog Debug Halt 0: The Watchdog runs when the processor is in debug state. 1: The Watchdog stops when the processor is in debug state. * WDIDLEHLT: Watchdog Idle Halt 0: The Watchdog runs when the system is in idle mode. 1: The Watchdog stops when the system is in idle state. * WDDIS: Watchdog Disable 0: Enables the Watchdog Timer. 1: Disables the Watchdog Timer.
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17.4.3 Watchdog Timer Status Register Register Name: WDT_SR Access Type:
31 - 23 - 15 - 7 -
Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 WDERR 24 - 16 - 8 - 0 WDUNF
* WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR. * WDERR: Watchdog Error 0: No Watchdog error occurred since the last read of WDT_SR. 1: At least one Watchdog error occurred since the last read of WDT_SR.
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18. Shutdown Controller (SHDWC)
18.1 Description
The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines.
18.2
Block Diagram
Figure 18-1. Shutdown Controller Block Diagram
SLCK
Shutdown Controller
SYSC_SHMR read SYSC_SHSR reset
CPTWK0 WKMODE0 WKUP0
WAKEUP0 SYSC_SHSR
set
read SYSC_SHSR
Wake-up
reset
RTTWKEN RTT Alarm
SYSC_SHMR
RTTWK
set
SYSC_SHSR
Shutdown Output Controller
SYSC_SHCR
SHDN
SHDW
Shutdown
18.3
I/O Lines Description
Table 18-1.
Name WKUP0 SHDN
I/O Lines Description
Description Wake-up 0 input Shutdown output Type Input Output
18.4
18.4.1
Product Dependencies
Power Management The Shutdown Controller is continuously clocked by Slow Clock. The Power Management Controller has no effect on the behavior of the Shutdown Controller.
18.5
Functional Description
The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN.
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A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system. The software is able to control the pin SHDN by writing the Shutdown Control Register (SHDW_CR) with the bit SHDW at 1. The shutdown is taken into account only 2 slow clock cycles after the write of SHDW_CR. This register is password-protected and so the value written should contain the correct key for the command to be taken into account. As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). The transition detector can be programmed to detect either a positive or negative transition or any level change on WKUP0. The detection can also be disabled. Programming is performed by defining WKMODE0. Moreover, a debouncing circuit can be programmed for WKUP0. The debouncing circuit filters pulses on WKUP0 shorter than the programmed number of 16 SLCK cycles in CPTWK0 of the SHDW_MR register. If the programmed level change is detected on a pin, a counter starts. When the counter reaches the value programmed in the corresponding field, CPTWK0, the SHDN pin is released. If a new input change is detected before the counter reaches the corresponding value, the counter is stopped and cleared. WAKEUP0 of the Status Register (SHDW_SR) reports the detection of the programmed events on WKUP0, with a reset after the read of SHDW_SR.
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18.6
18.6.1
Shutdown Controller (SHDWC) User Interface
Register Mapping Shutdown Controller (SHDWC) Registers
Register Shutdown Control Register Shutdown Mode Register Shutdown Status Register Name SHDW_CR SHDW_MR SHDW_SR Access Write-only Read-Write Read-only Reset Value 0x0000_0103 0x0000_0000
Table 18-2.
Offset 0x00 0x04 0x18
18.6.2 Shutdown Control Register Register Name: SHDW_CR Access Type:
31
Write-only
30 29 28 KEY 27 26 25 24
23 - 15 - 7 -
22 - 14 - 6 -
21 - 13 - 5 -
20 - 12 - 4 -
19 - 11 - 3 -
18 - 10 - 2 -
17 - 9 - 1 -
16 - 8 - 0 SHDW
* SHDW: Shutdown Command 0 = No effect. 1 = If KEY is correct, asserts the SHDN pin. * KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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18.6.3 Shutdown Mode Register Register Name: SHDW_MR Access Type:
31 - 23 - 15
Read/Write
30 - 22 - 14 - 29 - 21 - 13 28 - 20 - 12 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 WKMODE0 0 24 - 16 RTTWKEN 8
7
6 CPTWK0
5
4
* WKMODE0: Wake-up Mode 0
WKMODE[1:0] 0 0 1 1 0 1 0 1 Wake-up Input Transition Selection None. No detection is performed on the wake-up input Low to high level High to low level Both levels change
* CPTWK0: Counter on Wake-up 0 Defines the number of 16 Slow Clock cycles, the level detection on the corresponding input pin shall last before the wakeup event occurs. Because of the internal synchronization of WKUP0 , the SHDN pin is released (CPTWK x 16 + 1) Slow Clock cycles after the event on WKUP. * RTTWKEN: Real-time Timer Wake-up Enable 0 = The RTT Alarm signal has no effect on the Shutdown Controller. 1 = The RTT Alarm signal forces the de-assertion of the SHDN pin.
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18.6.4 Shutdown Status Register Register Name: SHDW_SR Access Type:
31 - 23 - 15 - 7 -
Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 RTTWK 8 - 0 WAKEUP0
* WAKEUP0: Wake-up 0 Status 0 = No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. 1 = At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. * RTTWK: Real-time Timer Wake-up 0 = No wake-up alarm from the RTT occurred since the last read of SHDW_SR. 1 = At least one wake-up alarm from the RTT occurred since the last read of SHDW_SR.
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19. AT91SAM9263 Bus Matrix
19.1 Description
Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 9 AHB Masters to 8 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus and provides a Chip Configuration User Interface with Registers that allow the Bus Matrix to support application specific features.
19.2
Memory Mapping
Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible. The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that allows to perform remap action for every master independently.
19.3
Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus granting mechanism allows to set a default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master and fixed default master.
19.3.1
No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master, suits low power mode. Last Access Master At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to itsfixed default master. Unlike last access master, the fixed master doesn't change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG). To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that allow to set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field allows to choose the default master type (no default, last access master, fixed default master) whereas the 4-bit
19.3.2
19.3.3
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FIXED_DEFMSTR field allows to choose a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description.
19.4
Arbitration
The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, allowing to arbitrate each slave differently. The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and this for each slave: 1. Round-Robin Arbitration (the default) 2. Fixed Priority Arbitration This choice is given through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG). Each algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration has to be done, it is realized only under some specific conditions detailed in the following paragraph.
19.4.1
Arbitration rules Each arbiter has the ability to arbitrate between two or more different master's requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: when a slave is currently doing a single access. 3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst (See "Undefined Length Burst Arbitration" on page iv.). 4. Slot Cycle Limit: when the slot cycle counter has reach the limit value indicating that the current master access is too long and must be broken (See "Slot Cycle Limit Arbitration" on page iv.).
19.4.1.1
Undefined Length Burst Arbitration In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as for defined length burst transfer, which is selected between the following: 1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer. 3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.
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4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG). 19.4.1.2 Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word transfer. Round-Robin Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master's requests arise at the same time, the master with the lowest number is first serviced then the others are serviced in a round-robin manner. There are three round-robin algorithm implemented: * Round-Robin arbitration without default master * Round-Robin arbitration with last access master * Round-Robin arbitration with fixed default master 19.4.2.1 Round-Robin Arbitration without Default Master This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. Round-Robin Arbitration with Last Access Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is pending, the slave remains connected to the last master that performs the access. Other non privileged masters will still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses.
19.4.2
19.4.2.2
19.4.2.3
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19.4.3
Fixed Priority Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master's requests are active at the same time, the master with the highest priority number is serviced first. If two or more master's requests with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and MATRIX_PRBS).
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19.5 Bus Matrix User Interface
Register Mapping
Register Master Configuration Register 0 Master Configuration Register 1 Master Configuration Register 2 Master Configuration Register 3 Master Configuration Register 4 Master Configuration Register 5 Master Configuration Register 6 Master Configuration Register 7 Master Configuration Register 8 Reserved Slave Configuration Register 0 Slave Configuration Register 1 Slave Configuration Register 2 Slave Configuration Register 3 Slave Configuration Register 4 Slave Configuration Register 5 Slave Configuration Register 6 Slave Configuration Register 7 Reserved Priority Register A for Slave 0 Priority Register B for Slave 0 Priority Register A for Slave 1 Priority Register B for Slave 1 Priority Register A for Slave 2 Priority Register B for Slave 2 Priority Register A for Slave 3 Priority Register B for Slave 3 Priority Register A for Slave 4 Priority Register B for Slave 4 Priority Register A for Slave 5 Priority Register B for Slave 5 Priority Register A for Slave 6 Priority Register B for Slave 6 Priority Register A for Slave 7 Priority Register B for Slave 7 Name MATRIX_MCFG0 MATRIX_MCFG1 MATRIX_MCFG2 MATRIX_MCFG3 MATRIX_MCFG4 MATRIX_MCFG5 MATRIX_MCFG6 MATRIX_MCFG7 MATRIX_MCFG8 - MATRIX_SCFG0 MATRIX_SCFG1 MATRIX_SCFG2 MATRIX_SCFG3 MATRIX_SCFG4 MATRIX_SCFG5 MATRIX_SCFG6 MATRIX_SCFG7 - MATRIX_PRAS0 MATRIX_PRBS0 MATRIX_PRAS1 MATRIX_PRBS1 MATRIX_PRAS2 MATRIX_PRBS2 MATRIX_PRAS3 MATRIX_PRBS3 MATRIX_PRAS4 MATRIX_PRBS4 MATRIX_PRAS5 MATRIX_PRBS5 MATRIX_PRAS6 MATRIX_PRBS6 MATRIX_PRAS7 MATRIX_PRBS7 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write - Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write - Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - 0x00010010 0x00050010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 - 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
Table 19-1.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020
0x0024 - 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 - 0x007C 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC
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Table 19-1.
Offset 0x00C0 - 0x00FC 0x0100 0x0104 - 0x010C
Register Mapping
Register Reserved Master Remap Control Register Reserved Name - MATRIX_MRCR - Access - Read/Write - Reset Value - 0x00000000 -
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19.5.1 Bus Matrix Master Configuration Registers MATRIX_MCFG0...MATRIX_MCFG8 Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 ULBT 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* ULBT: Undefined Length Burst Type 0: Infinite Length Burst No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. 1: Single Access The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst. 2: Four-beat Burst The undefined length burst is split into four-beat burst allowing rearbitration at each four-beat burst end. 3: Eight-beat Burst The undefined length burst is split into eight-beat burst allowing rearbitration at each eight-beat burst end. 4: Sixteen-beat Burst The undefined length burst is split into sixteen-beat burst allowing rearbitration at each sixteen-beat burst end.
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19.5.2 Bus Matrix Slave Configuration Registers MATRIX_SCFG0...MATRIX_SCFG7 Read/Write
30 - 22 29 - 21 28 - 20 27 - 19 26 - 18 17 25 ARBT 16 24
Register Name: Access Type:
31 - 23 - 15 - 7
FIXED_DEFMSTR 14 - 6 13 - 5 12 - 4 SLOT_CYCLE 11 - 3 10 - 2
DEFMSTR_TYPE 9 - 1 8 - 0
* SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave. This limit has been placed to avoid locking a very slow slave when very long bursts are used. Note that an unreasonably small value breaks every burst and the Bus Matrix then arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. * DEFMASTR_TYPE: Default Master Type 0: No Default Master At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one-cycle latency for the first acccess of a burst transfer or for a single access. 1: Last Default Master At the end of current slave access, if no other master request is pending, the slave remains connected to the last master that accessed it. This results in not having the one cycle latency when the last master tries access to the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number of which has been written in the FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master tries access to the slave again. * FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0. * ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration 2: Reserved 3: Reserved
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19.5.3 Bus Matrix Priority Registers A For Slaves MATRIX_PRAS0...MATRIX_PRAS7 Read/Write
30 - 22 - 14 - 6 - 5 M1PR 13 M3PR 4 21 M5PR 12 29 M7PR 20 28 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 1 M0PR 9 M2PR 0 17 M4PR 8 25 M6PR 16 24
Register Name: Access Type:
31 - 23 - 15 - 7 -
* MxPR: Master x Priority Fixed prority of Master x for accessing to the selected slave.The higher the number, the higher the priority. 19.5.4 Bus Matrix Priority Registers B For Slaves MATRIX_PRBS0...MATRIX_PRBS7 Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 M8PR 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* M8PR: Master 8 Priority Fixed prority of Master 8 for accessing to the selected slave. The higher the number, the higher the priority.
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19.5.5 Bus Matrix Master Remap Control Register MATRIX_MRCR Read/Write 0x0000_0000
31 - 23 - 15 - 7 RCB7 30 - 22 - 14 - 6 RCB6 29 - 21 - 13 - 5 RCB5 28 - 20 - 12 - 4 RCB4 27 - 19 - 11 - 3 RCB3 26 - 18 - 10 - 2 RCB2 25 - 17 - 9 - 1 RCB1 24 - 16 - 8 RCB8 0 RCB0
Register Name: Access Type: Reset:
* RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master. 1: Enable remapped address decoding for the selected Master.
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19.6 Chip Configuration User Interface
Chip Configuration User Interface
Register Reserved Bus Matrix TCM Configuration Register Reserved EBI0 Chip Select Assignment Register EBI1 Chip Select Assignment Register Reserved Name - MATRIX_TCMR - EBI0_CSA EBI1_CSA - Access - Read/Write - Read/Write Read/Write - Reset Value - 0x00000000 - 0x00010000 0x00010000 -
Table 19-2.
Offset 0x0110 0x0114
0x0118 - 0x011C 0x0120 0x0124 0x0128 - 0x01FC
19.6.1
Bus Matrix TCM Configuration Register MATRIX_TCR Read/Write 0x0000_0000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 DTCM_SIZE 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 ITCM_SIZE 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type: Reset:
* ITCM_SIZE: Size of ITCM enabled memory block 0000: 0 KB (No ITCM Memory) 0101: 16 KB 0110: 32 KB Others: Reserved * DTCM_SIZE: Size of DTCM enabled memory block 0000: 0 KB (No DTCM Memory) 0101: 16 KB 0110: 32 KB Others: Reserved
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19.6.2 EBI0 Chip Select Assignment Register EBI0_CSA Read/Write 0x0001_0000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 EBI0_CS5A 28 - 20 - 12 - 4 EBI0_CS4A 27 - 19 - 11 - 3 EBI0_CS3A 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 EBI0_CS1A 24 - 16 VDDIOMSEL 8 EBI0_DBPUC 0 -
Register Name: Access Type: Reset:
* EBI0_CS1A: EBI0 Chip Select 1 Assignment 0 = EBI0 Chip Select 1 is assigned to the Static Memory Controller. 1 = EBI0 Chip Select 1 is assigned to the SDRAM Controller. * EBI0_CS3A: EBI0 Chip Select 3 Assignment 0 = EBI0 Chip Select 3 is only assigned to the Static Memory Controller and EBI0_NCS3 behaves as defined by the SMC. 1 = EBI0 Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. * EBI0_CS4A: EBI0 Chip Select 4 Assignment 0 = EBI0 Chip Select 4 is only assigned to the Static Memory Controller and EBI0_NCS4 behaves as defined by the SMC. 1 = EBI0 Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated. * EBI0_CS5A: EBI0 Chip Select 5 Assignment 0 = EBI0 Chip Select 5 is only assigned to the Static Memory Controller and EBI0_NCS5 behaves as defined by the SMC. 1 = EBI0 Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated. * EBI0_DBPUC: EBI0 Data Bus Pull-Up Configuration 0 = EBI0 D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM0 power supply. 1 = EBI0 D0 - D15 Data Bus bits are not internally pulled-up. * VDDIOMSEL: Memory voltage selection 0 = Memories are 1.8V powered. 1 = Memories are 3.3V powered.
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19.6.3 EBI1 Chip Select Assignment Register EBI1_CSA Read/Write 0x0001_0000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 EBI1_CS2A 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 EBI1_CS1A 24 - 16 VDDIOMSEL 8 EBI1_DBPUC 0 -
Register Name: Access Type: Reset:
* EBI1_CS1A: EBI1 Chip Select 1 Assignment 0 = EBI1 Chip Select 1 is assigned to the Static Memory Controller. 1 = EBI1 Chip Select 1 is assigned to the SDRAM Controller. * EBI1_CS2A: EBI1 Chip Select 2 Assignment 0 = EBI1 Chip Select 2 is only assigned to the Static Memory Controller and EBI1_NCS2 behaves as defined by the SMC. 1 = EBI1 Chip Select 2 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. * EBI1_DBPUC: EBI1 Data Bus Pull-Up Configuration 0 = EBI1 D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM1 power supply. 1 = EBI1 D0 - D15 Data Bus bits are not internally pulled-up. * VDDIOMSEL: Memory voltage selection 0 = Memories are 1.8V powered. 1 = Memories are 3.3V powered.
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20. External Bus Interface (EBI)
20.1 Description
The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM. The EBI0 also supports the CompactFlash and the NANDFlash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI0 handles data transfers with up to six external devices, each assigned to six address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to six chip select lines (NCS[5:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. The EBI1 also supports the NANDFlash protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI1 handles data transfers with up to three external devices, each assigned to three address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 23 bits, up to three chip select lines (NCS[2:0]) and several control pins that are generally multiplexed between the different external Memory Controllers.
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20.2
20.2.1
Block Diagram
External Bus Interface 0 Figure 20-1 shows the organization of the External Bus Interface 0.
Figure 20-1. Organization of the External Bus Interface 0
Bus Matrix
External Bus Interface 0
D[15:0] AHB SDRAM Controller A0/NBS0 A1/NWR2/NBS2 A[15:2], A[22:18] A16/BA0 Static Memory Controller MUX Logic A17/BA1 NCS0 NCS1/SDCS NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CompactFlash Logic SDCK SDCKE RAS CAS NAND Flash Logic SDWE SDA10 NANDOE NANDWE ECC Controller PIO Chip Select Assignor D[31:16] A[25:23] CFRNW NCS4/CFCS0 NCS5/CFCS1 NCS2 User Interface NWAIT CFCE1 CFCE2
Address Decoders
APB
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20.2.2 External Bus Interface 1 Figure 20-2 shows the organization of the External Bus Interface 1.
Figure 20-2. Organization of the External Bus Interface 1
Bus Matrix
External Bus Interface 1
AHB
SDRAM Controller D[15:0] Static Memory Controller MUX Logic A0/NBS0 A1/NWR2/NBS2 A[15:2], A[22:18] A16/BA0 A17/BA1 NCS0 NRD NWR0/NWE NWR1/NBS1
NAND Flash Logic
SDWE ECC Controller SDA10 NANDOE NANDWE D[31:16] PIO Chip Select Assignor NWR3/NBS3 NCS1/SDCS NCS2/NANDCS SDCK SDCKE User Interface NWAIT RAS CAS
Address Decoders
APB
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20.3 I/O Lines Description
EBI0 I/O Lines Description
Function EBI EBI0_D0 - EBI0_D31 EBI0_A0 - EBI0_A25 EBI0_NWAIT Data Bus Address Bus External Wait Signal SMC EBI0_NCS0 - EBI0_NCS5 EBI0_NWR0 - EBI0_NWR3 EBI0_NRD EBI0_NWE EBI0_NBS0 - EBI0_NBS3 Chip Select Lines Write Signals Read Signal Write Enable Byte Mask Signals EBI for CompactFlash Support EBI0_CFCE1 - EBI0_CFCE2 EBI0_CFOE EBI0_CFWE EBI0_CFIOR EBI0_CFIOW EBI0_CFRNW EBI0_CFCS0 - EBI0_CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash I/O Read Signal CompactFlash I/O Write Signal CompactFlash Read Not Write Signal CompactFlash Chip Select Lines EBI for NAND Flash Support EBI0_NANDCS EBI0_NANDOE EBI0_NANDWE NAND Flash Chip Select Line NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller EBI0_SDCK EBI0_SDCKE EBI0_SDCS EBI0_BA0 - EBI0_BA1 EBI0_SDWE EBI0_RAS - EBI0_CAS EBI0_NWR0 - EBI0_NWR3 EBI0_NBS0 - EBI0_NBS3 EBI0_SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line Bank Select SDRAM Write Enable Row and Column Signal Write Signals Byte Mask Signals SDRAM Address 10 Line Output Output Output Output Output Output Output Output Output Low Low Low Low High Low Output Output Output Low Low Low Output Output Output Output Output Output Output Low Low Low Low Low Low Output Output Output Output Output Low Low Low Low Low I/O Output Input Low Type Active Level
Table 20-1.
Name
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Table 20-2.
Name
EBI1 I/O Lines Description
Function EBI Type Active Level
EBI1_D0 - EBI1_D31 EBI1_A0 - EBI1_A23 EBI1_NWAIT
Data Bus Address Bus External Wait Signal SMC
I/O Output Input Low
EBI1_NCS0 - EBI1_NCS2 EBI1_NWR0 - EBI1_NWR3 EBI1_NRD EBI1_NWE EBI1_NBS0 - EBI1_NBS3
Chip Select Lines Write Signals Read Signal Write Enable Byte Mask Signals EBI for NAND Flash Support
Output Output Output Output Output
Low Low Low Low Low
EBI1_NANDCS EBI1_NANDOE EBI1_NANDWE
NAND Flash Chip Select Line NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller
Output Output Output
Low Low Low
EBI1_SDCK EBI1_SDCKE EBI1_SDCS EBI1_BA0 - EBI1_BA1 EBI1_SDWE EBI1_RAS - EBI1_CAS EBI1_NWR0 - EBI1_NWR3 EBI1_NBS0 - EBI1_NBS3 EBI1_SDA10
SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line Bank Select SDRAM Write Enable Row and Column Signal Write Signals Byte Mask Signals SDRAM Address 10 Line
Output Output Output Output Output Output Output Output Output Low Low Low Low High Low
The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment.
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Table 20-3 on page 162 details the connections between the two Memory Controllers and the EBI pins. Table 20-3. EBIx Pins and Memory Controllers I/O Lines Connections(1)
EBIx Pins(1) EBIx_NWR1/NBS1/CFIOR EBIx_A0/NBS0 EBIx_A1/NBS2/NWR2 EBIx_A[11:2] EBIx_SDA10 EBIx_A12 EBIx_A[14:13] EBIx_A[22:15] EBIx_A[25:23](2) EBIx_D[31:0] Note: 1. x indicates 0 or 1 2. Only for EBI0 SDRAMC I/O Lines NBS1 Not Supported Not Supported SDRAMC_A[9:0] SDRAMC_A10 Not Supported SDRAMC_A[12:11] Not Supported Not Supported D[31:0] SMC I/O Lines NWR1/NUB SMC_A0/NLB SMC_A1 SMC_A[11:2] Not Supported SMC_A12 SMC_A[14:13] SMC_A[22:15] SMC_A[25:23] D[31:0]
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20.4
20.4.1
Application Example
Hardware Interface Table 20-4 on page 163 details the connections to be applied between the EBI pins and the external devices for each Memory Controller. EBI Pins and External Static Devices Connections
Pins of the Interfaced Device
Table 20-4.
Signals: EBI0_, EBI1_ Controller
D0 - D7 D8 - D15 D16 - D23 D24 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A22 A23 - A25 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NRD/CFOE NWR0/NWE NWR1/NBS1 NWR3/NBS3
(5) (5) (5) (5)
8-bit Static Device
2 x 8-bit Static Devices
16-bit Static Device SMC
4 x 8-bit Static Devices
2 x 16-bit Static Devices
32-bit Static Device
D0 - D7 - - - A0 A1 A[2:22] A[23:25] CS CS CS CS CS CS OE WE - -
D0 - D7 D8 - D15 - - - A0 A[1:21] A[22:24] CS CS CS CS CS CS OE WE WE -
(1) (1)
D0 - D7 D8 - D15 - - NLB A0 A[1:21] A[22:24] CS CS CS CS CS CS OE WE NUB -
D0 - D7 D8 - D15 D16 - D23 D24 - D31 - WE(2) A[0:20] A[21:23] CS CS CS CS CS CS OE WE WE
(2) (2)
D0 - D7 D8 - 15 D16 - D23 D24 - D31 NLB
(3)
D0 - D7 D8 - 15 D16 - D23 D24 - D31 BE0(6) BE2(6) A[0:20] A[21:23] CS CS CS CS CS CS OE WE BE1(6) BE3(6)
NLB(4) A[0:20] A[21:23] CS CS CS CS CS CS OE WE NUB
(3)
WE(2)
NUB(4)
Notes:
1. 2. 3. 4. 5. 6.
NWR1 enables upper byte writes. NWR0 enables lower byte writes. NWRx enables corresponding byte x writes. (x = 0,1,2 or 3) NBS0 and NBS1 enable respectively lower and upper bytes of the lower 16-bit word. NBS2 and NBS3 enable respectively lower and upper bytes of the upper 16-bit word. EBI0 signals only BEx: Byte x Enable (x = 0,1,2 or 3)
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Table 20-5. EBI Pins and External Devices Connections
Pins of the Interfaced Device Signals: EBI0_, EBI1_ Controller
D0 - D7 D8 - D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21 A22 A23 - A24(4) A25
(4)
SDRAM SDRAMC
D0 - D7 D8 - D15 D16 - D31 DQM0 DQM2 A[0:8] A9 A10 - A[11:12] - BA0 BA1 - - - - - - CS -
(5) (4)
CompactFlash (EBI0 only)
CompactFlash True IDE Mode (EBI0 only) SMC
NAND Flash
D0 - D7 D8 - 15 - A0 A1 A[2:10] - - - - - - - - - REG - CFRNW - - - - - CFCS0 CFCS1 - - OE WE IOR IOW CE1 CE2
(1) (1) (1)
D0 - D7 D8 - 15 - A0 A1 A[2:10] - - - - - - - - - REG - CFRNW - - - - - CFCS0 CFCS1 - - - WE IOR IOW CS0 CS1
(1) (1) (1)
AD0-AD7 AD8-AD15 - - - - - - - - - - - - ALE(3) CLE(3) - - - - - - - - - OE WE - - - - - -
NCS0 NCS1/SDCS NCS2
(4)
NCS2/NANDCS NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 NANDOE
(4) (4) (4) (4)
- - - - - - - - DQM1 DQM3 - -
NANDWE
NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW CFCE1 CFCE2
(4) (4)
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Table 20-5. EBI Pins and External Devices Connections (Continued)
Pins of the Interfaced Device Signals: EBI0_, EBI1_ Controller
SDCK SDCKE RAS CAS SDWE NWAIT Pxx Pxx Pxx
(2) (2) (2)
SDRAM SDRAMC
CLK CKE RAS CAS WE - - - -
CompactFlash (EBI0 only)
CompactFlash True IDE Mode (EBI0 only) SMC
NAND Flash
- - - - - WAIT CD1 or CD2 - -
- - - - - WAIT CD1 or CD2 - -
- - - - - - - CE RDY
Note:
1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For details, see "NAND Flash Support" on page 172. 4. EBI0 signals only 5. EBI1 signals only
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20.4.2 Connection Examples Figure 20-3 shows an example of connections between the EBI and external devices.
Figure 20-3. EBI Connections to Memory Devices
EBI
D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE
D0-D7
2M x 8 SDRAM
D0-D7
D8-D15
2M x 8 SDRAM
D0-D7
CS CLK CKE SDWE WE RAS CAS DQM NBS0
A0-A9, A11 A10 BA0 BA1
A2-A11, A13 SDA10 A16/BA0 A17/BA1
CS CLK CKE SDWE WE RAS CAS DQM NBS1
A0-A9, A11 A10 BA0 BA1
A2-A11, A13 SDA10 A16/BA0 A17/BA1
SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25
D16-D23 NCS0 NCS1/SDCS NCS2 NCS3 NCS4 NCS5
D0-D7
2M x 8 SDRAM
D24-D31
2M x 8 SDRAM
D0-D7
CS CLK CKE SDWE WE RAS CAS DQM NBS2
A0-A9, A11 A10 BA0 BA1
A2-A11, A13 SDA10 A16/BA0 A17/BA1
CS CLK CKE SDWE WE RAS CAS DQM NBS3
A0-A9, A11 A10 BA0 BA1
A2-A11, A13 SDA10 A16/BA0 A17/BA1
128K x 8 SRAM
D0-D7 D0-D7 A0-A16 A1-A17 D8-D15
128K x 8 SRAM
D0-D7 A0-A16 A1-A17
CS OE NRD/NOE WE A0/NWR0/NBS0
CS OE NRD/NOE WE NWR1/NBS1
20.5
20.5.1
Product Dependencies
I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller.
20.6
Functional Description
The EBI transfers data between the internal AHB Bus (handled by the Bus Matrix) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control buses and is composed of the following elements: * the Static Memory Controller (SMC) * the SDRAM Controller (SDRAMC)
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* the ECC Controller (ECC) * a chip select assignment feature that assigns an AHB address space to the external devices * a multiplex controller circuit that shares the pins between the different Memory Controllers * programmable CompactFlash support logic (EBI0 only) * programmable NAND Flash support logic 20.6.1 Bus Multiplexing The EBI0 and EBI1 offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Controller without delaying the other external Memory Controller accesses. 20.6.2 Pull-up Control The EBI0_CSA and EBI1_CSA registers in the Chip Configuration User Interface permit enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the EBIx_DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16D31 lines can be performed by programming the appropriate PIO controller. 20.6.3 Static Memory Controller For information on the Static Memory Controller, refer to the Static Memory Controller section. SDRAM Controller For information on the SDRAM Controller, refer to the SDRAM section. ECC Controller For information on the ECC Controller, refer to the ECC section. 20.6.6 CompactFlash Support (EBI0 only) The External Bus Interface 0 integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 and/or NCS5 address space. Programming the EBI0_CS4A and/or EBI0_CS5A bit of the EBI0_CSA Register in the Chip Configuration User Interface to the appropriate value enables this logic. For details on this register, refer to the in the Bus Matrix Section. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 and/or NCS5 (i.e., between 0x5000 0000 and 0x5FFF FFFF for NCS4 and between 0x6000 0000 and 0x6FFF FFFF for NCS5). All CompactFlash modes (Attribute Memory, Common Memory, I/O and True IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and _ATA SEL (True IDE mode) are not handled.
20.6.4
20.6.5
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20.6.6.1 I/O Mode, Common Memory Mode, Attribute Memory Mode and True IDE Mode Within the NCS4 and/or NCS5 address space, the current transfer address is used to distinguish I/O mode, common memory mode, attribute memory mode and True IDE mode. The different modes are accessed through a specific memory mapping as illustrated on Figure 20-4. A[23:21] bits of the transfer address are used to select the desired mode as described in Table 20-6 on page 168.
Figure 20-4. CompactFlash Memory Mapping
True IDE Alternate Mode Space Offset 0x00E0 0000 True IDE Mode Space Offset 0x00C0 0000 CF Address Space Offset 0x0080 0000 Common Memory Mode Space Offset 0x0040 0000 Attribute Memory Mode Space Offset 0x0000 0000 I/O Mode Space
Note:
The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode).
Table 20-6.
A[23:21] 000 010 100 110 111
CompactFlash Mode Selection
Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode Alternate True IDE Mode
20.6.6.2
CFCE1 and CFCE2 Signals To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit data bus. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the corresponding NCS pin (NCS4 or NCS5). The Chip Select Register (DBW field in the corresponding Chip Select Register) of the NCS4 and/or NCS5 address space must be set as shown in Table 20-7 to enable the required access type. NBS1 and NBS0 are the byte selection signals from SMC and are available when the SMC is set in Byte Select mode on the corresponding Chip Select.
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The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For details on these waveforms and timings, refer to the Static Memory Controller section. Table 20-7.
Mode Attribute Memory
CFCE1 and CFCE2 Truth Table
CFCE2 NBS1 NBS1 CFCE1 NBS0 NBS0 0 NBS0 0 DBW 16 bits 16bits 8 bits 16 bits 8 bits Comment Access to Even Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Access to Odd Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Access to Odd Byte on D[7:0] Byte Select SMC Access Mode Byte Select Byte Select
Common Memory 1 NBS1 I/O Mode 1 True IDE Mode Task File Data Register Alternate True IDE Mode Control Register Alternate Status Read Drive Address Standby Mode or Address Space is not assigned to CF 0 0 1 1 1 1 Don't Care 8 bits - 1 1 0 0 8 bits 16 bits
Access to Even Byte on D[7:0] Access to Odd Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Byte Select
Access to Even Byte on D[7:0] Access to Odd Byte on D[7:0] -
Don't Care
-
20.6.6.3
Read/Write Signals In I/O mode and True IDE mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 20-5 on page 170 demonstrates a schematic representation of this logic. Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 (and/or NCS5) chip select to the appropriate values. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles of the Static Memory Controller section.
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Figure 20-5. CompactFlash Read/Write Control Signals
External Bus Interface SMC A23 1 1 0 1 A22 NRD_NOE NWR0_NWE 1 1 0 1
CompactFlash Logic
0 0 1 1 CFOE CFWE
CFIOR CFIOW
Table 20-8.
CompactFlash Mode Selection
CFOE NRD 1 0 CFWE NWR0_NWE 1 1 CFIOR 1 NRD NRD CFIOW 1 NWR0_NWE NWR0_NWE
Mode Base Address Attribute Memory Common Memory I/O Mode True IDE Mode
20.6.6.4
Multiplexing of CompactFlash Signals on EBI Pins Table 20-9 on page 170 and Table 20-10 on page 171 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 20-9 are strictly dedicated to the CompactFlash interface as soon as the EBI0_CS4A and/or EBI0_CS5A field of the EBI0_CSA Register in the Chip Configuration User Interface is set. These pins must not be used to drive any other memory devices. The EBI pins in Table 20-10 on page 171 remain shared between all memory areas when the corresponding CompactFlash interface is enabled (EBI0_CS4A = 1 and/or EBI0_CS5A = 1).
Table 20-9.
Pins
Dedicated CompactFlash Interface Multiplexing
CompactFlash Signals CS4A = 1 CS5A = 1 CS4A = 0 NCS4 CFCS1 NCS5 EBI Signals CS5A = 0
NCS4/CFCS0 NCS5/CFCS1
CFCS0
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Table 20-10. Shared CompactFlash Interface Multiplexing
Access to CompactFlash Device Pins NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW Access to Other EBI Devices EBI Signals NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25
20.6.6.5
Application Example Figure 20-6 on page 171 illustrates an example of a CompactFlash application. CFCS0 and CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS0 signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller Section.
Figure 20-6. CompactFlash Application Example
EBI CompactFlash Connector
D[15:0] DIR /OE A25/CFRNW NCS4/CFCS0
D[15:0]
_CD1 CD (PIO) _CD2 /OE A[10:0] A22/REG A[10:0] _REG
NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW
_OE _WE _IORD _IOWR
CFCE1 CFCE2
_CE1 _CE2
NWAIT
_WAIT
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20.6.7 NAND Flash Support External Bus Interfaces 0 and 1 integrate circuitry that interfaces to NAND Flash devices. External Bus Interface 0 The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space. Programming the EBI0_CS3A field in the EBI0_CSA Register in the Chip Configuration User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to the Bus Matrix Section. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. See Figure "NAND Flash Signal Multiplexing on EBI Pins" on page 172 for more information. For details on these waveforms, refer to the Static Memory Controller section. Figure 20-7. NAND Flash Signal Multiplexing on EBI Pins
SMC NAND Flash Logic
20.6.7.1
NCSx NRD
NANDOE
NANDOE
NANDWE NWR0_NWE
NANDWE
20.6.7.2
External Bus Interface 1 The NAND Flash logic is driven by the Static Memory Controller on the NCS2 address space. Programming the EBI1_CS2A field in the EBI1_CSA Register in the Chip Configuration User Interface to the appropriate value enables the NAND Flash logic. For details on this register, refer to the Bus Matrix Section. Access to an external NAND Flash device is then made by accessing the address space reserved to NCS2 (i.e., between 0x9000 0000 and 0x9FFF FFFF). The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals when the NCS2 signal is active. NANDOE and NANDWE are invalidated as soon as the transfer address fails to lie in the NCS2 address space. See Figure 20-7 on page 172 for more information. For details on these waveforms, refer to the Static Memory Controller section.
20.6.7.3
NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address 172
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
within the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is not selected, preventing the device from returning to standby mode. Figure 20-8. NAND Flash Application Example
D[7:0] A[22:21]
AD[7:0] ALE CLE
NCSx/NANDCS
Not Connected
EBI NAND Flash
NANDOE NANDWE
NOE NWE
PIO PIO
CE R/B
Note:
The External Bus Interfaces 0 and 1 are also able to support 16-bit devices.
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20.7
Implementation Examples
The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer web site to check current device availability.
20.7.1 20.7.1.1
16-bit SDRAM Hardware Configuration
D[0..15] A[0..14]
(Not used A12)
U1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 A14 SDCKE SDCK NBS0 NBS1 CAS RAS SDWE SDA10 BA0 BA1
23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40
SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE SDCS_NCS1
37 38 15 39 17 18 16 19
A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ
2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C1 C2 C3 C4 C5 C6 C7 1 1 1 1 1 1 1
256 Mbits
TSOP54 PACKAGE
20.7.1.2
Software Configuration The following configuration has to be performed: * Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in the section "SDRAM Device Initialization" in "SDRAM Controller (SDRAMC)".
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20.7.2 20.7.2.1
D[0..31] A[0..14]
32-bit SDRAM Hardware Configuration
(Not used A12)
U1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 A14 SDCKE SDCK NBS0 NBS1 CAS RAS SDWE SDA10 BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE 37 38 15 39 17 18 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 C1 C2 C3 C4 C5 C6 C7 100NF 100NF 100NF 100NF 100NF 100NF 100NF A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 BA0 BA1 A14 SDCKE SDCK A1 CFIOW_NBS3_NWR3 NBS2 NBS3 CAS RAS SDWE 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 37 38 15 39 17 18 16 19
U2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 3V3 C8 C9 C10 C11 C12 C13 C14 100NF 100NF 100NF 100NF 100NF 100NF 100NF
SDCS_NCS1
256 Mbits
TSOP54 PACKAGE
256 Mbits
20.7.2.2
Software Configuration The following configuration has to be performed: * Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * Initialize the SDRAM Controller depending on the SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the section "SDRAM Device Initialization" in "SDRAM Controller (SDRAMC)".
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20.7.3 20.7.3.1
8-bit NANDFlash Hardware Configuration
D[0..7]
U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 R2 10K 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 16 17 8 18 9 7 19 CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C
K9F2G08U0M I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.C VCC VCC VSS VSS 29 30 31 32 41 42 43 44 48 47 46 45 40 39 38 35 34 33 28 27 37 12 36 13 D0 D1 D2 D3 D4 D5 D6 D7
3V3
C2 100NF C1 100NF
2 Gb
TSOP48 PACKAGE
20.7.3.2
Software Configuration The following configuration has to be performed: * Assign the EBI CS3 to the NANDFlash by setting the bit EBI_CS3A in the EBI Chip Select Assignment Register located in the bus matrix memory space * Reserve A21 / A22 for ALE / CLE functions. Address and Command Latches are controlled respectively by setting to 1 the address bit A21 and A22 during accesses. * NANDOE and NANDWE signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. * Configure a PIO line as an input to manage the Ready/Busy signal. * Configure Static Memory Controller CS3 Setup, Pulse, Cycle and Mode accordingly to NANDFlash timings, the data bus width and the system bus frequency.
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20.7.4 20.7.4.1 16-bit NANDFlash Hardware Configuration
D[0..15]
U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) 3V3 R1 R2 10K 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 16 17 8 18 9 7 19 CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C
MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.C VCC VCC VSS VSS VSS 39 38 36 37 12 48 25 13
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
3V3
C2 100NF C1 100NF
2 Gb
TSOP48 PACKAGE
20.7.4.2
Software Configuration The software configuration is the same as for an 8-bit NANDFlash except the data bus width programmed in the mode register of the Static Memory Controller.
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20.7.5 20.7.5.1
NOR Flash on NCS0 Hardware Configuration
D[0..15] A[1..22] U1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 15 10 9 12 11 14 13 26 28
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 RESET WE WP VPP CE OE
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
AT49BV6416
29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
3V3
VCCQ VCC VSS VSS
47 37 46 27
NRST NWE 3V3 NCS0 NRD
C2 100NF
C1 100NF
TSOP48 PACKAGE
20.7.5.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory at slow clock. For another configuration, configure the Static Memory Controller CS0 Setup, Pulse, Cycle and Mode depending on Flash timings and system bus frequency.
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20.7.6 20.7.6.1 Compact Flash Hardware Configuration
D[0..15] MN1A D15 D14 D13 D12 D11 D10 D9 D8
MEMORY & I/O MODE
J1 3V3
A2 A1 B2 B1 C2 C1 D2 D1 A3 A4
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1DIR 1OE
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
A5 A6 B5 B6 C5 C6 D5 D6
CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8
74ALVCH32245 MN1B D7 D6 D5 D4 D3 D2 D1 D0 A25/CFRNW CFCSx (CFCS0 or CFCS1) (ANY PIO) CARD DETECT A[0..10] MN1C A10 A9 A8 A7 A6 A5 A4 A3 3V3
E2 E1 F2 F1 G2 G1 H2 H1 H3 H4
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2DIR 2OE
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
E5 E6 F5 F6 G5 G6 H5 H6
CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0
CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 CD2 CD1 CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3 CF_A2 CF_A1 CF_A0 REG
31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 25 26 8 10 11 12 14 15 16 17 18 19 20 44 36 9 35 34 32 7 24
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CD2# CD1# A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 REG# WE# OE# IOWR# IORD# CE2# CE1# WP WAIT# RESET
VCC VCC GND GND
38 13 50 1
C1 100NF C2 100NF
3V3
4 6 5
74ALVCH32245 MN2B SN74ALVC32
R1 MN2A 47K SN74ALVC32
R2 47K CD2 CD1
1 3 2
J5 J6 K5 K6 L5 L6 M5 M6 J3 J4
3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3DIR 3OE
3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8
J2 J1 K2 K1 L2 L1 M2 M1
CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3
WE OE IOWR IORD CE2 CE1
CSEL# INPACK# BVD2 BVD1
39 43 45 46
WAIT# RESET
42 41
VS2# VS1# RDY/BSY
40 33 37
RDY/BSY
74ALVCH32245 MN1D A2 A1 A0 A22/REG CFWE CFOE CFIOW CFIOR
N5 N6 P5 P6 R5 R6 T6 T5 T3 T4
4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 4DIR 4OE
4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
N2 N1 P2 P1 R2 R1 T1 T2
CF_A2 CF_A1 CF_A0 REG WE OE IOWR IORD
N7E50-7516VY-20
74ALVCH32245
1
CFCE2
2
MN3A SN74ALVC125 3
CE2
4
CFCE1
5
MN3B SN74ALVC125 6
CE1
10
(ANY PIO) CFRST
9
MN3C SN74ALVC125 RESET 8
13
(ANY PIO) CFIRQ
11
MN3D R3 SN74ALVC125 10K RDY/BSY 12
3V3
MN4 3V3 NWAIT
5 VCC 4
1 2 3
WAIT#
R4 10K 3V3
GND
SN74LVC1G125-Q1
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20.7.6.2
Software Configuration The following configuration has to be performed: * Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line A22 for REG function. * A23, CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. * Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. * Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency.
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20.7.7 20.7.7.1 Compact Flash True IDE Hardware Configuration
D[0..15] MN1A D15 D14 D13 D12 D11 D10 D9 D8
TRUE IDE MODE
J1 3V3
A2 A1 B2 B1 C2 C1 D2 D1 A3 A4
1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1DIR 1OE
1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8
A5 A6 B5 B6 C5 C6 D5 D6
CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8
74ALVCH32245 MN1B D7 D6 D5 D4 D3 D2 D1 D0 A25/CFRNW CFCSx (CFCS0 or CFCS1) (ANY PIO) CARD DETECT A[0..10] A10 A9 A8 A7 A6 A5 A4 A3 3V3 MN1C CF_A10 CF_A9 CF_A8 CF_A7 CF_A6 CF_A5 CF_A4 CF_A3
E2 E1 F2 F1 G2 G1 H2 H1 H3 H4
2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 2DIR 2OE
2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8
E5 E6 F5 F6 G5 G6 H5 H6
CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0
CF_D15 CF_D14 CF_D13 CF_D12 CF_D11 CF_D10 CF_D9 CF_D8 CF_D7 CF_D6 CF_D5 CF_D4 CF_D3 CF_D2 CF_D1 CF_D0 CD2 CD1
31 30 29 28 27 49 48 47 6 5 4 3 2 23 22 21 25 26 8 10 11 12 14 15 16 17 18 19 20 44 36 9 35 34 32 7 24
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CD2# CD1# A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 REG# WE# ATA SEL# IOWR# IORD# CS1# CS0# IOIS16# IORDY RESET#
N7E50-7516VY-20
VCC VCC GND GND
38 13 50 1
C1 100NF C2 100NF
3V3
4 6 5
74ALVCH32245 MN2B SN74ALVC32
R1 MN2A 47K SN74ALVC32
R2 47K CD2 CD1 CF_A2 CF_A1 CF_A0 3V3
1 3 2
J5 J6 K5 K6 L5 L6 M5 M6 J3 J4
3A1 3A2 3A3 3A4 3A5 3A6 3A7 3A8 3DIR 3OE
3B1 3B2 3B3 3B4 3B5 3B6 3B7 3B8
J2 J1 K2 K1 L2 L1 M2 M1
CSEL# INPACK# DASP# PDIAG#
39 43 45 46
IOWR IORD CE2 CE1
IORDY RESET#
42 41
VS2# VS1# INTRQ
40 33 37
INTRQ
74ALVCH32245 MN1D A2 A1 A0 A22/REG CFWE CFOE CFIOW CFIOR
N5 N6 P5 P6 R5 R6 T6 T5 T3 T4
4A1 4A2 4A3 4A4 4A5 4A6 4A7 4A8 4DIR 4OE
4B1 4B2 4B3 4B4 4B5 4B6 4B7 4B8
N2 N1 P2 P1 R2 R1 T1 T2
CF_A2 CF_A1 CF_A0 REG WE OE IOWR IORD
74ALVCH32245
1
CFCE2
2
MN3A SN74ALVC125 3
CE2
4
CFCE1
5 10
MN3B SN74ALVC125 6
CE1
(ANY PIO)
CFRST
9 13
MN3C SN74ALVC125 RESET# 8
(ANY PIO)
CFIRQ
11
MN3D SN74ALVC125 INTRQ 12
R3 10K 3V3
MN4 3V3 NWAIT
5 VCC 4
1 2 3
IORDY
R4 10K 3V3
GND
SN74LVC1G125-Q1
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20.7.7.2
Software Configuration The following configuration has to be performed: * Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. * The address line A21 is to select Alternate True IDE (A21=1) or True IDE (A21=0) modes. * CFRNW, CFS0, CFCS1, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. * Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. * Configure SMC CS4 and/or SMC_CS5 (for Slot 0 or 1) Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency.
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21. Static Memory Controller (SMC)
21.1 Description
The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable. The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from userprogrammed waveforms to slow-rate specific waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up to 32 bytes.
21.2
I/O Lines Description
I/O Line Description
Description Static Memory Controller Chip Select Lines Read Signal Write 0/Write Enable Signal Address Bit 0/Byte 0 Select Signal Write 1/Byte 1 Select Signal Address Bit 1/Write 2/Byte 2 Select Signal Write 3/Byte 3 Select Signal Address Bus Data Bus External Wait Signal Type Output Output Output Output Output Output Output Output I/O Input Low Active Level Low Low Low Low Low Low Low
Table 21-1.
Name NCS[7:0] NRD NWR0/NWE A0/NBS0 NWR1/NBS1
A1/NWR2/NBS2 NWR3/NBS3 A[25:2] D[31:0] NWAIT
21.3
Multiplexed Signals
Static Memory Controller (SMC) Multiplexed Signals
Related Function Byte-write or byte-select access, see "Byte Write or Byte Select Access" on page 185 8-bit or 16-/32-bit data bus, see "Data Bus Width" on page 185 Byte-write or byte-select access see "Byte Write or Byte Select Access" on page 185 NBS2 8-/16-bit or 32-bit data bus, see "Data Bus Width" on page 185. Byte-write or byte-select access, see "Byte Write or Byte Select Access" on page 185 Byte-write or byte-select access see "Byte Write or Byte Select Access" on page 185
Table 21-2.
Multiplexed Signals NWR0 A0 NWR1 A1 NWR3 NWE NBS0 NBS1 NWR2 NBS3
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21.4
21.4.1
Application Example
Hardware Interface
Figure 21-1. SMC Connections to Static Memory Devices
D0-D31
A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3
D0 - D7
128K x 8 SRAM
D0 - D7 CS A0 - A16 A2 - A18
D8-D15
128K x 8 SRAM
D0-D7 CS A0 - A16 A2 - A18
NCS0 NCS1 NCS2 NCS3 NCS4 NCS5 NCS6 NCS7
NRD NWR0/NWE
OE WE
NRD NWR1/NBS1
OE WE
D16 - D23 A2 - A25 CS
128K x 8 SRAM
D0 - D7
D24-D31
128K x 8 SRAM
D0-D7 CS A2 - A18 A0 - A16
A0 - A16 NRD A1/NWR2/NBS2 OE WE
A2 - A18 NRD OE NWR3/NBS3 WE
Static Memory Controller
21.5
21.5.1
Product Dependencies
I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O Lines of the SMC are not used by the application, they can be used for other putposes by the PIO Controller.
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21.6 External Memory Mapping
The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 21-1). A[25:0] is only significant for 8-bit memory, A[25:1] is used for 16-bit memory, A[25:2] is used for 32-bit memory. Figure 21-2. Memory Connections for Eight External Devices
NCS[0] - NCS[7] NRD
NCS7 NCS6 NCS5 NCS4 NCS3 NCS2 NCS1 NCS0
Memory Enable Memory Enable
SMC
NWE A[25:0] D[31:0]
Memory Enable Memory Enable
Memory Enable Memory Enable
Memory Enable
Memory Enable Output Enable Write Enable A[25:0]
8 or 16 or 32
D[31:0] or D[15:0] or D[7:0]
21.7
21.7.1
Connection to External Devices
Data Bus Width A data bus width of 8, 16, or 32 bits can be selected for each chip select. This option is controlled by the field DBW in SMC_MODE (Mode Register) for the corresponding chip select. Figure 21-3 shows how to connect a 512K x 8-bit memory on NCS2. Figure 21-4 shows how to connect a 512K x 16-bit memory on NCS2. Figure 21-5 shows two 16-bit memories connected as a single 32-bit memory
21.7.2
Byte Write or Byte Select Access Each chip select with a 16-bit or 32-bit data bus can operate with one of two different types of write access: byte write or byte select access. This is controlled by the BAT field of the SMC_MODE register for the corresponding chip select.
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Figure 21-3.
Memory Connection for an 8-bit Data Bus
D[7:0] A[18:2] A0 SMC A1 NWE NRD NCS[2] D[7:0]
A[18:2] A0 A1 Write Enable Output Enable Memory Enable
Figure 21-4.
Memory Connection for a 16-bit Data Bus
D[15:0] A[19:2] A1 SMC NBS0 NBS1 NWE NRD NCS[2] D[15:0] A[18:1] A[0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable
Figure 21-5. Memory Connection for a 32-bit Data Bus
D[31:16] D[15:0] A[20:2] D[31:16] D[15:0] A[18:0] Byte 0 Enable Byte 1 Enable Byte 2 Enable Byte 3 Enable Write Enable Output Enable Memory Enable
SMC
NBS0 NBS1 NBS2 NBS3 NWE NRD NCS[2]
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21.7.2.1 Byte Write Access Byte write access supports one byte write signal per byte of the data bus and a single read signal. * For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. One single read signal (NRD) is provided. Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory. * For 32-bit devices: NWR0, NWR1, NWR2 and NWR3, are the write signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. One single read signal (NRD) is provided. Byte Write Access is used to connect 4 x 8-bit devices as a 32-bit memory. Byte Write option is illustrated on Figure 21-6. 21.7.2.2 Byte Select Access In this mode, read/write operations can be enabled/disabled at a byte level. One byte-select line per byte of the data bus is provided. One NRD and one NWE signal control read and write. * For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals for respectively byte0 (lower byte) and byte1 (upper byte) of a 16-bit bus. Byte Select Access is used to connect one 16-bit device. * For 32-bit devices: NBS0, NBS1, NBS2 and NBS3, are the selection signals of byte0 (lower byte), byte1, byte2 and byte 3 (upper byte) respectively. Byte Select Access is used to connect two 16-bit devices. Figure 21-7 shows how to connect two 16-bit devices on a 32-bit data bus in Byte Select Access mode, on NCS3 (BAT = Byte Select Access). Figure 21-6. Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option
D[7:0] D[15:8] A[24:2] A[23:1] A[0] Write Enable Read Enable Memory Enable D[7:0]
SMC
A1 NWR0 NWR1 NRD NCS[3]
D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable
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21.7.2.3
Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed. Table 21-3 shows signal multiplexing depending on the data bus width and the byte access type. For 32-bit devices, bits A0 and A1 are unused. For 16-bit devices, bit A0 of address is unused. When Byte Select Option is selected, NWR1 to NWR3 are unused. When Byte Write option is selected, NBS0 to NBS3 are unused.
Figure 21-7. Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option)
D[15:0] D[31:16] A[25:2] NWE NBS0 NBS1 A[23:0] Write Enable Low Byte Enable High Byte Enable D[15:0]
SMC
NBS2 NBS3 NRD NCS[3] Read Enable Memory Enable
D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable
Table 21-3.
Signal Name Device Type
SMC Multiplexed Signal Translation
32-bit Bus 1x32-bit Byte Select NBS0 NWE NBS1 NBS2 NBS3 2x16-bit Byte Select NBS0 NWE NBS1 NBS2 NBS3 NWR0 NWR1 NWR2 NWR3 4 x 8-bit Byte Write 16-bit Bus 1x16-bit Byte Select NBS0 NWE NBS1 A1 NWR0 NWR1 A1 A1 2 x 8-bit Byte Write A0 NWE 8-bit Bus 1 x 8-bit
Byte Access Type (BAT) NBS0_A0 NWE_NWR0 NBS1_NWR1 NBS2_NWR2_A1 NBS3_NWR3
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21.8 Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to NBS3) always have the same timing as the A address bus. NWE represents either the NWE signal in byte select access type or one of the byte write lines (NWR0 to NWR3) in byte write access type. NWR0 to NWR3 have the same timings and protocol as NWE. In the same way, NCS represents one of the NCS[0..7] chip select lines. 21.8.1 Read Waveforms The read cycle is shown on Figure 21-8. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 21-8. Standard Read Cycle
MCK
A[25:2]
NBS0,NBS1, NBS2,NBS3, A0, A1 NRD
NCS
D[31:0] NRD_SETUP NRD_PULSE NRD_HOLD
NCS_RD_SETUP
NCS_RD_PULSE NRD_CYCLE
NCS_RD_HOLD
21.8.1.1
NRD Waveform The NRD signal is characterized by a setup timing, a pulse width and a hold timing. 1. NRD_SETUP: the NRD setup time is defined as the setup of address before the NRD falling edge; 2. NRD_PULSE: the NRD pulse length is the time between NRD falling edge and NRD rising edge; 3. NRD_HOLD: the NRD hold time is defined as the hold time of address after the NRD rising edge.
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21.8.1.2
NCS Waveform Similarly, the NCS signal can be divided into a setup time, pulse length and hold time: 1. NCS_RD_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_RD_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_RD_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge.
21.8.1.3
Read Cycle The NRD_CYCLE time is defined as the total duration of the read cycle, i.e., from the time where address is set on the address bus to the point where address may change. The total read cycle time is equal to: NRD_CYCLE = NRD_SETUP + NRD_PULSE + NRD_HOLD = NCS_RD_SETUP + NCS_RD_PULSE + NCS_RD_HOLD All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE
21.8.1.4
Null Delay Setup and Hold If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain active continuously in case of consecutive read cycles in the same memory (see Figure 21-9).
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Figure 21-9. No Setup, No Hold On NRD and NCS Read Signals
MCK
A[25:2]
NBS0,NBS1, NBS2,NBS3, A0, A1 NRD
NCS
D[31:0] NRD_PULSE NRD_PULSE NRD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_CYCLE
NRD_CYCLE
21.8.1.5
Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
21.8.2
Read Mode As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and NCS controls the read operation.
21.8.2.1
Read is Controlled by NRD (READ_MODE = 1): Figure 21-10 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available tPACC after the falling edge of NRD, and turns to `Z' after the rising edge of NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed waveform of NCS may be.
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Figure 21-10. READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
MCK
A[25:2]
NBS0,NBS1, NBS2,NBS3, A0, A1 NRD
NCS tPACC D[31:0]
Data Sampling
21.8.2.2
Read is Controlled by NCS (READ_MODE = 0) Figure 21-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.
Figure 21-11. READ_MODE = 0: Data is sampled by SMC before the rising edge of NCS
MCK
A[25:2]
NBS0,NBS1, NBS2,NBS3, A0, A1 NRD
NCS tPACC D[31:0]
Data Sampling
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21.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 21-12. The write cycle starts with the address setting on the memory address bus. NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. NWE_SETUP: the NWE setup time is defined as the setup of address and data before the NWE falling edge; 2. NWE_PULSE: The NWE pulse length is the time between NWE falling edge and NWE rising edge; 3. NWE_HOLD: The NWE hold time is defined as the hold time of address and data after the NWE rising edge. The NWE waveforms apply to all byte-write lines in Byte Write access mode: NWR0 to NWR3. 21.8.3.2 NCS Waveforms The NCS signal waveforms in write operation are not the same that those applied in read operations, but are separately defined: 1. NCS_WR_SETUP: the NCS setup time is defined as the setup time of address before the NCS falling edge. 2. NCS_WR_PULSE: the NCS pulse length is the time between NCS falling edge and NCS rising edge; 3. NCS_WR_HOLD: the NCS hold time is defined as the hold time of address after the NCS rising edge. Figure 21-12. Write Cycle
MCK
21.8.3.1
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 NWE
NCS
NWE_SETUP NCS_WR_SETUP
NWE_PULSE
NWE_HOLD
NCS_WR_PULSE NWE_CYCLE
NCS_WR_HOLD
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21.8.3.3
Write Cycle The write_cycle time is defined as the total duration of the write cycle, that is, from the time where address is set on the address bus to the point where address may change. The total write cycle time is equal to: NWE_CYCLE = NWE_SETUP + NWE_PULSE + NWE_HOLD = NCS_WR_SETUP + NCS_WR_PULSE + NCS_WR_HOLD All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as: NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
21.8.3.4
Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 21-13). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
Figure 21-13. Null Setup and Hold Values of NCS and NWE in Write Cycle
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3
NCS
D[31:0] NWE_PULSE NWE_PULSE NWE_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NCS_WR_PULSE
NWE_CYCLE
NWE_CYCLE
NWE_CYCLE
21.8.3.5
Null Pulse Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
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21.8.4 Write Mode The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal controls the write operation. 21.8.4.1 Write is Controlled by NWE (WRITE_MODE = 1): Figure 21-14 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during the pulse and hold steps of the NWE signal. The internal data buffers are turned out after the NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.
Figure 21-14. WRITE_MODE = 1. The write operation is controlled by NWE
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0]
21.8.4.2
Write is Controlled by NCS (WRITE_MODE = 0) Figure 21-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal. The internal data buffers are turned out after the NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
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Figure 21-15. WRITE_MODE = 0. The write operation is controlled by NCS
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3
NCS
D[31:0]
21.8.5
Coding Timing Parameters All timing parameters are defined for one chip select and are grouped together in one SMC_REGISTER according to their type. The SMC_SETUP register groups the definition of all setup parameters: * NRD_SETUP, NCS_RD_SETUP, NWE_SETUP, NCS_WR_SETUP The SMC_PULSE register groups the definition of all pulse parameters: * NRD_PULSE, NCS_RD_PULSE, NWE_PULSE, NCS_WR_PULSE The SMC_CYCLE register groups the definition of all cycle parameters: * NRD_CYCLE, NWE_CYCLE Table 21-4 shows how the timing parameters are coded and their permitted range.
Table 21-4.
Coding and Range of Timing Parameters
Permitted Range
Coded Value setup [5:0] pulse [6:0] cycle [8:0]
Number of Bits 6 7 9
Effective Value 128 x setup[5] + setup[4:0] 256 x pulse[6] + pulse[5:0] 256 x cycle[8:7] + cycle[6:0]
Coded Value 0 31 0 63 0 127
Effective Value 128 128+31 256 256+63 256 256+127 512 512+127 768 768+127
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21.8.6 Reset Values of Timing Parameters Table 21-5 gives the default value of timing parameters at reset. Table 21-5.
Register SMC_SETUP SMC_PULSE SMC_CYCLE WRITE_MODE READ_MODE
Reset Values of Timing Parameters
Reset Value 0x01010101 0x01010101 0x00030003 1 1 All setup timings are set to 1 All pulse timings are set to 1 The read and write operation last 3 Master Clock cycles and provide one hold cycle Write is controlled with NWE Read is controlled with NRD
21.8.7
Usage Restriction The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpredictable behavior of the SMC. For read operations: Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the memory interface because of the propagation delay of theses signals through external logic and pads. If positive setup and hold values must be verified, then it is strictly recommended to program non-null values so as to cover possible skews between address, NCS and NRD signals. For write operations: If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address, byte select lines, and NCS signal after the rising edge of NWE. This is true for WRITE_MODE = 1 only. See "Early Read Wait State" on page 198. For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior. In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals (write), these setup and hold times must be converted into setup and hold times in reference to the address bus.
21.9
Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or operation conflict.
21.9.1
Chip Select Wait States The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is no bus contention between the de-activation of one device and the activation of the next one. During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to NWR3, NCS[0..7], NRD lines are all set to 1. Figure 21-16 illustrates a chip select wait state between access on Chip Select 0 and Chip Select 2.
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Figure 21-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE
NCS0
NCS2 NRD_CYCLE D[31:0] NWE_CYCLE
Read to Write Chip Select Wait State Wait State
21.9.2
Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins. This wait state is not generated in addition to a chip select wait state. The early read cycle thus only occurs between a write and read access to the same memory device (same chip select). An early read wait state is automatically inserted if at least one of the following conditions is valid: * if the write controlling signal has no hold time and the read controlling signal has no setup time (Figure 21-17). * in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode (Figure 21-18). The write operation must end with a NCS rising edge. Without an Early Read Wait State, the write operation could not complete properly. * in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD = 0), the feedback of the write control signal is used to control address, data, chip select and byte select lines. If the external write control signal is not inactivated as expected due to load capacitances, an Early Read Wait State is inserted and address, data and control signals are maintained one more cycle. See Figure 21-19.
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Figure 21-17. Early Read Wait State: Write with No Hold Followed by Read with No Setup
MCK
A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD no hold no setup D[31:0]
write cycle
Early Read wait state
read cycle
Figure 21-18. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read with No NCS Setup
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 NCS
NRD no hold D[31:0] no setup
write cycle (WRITE_MODE = 0)
Early Read wait state
read cycle (READ_MODE = 0 or READ_MODE = 1)
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Figure 21-19. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read with One Set-up Cycle
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) no hold NRD read setup = 1
D[31:0]
write cycle (WRITE_MODE = 1)
Early Read wait state
read cycle (READ_MODE = 0 or READ_MODE = 1)
21.9.3
Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface. When detecting that a new user configuration has been written in the user interface, the SMC inserts a wait state before starting the next access. The so called "Reload User Configuration Wait State" is used by the SMC to load the new set of parameters to apply to next accesses. The Reload Configuration Wait State is not applied in addition to the Chip Select Wait State. If accesses before and after re-programming the user interface are made to different devices (Chip Selects), then one single Chip Select Wait State is applied. On the other hand, if accesses before and after writing the user interface are made to the same device, a Reload Configuration Wait State is inserted, even if the change does not concern the current Chip Select.
21.9.3.1
User Procedure To insert a Reload Configuration Wait State, the SMC detects a write access to any SMC_MODE register of the user interface. If the user only modifies timing registers (SMC_SETUP, SMC_PULSE, SMC_CYCLE registers) in the user interface, he must validate the modification by writing the SMC_MODE, even if no change was made on the mode parameters. Slow Clock Mode Transition A Reload Configuration Wait State is also inserted when the Slow Clock Mode is entered or exited, after the end of the current transfer (see "Slow Clock Mode" on page 212).
21.9.3.2
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21.9.4 Read to Write Wait State Due to an internal mechanism, a wait cycle is always inserted between consecutive read and write SMC accesses. This wait cycle is referred to as a read to write wait state in this document. This wait cycle is applied in addition to chip select and reload user configuration wait states when they are to be inserted. See Figure 21-16 on page 198.
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21.10 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: * before starting a read access to a different external memory * before starting a write access to the same device or to a different external one. The Data Float Output Time (t DF ) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select. The value of TDF_CYCLES indicates the number of data float wait cycles (between 0 and 15) before the external device releases the bus, and represents the time allowed for the data output to go to high impedance after the memory is disabled. Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t DF will not slow down the execution of a program from internal memory. The data float wait states management depends on the READ_MODE and the TDF_MODE fields of the SMC_MODE register for the corresponding chip select. 21.10.1 READ_MODE Setting the READ_MODE to 1 indicates to the SMC that the NRD signal is responsible for turning off the tri-state buffers of the external memory device. The Data Float Period then begins after the rising edge of the NRD signal and lasts TDF_CYCLES MCK cycles. When the read operation is controlled by the NCS signal (READ_MODE = 0), the TDF field gives the number of MCK cycles during which the data bus remains busy after the rising edge of NCS. Figure 21-20 illustrates the Data Float Period in NRD-controlled mode (READ_MODE =1), assuming a data float period of 2 cycles (TDF_CYCLES = 2). Figure 21-21 shows the read operation when controlled by NCS (READ_MODE = 0) and the TDF_CYCLES parameter equals 3.
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Figure 21-20. TDF Period in NRD Controlled Read Access (TDF = 2)
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 NRD
NCS tpacc D[31:0] TDF = 2 clock cycles
NRD controlled read operation
Figure 21-21. TDF Period in NCS Controlled Read Operation (TDF = 3)
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 NRD
NCS tpacc D[31:0]
TDF = 3 clock cycles NCS controlled read operation
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21.10.2
TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert. Figure 21-22 shows a read access controlled by NRD, followed by a write access controlled by NWE, on Chip Select 0. Chip Select 0 has been programmed with: NRD_HOLD = 4; READ_MODE = 1 (NRD controlled) NWE_SETUP = 3; WRITE_MODE = 1 (NWE controlled) TDF_CYCLES = 6; TDF_MODE = 1 (optimization enabled).
Figure 21-22. TDF Optimization: No TDF Wait States Inserted if the TDF Period is Over When the Next Access Begins
MCK
A[25:2]
NRD NRD_HOLD= 4 NWE
NWE_SETUP= 3 NCS0
TDF_CYCLES = 6
D[31:0]
read access on NCS0 (NRD controlled)
Read to Write Wait State
write access on NCS0 (NWE controlled)
21.10.3
TDF Optimization Disabled (TDF_MODE = 0) When optimization is disabled, tdf wait states are inserted at the end of the read transfer, so that the data float period is ended when the second access begins. If the hold period of the read1 controlling signal overlaps the data float period, no additional tdf wait states will be inserted. Figure 21-23, Figure 21-24 and Figure 21-25 illustrate the cases: * read access followed by a read access on another chip select, * read access followed by a write access on another chip select, * read access followed by a write access on the same chip select, with no TDF optimization.
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Figure 21-23. TDF Optimization Disabled (TDF Mode = 0). TDF Wait States Between 2 Read Accesses on Different Chip Selects
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD)
read1 hold = 1
read2 setup = 1
read2 controlling signal (NRD) D[31:0]
TDF_CYCLES = 6
5 TDF WAIT STATES read1 cycle TDF_CYCLES = 6 Chip Select Wait State read 2 cycle TDF_MODE = 0 (optimization disabled)
Figure 21-24. TDF Mode = 0: TDF Wait States Between a Read and a Write Access on Different Chip Selects
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD)
read1 hold = 1
write2 setup = 1
write2 controlling signal (NWE)
TDF_CYCLES = 4
D[31:0]
read1 cycle TDF_CYCLES = 4 Read to Write Chip Select Wait State Wait State
2 TDF WAIT STATES
write2 cycle TDF_MODE = 0 (optimization disabled)
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Figure 21-25. TDF Mode = 0: TDF Wait States Between Read and Write Accesses on the Same Chip Select
MCK
A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD)
read1 hold = 1
write2 setup = 1
write2 controlling signal (NWE)
TDF_CYCLES = 5
D[31:0]
4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 write2 cycle TDF_MODE = 0 (optimization disabled)
Read to Write Wait State
21.11 External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC. The EXNW_MODE field of the SMC_MODE register on the corresponding chip select must be set to either to "10" (frozen mode) or "11" (ready mode). When the EXNW_MODE is set to "00" (disabled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal delays the read or write operation in regards to the read or write controlling signal, depending on the read and write modes of the corresponding chip select. 21.11.1 Restriction When one of the EXNW_MODE is enabled, it is mandatory to program at least one hold cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in Page Mode ("Asynchronous Page Mode" on page 215), or in Slow Clock Mode ("Slow Clock Mode" on page 212). The NWAIT signal is assumed to be a response of the external device to the read/write request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write controlling signal. The assertion of the NWAIT signal outside the expected period has no impact on SMC behavior.
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21.11.2 Frozen Mode When the external device asserts the NWAIT signal (active low), and after internal synchronization of this signal, the SMC state is frozen, i.e., SMC internal counters are frozen, and all control signals remain unchanged. When the resynchronized NWAIT signal is deasserted, the SMC completes the access, resuming the access from the point where it was stopped. See Figure 2126. This mode must be selected when the external device uses the NWAIT signal to delay the access and to freeze the SMC. The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure 21-27. Figure 21-26. Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 4 NWE 6 NCS 5 4 3 2 2 3 2 1 1
FROZEN STATE 1 1 0
2
2
1
0
D[31:0]
NWAIT
internally synchronized NWAIT signal
Write cycle
EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7
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Figure 21-27. Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10)
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 4 3 2
FROZEN STATE 2 2 1 0 2 1 0 5 5 5 4 3 2 1 0 1 0
NCS
NRD
NWAIT
internally synchronized NWAIT signal
Read cycle
EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 Assertion is ignored
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21.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 21-28 and Figure 21-29. After deassertion, the access is completed: the hold step of the access is performed. This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability to complete the read or write operation. If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the controlling read/write signal, it has no impact on the access length as shown in Figure 21-29. Figure 21-28. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1
Wait STATE 4 3 2 1 0 0 0
NWE 6 NCS 5 4 3 2 1 1 1 0
D[31:0]
NWAIT
internally synchronized NWAIT signal
Write cycle
EXNW_MODE = 11 (Ready mode) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7
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Figure 21-29. NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11)
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 6 NCS 5 4 3 2 1 0
Wait STATE 0
NRD
6
5
4
3
2
1
1
0
NWAIT
internally synchronized NWAIT signal
Read cycle
EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 Assertion is ignored
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21.11.4 NWAIT Latency and Read/write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated on Figure 21-30. When EXNW_MODE is enabled (ready or frozen), the user must program a pulse length of the read and write controlling signal of at least: minimal pulse length = NWAIT latency + 2 resynchronization cycles + 1 cycle Figure 21-30. NWAIT Latency
MCK A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 4 NRD minimal pulse length 3 2 1 0 0
WAIT STATE 0
NWAIT intenally synchronized NWAIT signal
NWAIT latency 2 cycle resynchronization
Read cycle EXNW_MODE = 10 or 11 READ_MODE = 1 (NRD_controlled) NRD_PULSE = 5
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21.12 Slow Clock Mode
The SMC is able to automatically apply a set of "slow clock mode" read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate. When activated, the slow mode is active on all chip selects. 21.12.1 Slow Clock Mode Waveforms Figure 21-31 illustrates the read and write operations in slow clock mode. They are valid on all chip selects. Table 21-6 indicates the value of read and write parameters in slow clock mode.
Figure 21-31. Read/write Cycles in Slow Clock Mode
MCK MCK
A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 NRD 1 1 NCS NRD_CYCLE = 2 SLOW CLOCK MODE READ
NWE
1 1
1
NCS NWE_CYCLE = 3 SLOW CLOCK MODE WRITE
Table 21-6.
Read and Write Timing Parameters in Slow Clock Mode
Duration (cycles) 1 1 0 2 2 Write Parameters NWE_SETUP NWE_PULSE NCS_WR_SETUP NCS_WR_PULSE NWE_CYCLE Duration (cycles) 1 1 0 3 3
Read Parameters NRD_SETUP NRD_PULSE NCS_RD_SETUP NCS_RD_PULSE NRD_CYCLE
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21.12.2 Switching from (to) Slow Clock Mode to (from) Normal Mode When switching from slow clock mode to the normal mode, the current slow clock mode transfer is completed at high clock rate, with the set of slow clock mode parameters.See Figure 21-32 on page 213. The external device may not be fast enough to support such timings. Figure 21-33 illustrates the recommended procedure to properly switch from one mode to the other. Figure 21-32. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE
1 NCS
1
1
1
1
1
2
3
2
NWE_CYCLE = 3 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE
NWE_CYCLE = 7 NORMAL MODE WRITE
This write cycle finishes with the slow clock mode set of parameters after the clock rate transition
Slow clock mode transition is detected: Reload Configuration Wait State
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Figure 21-33. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow Clock Mode
Slow Clock Mode internal signal from PMC
MCK
A[25:2]
NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 NCS 1 1 2 3 2
SLOW CLOCK MODE WRITE
IDLE STATE
NORMAL MODE WRITE
Reload Configuration Wait State
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21.13 Asynchronous Page Mode
The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory. The MSB of data address defines the address of the page in memory, the LSB of address define the address of the data in the page as detailed in Table 21-7. With page mode memory devices, the first access to one page (tpa) takes longer than the subsequent accesses to the page (tsa ) as shown in Figure 21-34. When in page mode, the SMC enables the user to define different read timings for the first access within one page, and next accesses within the page. Table 21-7.
Page Size 4 bytes 8 bytes 16 bytes 32 bytes Notes:
Page Address and Data Address within a Page
Page Address(1) A[25:2] A[25:3] A[25:4] A[25:5] Data Address in the Page(2) A[1:0] A[2:0] A[3:0] A[4:0]
1. A denotes the address bus of the memory device. 2. For 16-bit devices, the bit 0 of address is ignored. For 32-bit devices, bits [1:0] are ignored.
21.13.1
Protocol and Timings in Page Mode Figure 21-34 shows the NRD and NCS timings in page mode access.
Figure 21-34. Page Mode Read Protocol (Address MSB and LSB are defined in Table 21-7)
MCK A[MSB]
A[LSB] NRD NCS tpa tsa tsa
D[31:0]
NCS_RD_PULSE
NRD_PULSE
NRD_PULSE
The NRD and NCS signals are held low during all read transfers, whatever the programmed values of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS timings are identical. The pulse length of the first access to the page is defined with the 215
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NCS_RD_PULSE field of the SMC_PULSE register. The pulse length of subsequent accesses within the page are defined using the NRD_PULSE parameter. In page mode, the programming of the read timings is described in Table 21-8: Table 21-8.
Parameter READ_MODE NCS_RD_SETUP NCS_RD_PULSE NRD_SETUP NRD_PULSE NRD_CYCLE
Programming of Read Timings in Page Mode
Value `x' `x' tpa `x' tsa `x' Definition No impact No impact Access time of first access to the page No impact Access time of subsequent accesses in the page No impact
The SMC does not check the coherency of timings. It will always apply the NCS_RD_PULSE timings as page access timing (tpa) and the NRD_PULSE for accesses to the page (tsa), even if the programmed value for tpa is shorter than the programmed value for tsa. 21.13.2 Byte Access Type in Page Mode The Byte Access Type configuration remains active in page mode. For 16-bit or 32-bit page mode devices that require byte selection signals, configure the BAT field of the SMC_REGISTER to 0 (byte select access type). Page Mode Restriction The page mode is not compatible with the use of the NWAIT signal. Using the page mode and the NWAIT signal may lead to unpredictable behavior. Sequential and Non-sequential Accesses If the chip select and the MSB of addresses as defined in Table 21-7 are identical, then the current access lies in the same page as the previous one, and no page break occurs. Using this information, all data within the same page, sequential or not sequential, are accessed with a minimum access time (tsa). Figure 21-35 illustrates access to an 8-bit memory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long access time (tpa). Accesses to D3 and D7, though they are not sequential accesses, only require a short access time (tsa). If the MSB of addresses are different, the SMC performs the access of a new page. In the same way, if the chip select is different from the previous access, a page break occurs. If two sequential accesses are made to the page mode memory, but separated by an other internal or external peripheral access, a page break occurs on the second access because the chip select of the device was deasserted between both accesses.
21.13.3
21.13.4
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Figure 21-35. Access to Non-sequential Data within the Same Page
MCK
A[25:3]
Page address
A[2], A1, A0
A1
A3
A7
NRD NCS
D[7:0] NCS_RD_PULSE
D1 NRD_PULSE
D3 NRD_PULSE
D7
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21.14 Static Memory Controller (SMC) User Interface
The SMC is programmed using the registers listed in Table 21-9. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 21-9, "CS_number" denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers. Table 21-9. SMC Register Mapping
Offset 0x10 x CS_number + 0x00 0x10 x CS_number + 0x04 0x10 x CS_number + 0x08 0x10 x CS_number + 0x0C Register SMC Setup Register SMC Pulse Register SMC Cycle Register SMC Mode Register Name SMC_SETUP SMC_PULSE SMC_CYCLE SMC_MODE Access Read/Write Read/Write Read/Write Read/Write Reset State 0x01010101 0x01010101 0x00030003 0x10001000
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21.14.1 SMC Setup Register Register Name: SMC_SETUP[0 ..7] Access Type:
31 - 23 - 15 - 7 -
Read/Write
30 - 22 - 14 - 6 - 5 4 13 12 11 21 20 29 28 27 26 25 24 NCS_RD_SETUP 19 NRD_SETUP 10 9 8 18 17 16
NCS_WR_SETUP 3 NWE_SETUP 2 1 0
* NWE_SETUP: NWE Setup Length The NWE signal setup length is defined as: NWE setup length = (128* NWE_SETUP[5] + NWE_SETUP[4:0]) clock cycles * NCS_WR_SETUP: NCS Setup Length in WRITE Access In write access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_WR_SETUP[5] + NCS_WR_SETUP[4:0]) clock cycles * NRD_SETUP: NRD Setup Length The NRD signal setup length is defined in clock cycles as: NRD setup length = (128* NRD_SETUP[5] + NRD_SETUP[4:0]) clock cycles * NCS_RD_SETUP: NCS Setup Length in READ Access In read access, the NCS signal setup length is defined as: NCS setup length = (128* NCS_RD_SETUP[5] + NCS_RD_SETUP[4:0]) clock cycles
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21.14.2 SMC Pulse Register Register Name: SMC_PULSE[0..7] Access Type:
31 - 23 - 15 - 7 - 6 5 4 14 13 12 22 21 20
Read/Write
30 29 28 27 NCS_RD_PULSE 19 NRD_PULSE 11 NCS_WR_PULSE 3 NWE_PULSE 2 1 0 10 9 8 18 17 16 26 25 24
* NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle. * NCS_WR_PULSE: NCS Pulse Length in WRITE Access In write access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_WR_PULSE[6] + NCS_WR_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. * NRD_PULSE: NRD Pulse Length In standard read access, the NRD signal pulse length is defined in clock cycles as: NRD pulse length = (256* NRD_PULSE[6] + NRD_PULSE[5:0]) clock cycles The NRD pulse length must be at least 1 clock cycle. In page mode read access, the NRD_PULSE parameter defines the duration of the subsequent accesses in the page. * NCS_RD_PULSE: NCS Pulse Length in READ Access In standard read access, the NCS signal pulse length is defined as: NCS pulse length = (256* NCS_RD_PULSE[6] + NCS_RD_PULSE[5:0]) clock cycles The NCS pulse length must be at least 1 clock cycle. In page mode read access, the NCS_RD_PULSE parameter defines the duration of the first access to one page.
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21.14.3 SMC Cycle Register Register Name: SMC_CYCLE[0..7] Access Type:
31 - 23
Read/Write
30 - 22 29 - 21 28 - 20 NRD_CYCLE 27 - 19 26 - 18 25 - 17 24 NRD_CYCLE 16
15 - 7
14 - 6
13 - 5
12 - 4 NWE_CYCLE
11 - 3
10 - 2
9 - 1
8 NWE_CYCLE 0
* NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals. It is defined as: Write cycle length = (NWE_CYCLE[8:7]*256 + NWE_CYCLE[6:0]) clock cycles * NRD_CYCLE: Total Read Cycle Length The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and hold steps of the NRD and NCS signals. It is defined as: Read cycle length = (NRD_CYCLE[8:7]*256 + NRD_CYCLE[6:0]) clock cycles
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21.14.4 SMC MODE Register Register Name: SMC_MODE[0..7] Access Type:
31 - 23 - 15 - 7 -
Read/Write
30 - 22 - 14 - 6 - 5 EXNW_MODE 21 - 13 DBW 4 29 PS 20 TDF_MODE 12 11 - 3 - 10 - 2 - 28 27 - 19 26 - 18 TDF_CYCLES 9 - 1 WRITE_MODE 8 BAT 0 READ_MODE 25 - 17 24 PMEN 16
* READ_MODE: 1: The read operation is controlled by the NRD signal. - If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NRD. 0: The read operation is controlled by the NCS signal. - If TDF cycles are programmed, the external bus is marked busy after the rising edge of NCS. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states are inserted after the setup of NCS. * WRITE_MODE 1: The write operation is controlled by the NWE signal. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NWE. 0: The write operation is controlled by the NCS signal. - If TDF optimization is enabled (TDF_MODE =1), TDF wait states will be inserted after the setup of NCS. * EXNW_MODE: NWAIT Mode The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for the read and write controlling signal.
EXNW_MODE 0 0 1 1 0 1 0 1 NWAIT Mode Disabled Reserved Frozen Mode Ready Mode
* Disabled Mode: The NWAIT input signal is ignored on the corresponding Chip Select. * Frozen Mode: If asserted, the NWAIT signal freezes the current read or write cycle. After deassertion, the read/write cycle is resumed from the point where it was stopped. * Ready Mode: The NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read or write signal, to complete the access. If high, the access normally completes. If low, the access is extended until NWAIT returns high.
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* BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. * 1: Byte write access type: - Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. - Read operation is controlled using NCS and NRD. * 0: Byte select access type: - Write operation is controlled using NCS, NWE, NBS0, NBS1, NBS2 and NBS3 - Read operation is controlled using NCS, NRD, NBS0, NBS1, NBS2 and NBS3 * DBW: Data Bus Width
DBW 0 0 1 1 0 1 0 1 Data Bus Width 8-bit bus 16-bit bus 32-bit bus Reserved
* TDF_CYCLES: Data Float Time This field gives the integer number of clock cycles required by the external device to release the data after the rising edge of the read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDF_CYCLES period. The external bus cannot be used by another chip select during TDF_CYCLES + 1 cycles. From 0 up to 15 TDF_CYCLES can be set. * TDF_MODE: TDF Optimization 1: TDF optimization is enabled. - The number of TDF wait states is optimized using the setup period of the next read/write access. 0: TDF optimization is disabled. - The number of TDF wait states is inserted before the next access begins. * PMEN: Page Mode Enabled 1: Asynchronous burst read in page mode is applied on the corresponding chip select. 0: Standard read is applied. * PS: Page Size If page mode is enabled, this field indicates the size of the page in bytes.
PS 0 0 1 1 0 1 0 1 Page Size 4-byte page 8-byte page 16-byte page 32-byte page
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22. SDRAM Controller (SDRAMC)
22.1 Description
The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. The SDRAM controller supports a CAS latency of 1, 2 or 3 and optimizes the read access depending on the frequency. The different modes available - self-refresh, power-down and deep power-down modes - minimize power consumption on the SDRAM device.
22.2
I/O Lines Description
Table 22-1.
Name SDCK SDCKE SDCS BA[1:0] RAS CAS SDWE NBS[3:0] SDRAMC_A[12:0] D[31:0]
I/O Line Description
Description SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Data Bus Type Output Output Output Output Output Output Output Output Output I/O Low Low Low Low High Low Active Level
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22.3
22.3.1
Application Example
Software Interface The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller allows mapping different memory types according to the values set in the SDRAMC configuration register. The SDRAM Controller's function is to make the SDRAM device access protocol transparent to the user. Table 22-2 to Table 22-7 illustrate the SDRAM device memory mapping seen by the user in correlation with the device structure. Various configurations are illustrated.
22.3.2
32-bit Memory Data Bus Width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 22-2.
27 26 25
Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0]
Row[10:0] Row[10:0] Row[10:0] Row[10:0]
Column[7:0] Column[8:0] Column[9:0] Column[10:0]
M[1:0] M[1:0] M[1:0] M[1:0]
Table 22-3.
27 26 25
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0]
Row[11:0] Row[11:0] Row[11:0] Row[11:0]
Column[7:0] Column[8:0] Column[9:0] Column[10:0]
M[1:0] M[1:0] M[1:0] M[1:0]
Table 22-4.
27 26 25
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0]
Row[12:0] Row[12:0] Row[12:0] Row[12:0]
Column[7:0] Column[8:0] Column[9:0] Column[10:0]
M[1:0] M[1:0] M[1:0] M[1:0]
Notes:
1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[1] = BA1, Bk[0] = BA0.
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22.3.3 16-bit Memory Data Bus Width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Table 22-5.
Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0]
Row[10:0] Row[10:0] Row[10:0] Row[10:0]
Column[7:0] Column[8:0] Column[9:0] Column[10:0]
M0 M0 M0 M0
Table 22-6.
27 26 25
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0]
Row[11:0] Row[11:0] Row[11:0] Row[11:0]
Column[7:0] Column[8:0] Column[9:0] Column[10:0]
M0 M0 M0 M0
Table 22-7.
27 26 25
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0]
Row[12:0] Row[12:0] Row[12:0] Row[12:0]
Column[7:0] Column[8:0] Column[9:0] Column[10:0]
M0 M0 M0 M0
Notes:
1. M0 is the byte address inside a 16-bit half-word. 2. Bk[1] = BA1, Bk[0] = BA0.
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22.4
22.4.1
Product Dependencies
SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register. 3. The SDRAM memory type must be set in the Memory Device Register. 4. A minimum pause of 200 s is provided to precede any signal toggle. 5.
(1)
A NOP command is issued to the SDRAM devices. The application must set Mode to 1 in the Mode Register and perform a write access to any SDRAM address.
6. An All Banks Precharge command is issued to the SDRAM devices. The application must set Mode to 2 in the Mode Register and perform a write access to any SDRAM address. 7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in the Mode Register and perform a write access to any SDRAM location eight times. 8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular CAS latency and burst length. The application must set Mode to 3 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the address 0x20000000. 9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is issued to program the SDRAM parameters (TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register and perform a write access to the SDRAM. The write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a 16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write access should be done at the address 0x20800000 or 0x20400000. 10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and performing a write access at any location in the SDRAM. 11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh every 15.625 s or 7.81 s. With a 100 MHz frequency, the Refresh Timer Counter Register must be set with the value 1562(15.652 s x 100 MHz) or 781(7.81 s x 100 MHz). After initialization, the SDRAM devices are fully functional.
Note: 1. It is strongly recommended to respect the instructions stated in Step 5 of the initialization process in order to be certain that the subsequent commands issued by the SDRAMC will be taken into account.
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Figure 22-1. SDRAM Device Initialization Sequence
SDCKE tRP tRC tMRD
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
NBS Inputs Stable for 200 sec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command
22.4.2
I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function. If I/O lines of the SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller.
22.4.3
Interrupt The SDRAM Controller interrupt (Refresh Error notification) is connected to the Memory Controller. This interrupt may be ORed with other System Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller). Using the SDRAM Controller interrupt requires the AIC to be programmed first.
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22.5
22.5.1
Functional Description
SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. In both cases, the SDRAM controller keeps track of the active row in each bank, thus maximizing performance. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (tRP) commands and active/write (tRCD) commands. For definition of these timing parameters, refer to the "SDRAMC Configuration Register" on page 241. This is described in Figure 22-2 below.
Figure 22-2. Write Burst, 32-bit SDRAM Access
tRCD = 3 SDCS
SDCK
SDRAMC_A[12:0]
Row n
col a
col b
col c
col d
col e
col f
col g
col h
col i
col j
col k
col l
RAS
CAS
SDWE
D[31:0]
Dna
Dnb
Dnc
Dnd
Dne
Dnf
Dng
Dnh
Dni
Dnj
Dnk
Dnl
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22.5.2 SDRAM Controller Read Cycle The SDRAM Controller allows burst access, incremental burst of unspecified length or single access. In all cases, the SDRAM Controller keeps track of the active row in each bank, thus maximizing performance of the SDRAM. If row and bank addresses do not match the previous row/bank address, then the SDRAM controller automatically generates a precharge command, activates the new row and starts the read command. To comply with the SDRAM timing parameters, additional clock cycles on SDCK are inserted between precharge and active commands (tRP) and between active and read command (tRCD). These two parameters are set in the configuration register of the SDRAM Controller. After a read command, additional wait states are generated to comply with the CAS latency (1, 2 or 3 clock delays specified in the configuration register). For a single access or an incremented burst of unspecified length, the SDRAM Controller anticipates the next access. While the last value of the column is returned by the SDRAM Controller on the bus, the SDRAM Controller anticipates the read to the next column and thus anticipates the CAS latency. This reduces the effect of the CAS latency on the internal bus. For burst access of specified length (4, 8, 16 words), access is not anticipated. This case leads to the best performance. If the burst is broken (border, busy mode, etc.), the next access is handled as an incrementing burst of unspecified length. Figure 22-3. Read Burst, 32-bit SDRAM Access
tRCD = 3 SDCS CAS = 2
SDCK
SDRAMC_A[12:0]
Row n
col a
col b
col c
col d
col e
col f
RAS
CAS
SDWE D[31:0] (Input)
Dna
Dnb
Dnc
Dnd
Dne
Dnf
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22.5.3
Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 22-4 below.
Figure 22-4. Read Burst with Boundary Row Access
TRP = 3 SDCS TRCD = 3 CAS = 2
SDCK Row n
SDRAMC_A[12:0]
col a
col b
col c
col d
Row m
col a
col b
col c
col d
col e
RAS
CAS
SDWE
D[31:0]
Dna
Dnb
Dnc
Dnd
Dma
Dmb
Dmc
Dmd
Dme
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22.5.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles. A refresh error interrupt is generated when the previous auto-refresh command did not perform. It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR). When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is busy and the master is held by a wait signal. See Figure 22-5. Figure 22-5. Refresh Cycle Followed by a Read Access
tRP = 3 SDCS tRC = 8 tRCD = 3 CAS = 2
SDCK Row n
SDRAMC_A[12:0]
col c col d
Row m
col a
RAS
CAS
SDWE
D[31:0] (input)
Dnb
Dnc
Dnd
Dma
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22.5.5
Power Management Three low-power modes are available: * Self-refresh Mode: The SDRAM executes its own Auto-refresh cycle without control of the SDRAM Controller. Current drained by the SDRAM is very low. * Power-down Mode: Auto-refresh cycles are controlled by the SDRAM Controller. Between auto-refresh cycles, the SDRAM is in power-down. Current drained in Power-down mode is higher than in Self-refresh Mode. * Deep Power-down Mode: (Only available with Mobile SDRAM) The SDRAM contents are lost, but the SDRAM does not drain any current. The SDRAM Controller activates one low-power mode as soon as the SDRAM device is not selected. It is possible to delay the entry in self-refresh and power-down mode after the last access by programming a timeout value in the Low Power Register.
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22.5.6 Self-refresh Mode This mode is selected by programming the LPCB field to 1 in the SDRAMC Low Power Register. In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become "don't care" except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode. Some low-power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter or all banks of the SDRAM array. This feature reduces the self-refresh current. To configure this feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR) and Drive Strength (DS) parameters must be set in the Low Power Register and transmitted to the low-power SDRAM during initialization. After initialization, as soon as PASR/DS/TCSR fields are modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR/DS/TCSR bits are updated before entry into self-refresh mode. The SDRAM device must remain in self-refresh mode for a minimum period of tRAS and may remain in self-refresh mode for an indefinite period. This is described in Figure 22-6. Figure 22-6. Self-refresh Mode Behavior
Self Refresh Mode SRCB = 1 Write SDRAMC_SRR SDRAMC_A[12:0] Row TXSR = 3
SDCK
SDCKE
SDCS
RAS
CAS
SDWE Access Request to the SDRAM Controller
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22.5.7
Low-power Mode This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh operations are performed by the SDRAM itself, the SDRAM Controller carries out the refresh operation. The exit procedure is faster than in self-refresh mode. This is described in Figure 22-7.
Figure 22-7. Low-power Mode Behavior
TRCD = 3 SDCS CAS = 2 Low Power Mode
SDCK
SDRAMC_A[12:0]
Row n
col a
col b
col c
col d
col e
col f
RAS
CAS
SDCKE
D[31:0] (input)
Dna
Dnb
Dnc
Dnd
Dne
Dnf
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22.5.8 Deep Power-down Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost. When this mode is enabled, the application must not access to the SDRAM until a new initialization sequence is done (See "SDRAM Device Initialization" on page 228). This is described in Figure 22-8. Figure 22-8. Deep Power-down Mode Behavior
tRP = 3 SDCS
SDCK Row n
SDRAMC_A[12:0]
col c
col d
RAS
CAS
SDWE CKE
D[31:0] (input)
Dnb
Dnc
Dnd
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22.6
SDRAM Controller User Interface
SDRAM Controller Memory Map
Register SDRAMC Mode Register SDRAMC Refresh Timer Register SDRAMC Configuration Register SDRAMC Low Power Register SDRAMC Interrupt Enable Register SDRAMC Interrupt Disable Register SDRAMC Interrupt Mask Register SDRAMC Interrupt Status Register SDRAMC Memory Device Register Reserved Name SDRAMC_MR SDRAMC_TR SDRAMC_CR SDRAMC_LPR SDRAMC_IER SDRAMC_IDR SDRAMC_IMR SDRAMC_ISR SDRAMC_MDR - Access Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only Read - Reset State 0x00000000 0x00000000 0x852372C0 0x0 - - 0x0 0x0 0x0 -
Table 22-8.
Offset 0x00 0x04 0x08 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 - 0xFC
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22.6.1 SDRAMC Mode Register Register Name: SDRAMC_MR Access Type: Reset Value:
31 - 23 - 15 - 7 -
Read/Write 0x00000000
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 MODE 24 - 16 - 8 - 0
* MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed.
MODE 0 0 0 0 0 1 0 1 0 Description Normal mode. Any access to the SDRAM is decoded normally. The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. The address offset with respect to the SDRAM device base address is used to program the Mode Register. For instance, when this mode is activated, an access to the "SDRAM_Base + offset" address generates a "Load Mode Register" command with the value "offset" written to the SDRAM device Mode Register. The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. The SDRAM Controller issues an extended load mode register command when the SDRAM device is accessed regardless of the cycle. The address offset with respect to the SDRAM device base address is used to program the Mode Register. For instance, when this mode is activated, an access to the "SDRAM_Base + offset" address generates an "Extended Load Mode Register" command with the value "offset" written to the SDRAM device Mode Register. Deep power-down mode. Enters deep power-down mode.
0
1
1
1
0
0
1
0
1
1
1
0
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22.6.2 SDRAMC Refresh Timer Register Register Name: SDRAMC_TR Access Type: Reset Value:
31 - 23 - 15 - 7
Read/Write 0x00000000
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 COUNT 27 - 19 - 11 26 - 18 - 10 COUNT 3 2 1 0 25 - 17 - 9 24 - 16 - 8
* COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 s per row is a typical value for a burst of length one. To refresh the SDRAM device, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out.
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22.6.3 SDRAMC Configuration Register Register Name: SDRAMC_CR Access Type: Reset Value:
31
Read/Write 0x852372C0
30 TXSR 29 28 27 26 TRAS 21 TRCD 20 19 18 TRP 13 TRC 12 11 10 TWR 5 CAS 4 NB 3 NR 2 1 NC 0 9 8 17 16 25 24
23
22
15
14
7 DBW
6
* NC: Number of Column Bits Reset value is 8 column bits.
NC 0 0 1 1 0 1 0 1 Column Bits 8 9 10 11
* NR: Number of Row Bits Reset value is 11 row bits.
NR 0 0 1 1 0 1 0 1 Row Bits 11 12 13 Reserved
* NB: Number of Banks Reset value is two banks.
NB 0 1 Number of Banks 2 4
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* CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles are managed. In any case, another value must be programmed.
CAS 0 0 1 1 0 1 0 1 CAS Latency (Cycles) Reserved 1 2 3
* DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. * TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. * TRC: Row Cycle Delay Reset value is seven cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 0 and 15. * TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 0 and 15. * TRCD: Row to Column Delay Reset value is two cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 0 and 15. * TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 0 and 15. * TXSR: Exit Self Refresh to Active Delay Reset value is eight cycles. This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 0 and 15.
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22.6.4 SDRAMC Low Power Register Register Name: SDRAMC_LPR Access Type: Reset Value:
31 - 23 - 15 - 7 -
Read/Write 0x0
30 - 22 - 14 - 6 29 - 21 - 13 TIMEOUT 5 PASR 4 3 - 28 - 20 - 12 27 - 19 - 11 DS 2 - 1 LPCB 26 - 18 - 10 25 - 17 - 9 TCSR 0 24 - 16 - 8
* LPCB: Low-power Configuration Bits
00 Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device. The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters it after the access. The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the access. The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to low-power SDRAM.
01
10
11
* PASR: Partial Array Self-refresh (only for low-power SDRAM) PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set according to the SDRAM device specification. After initialization, as soon as PASR field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and PASR bits are updated before entry in self-refresh mode. * TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM) TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device specification. After initialization, as soon as TCSR field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and TCSR bits are updated before entry in self-refresh mode. * DS: Drive Strength (only for low-power SDRAM) DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter must be set according to the SDRAM device specification.
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After initialization, as soon as DS field is modified and self-refresh mode is activated, the Extended Mode Register is accessed automatically and DS bits are updated before entry in self-refresh mode. * TIMEOUT: Time to define when low-power mode is enabled
00 01 10 11 The SDRAM controller activates the SDRAM low-power mode immediately after the end of the last transfer. The SDRAM controller activates the SDRAM low-power mode 64 clock cycles after the end of the last transfer. The SDRAM controller activates the SDRAM low-power mode 128 clock cycles after the end of the last transfer. Reserved.
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22.6.5 SDRAMC Interrupt Enable Register Register Name: SDRAMC_IER Access Type:
31 - 23 - 15 - 7 -
Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES
* RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt.
22.6.6 SDRAMC Interrupt Disable Register Register Name: SDRAMC_IDR Access Type:
31 - 23 - 15 - 7 -
Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES
* RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt.
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22.6.7 SDRAMC Interrupt Mask Register Register Name: SDRAMC_IMR Access Type:
31 - 23 - 15 - 7 -
Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES
* RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled.
22.6.8 SDRAMC Interrupt Status Register Register Name: SDRAMC_ISR Access Type:
31 - 23 - 15 - 7 -
Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RES
* RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read.
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22.6.9 SDRAMC Memory Device Register Register Name: SDRAMC_MDR Access Type:
31 - 23 - 15 - 7 -
Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 MD 24 - 16 - 8 - 0
* MD: Memory Device Type
00 01 10 11 SDRAM Low-power SDRAM Reserved Reserved.
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23. Error Corrected Code (ECC) Controller
23.1 Description
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data. The ECC controller is capable of single bit error correction and 2-bit random detection. When NAND Flash/SmartMedia have more than 2 bits of errors, the data cannot be corrected. The ECC user interface is compliant with the ARM Advanced Peripheral Bus (APB rev2).
23.2
Block Diagram
Figure 23-1. Block Diagram
Static Memory Controller NAND Flash SmartMedia Logic
ECC Controller
Ctrl/ECC Algorithm
User Interface
APB
23.3
Functional Description
A page in NAND Flash and SmartMedia memories contains an area for main data and an additional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page size corresponds to the number of words in the main data plus the number of words in the extra area used for redundancy.
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The only configuration required for ECC is the NAND Flash or the SmartMedia page size (528/1056/2112/4224). Page size is configured setting the PAGESIZE field in the ECC Mode Register (ECC_MR). ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the SmartMedia is detected. Read and write access must start at a page boundary. ECC is computed as soon as the counter reaches the page size. Values in the ECC Parity Register (ECC_PR) and ECC NParity Register (ECC_NPR) are then valid and locked until a new start condition (read/write command followed by five access address cycles). 23.3.1 Write Access Once the flash memory page is written, the computed ECC code is available in the ECC Parity Error (ECC_PR) and ECC_NParity Error (ECC_NPR) registers. The ECC code value must be written by the software application at the end of the page, in the extra area used for redundancy. 23.3.2 Read Access After reading main data in the page area, the application can perform read access to the extra area used for redundancy. Error detection is automatically performed by the ECC controller. The application can check the ECC Status Register (ECC_SR) for any detected errors. It is up to the application to correct any detected error. ECC computation can detect four different circumstances: * No error: XOR between the ECC computation and the ECC code stored at the end of the NAND Flash or SmartMedia page is equal to 0. No error flags in the ECC Status Register (ECC_SR). * Recoverable error: Only the RECERR flag in the ECC Status register (ECC_SR) is set. The corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity Register (ECC_PR). The corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity Register (ECC_PR). * ECC error: The ECCERR flag in the ECC Status Register is set. An error has been detected in the ECC code stored in the Flash memory. The position of the corrupted bit can be found by the application performing an XOR between the Parity and the NParity contained in the ECC code stored in the flash memory. * Non correctable error: The MULERR flag in the ECC Status Register is set. Several unrecoverable errors have been detected in the flash memory page. ECC Status Register, ECC Parity Register and ECC NParity Register are cleared when a read/write command is detected or a software register is enabled. For single bit Error Correction and double bit Error Detection (SEC-DED) hsiao code is used. 32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-bit words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are generated according to the schemes shown in Figure 23-2 and Figure 23-3.
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Figure 23-2. Parity Generation for 512/1024/2048/4096 8-bit Words1
1st byte 2nd byte 3rd byte 4 th byte Bit7 Bit7 Bit7 Bit7 Bit6 Bit6 Bit6 Bit6 Bit5 Bit5 Bit5 Bit5 Bit4 Bit4 Bit4 Bit4 Bit3 Bit3 Bit3 Bit3 Bit2 Bit2 Bit2 Bit2 Bit1 Bit1 Bit1 Bit1 Bit0 Bit0 Bit0 Bit0 P8 P8' P8 P8' P16 P32 P16' PX
(page size -3 )th byte (page size -2 )th byte (page size -1 )th byte Page size th byte
Bit7 Bit7 Bit7 Bit7 P1 P2
Bit6 Bit6 Bit6 Bit6 P1'
Bit5 Bit5 Bit5 Bit5 P1
Bit4 Bit4 Bit4 Bit4 P1' P2'
Bit3 Bit3 Bit3 Bit3 P1 P2
Bit2 Bit2 Bit2 Bit2 P1'
Bit1 Bit1 Bit1 Bit1 P1 P2' P4'
Bit0 Bit0 Bit0 Bit0 P1'
P8 P8' P8 P8'
P16 P32 P16' PX'
P4
Page size Page size Page size Page size
= 512 = 1024 = 2048 = 4096
Px = 2048 Px = 4096 Px = 8192 Px = 16384
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4 P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1' P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2' P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
To calculate P8' to PX' and P8 to PX, apply the algorithm that follows.
Page size = 2n for i =0 to n begin for (j = 0 to page_size_byte) begin if(j[i] ==1) P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3] else P[2i+3]'=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end
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1st word 2nd word
3rd word 4th word
Figure 23-3. Parity Generation for 512/1024/2048/4096 16-bit Words
(Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word
(+)
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To calculate P8' to PX' and P8 to PX, apply the algorithm that follows.
Page size = 2n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2n+3] else P[2i+3]'=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end
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23.4 Error Corrected Code (ECC) Controller User Interface
Register Mapping
Register ECC Control Register ECC Mode Register ECC Status Register ECC Parity Register ECC NParity Register Reserved Register Name ECC_CR ECC_MR ECC_SR ECC_PR ECC_NPR - Access Write-only Read/Write Read-only Read-only Read-only - Reset 0x0 0x0 0x0 0x0 0x0 -
Table 23-1.
Offset 0x00 0x04 0x8 0x0C 0x10 0x14 - 0xFC
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23.4.1 Name: Access Type:
31 - 23 - 15 - 7 -
ECC Control Register ECC_CR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 RST
* RST: RESET Parity Provides reset to current ECC by software. 1: Resets ECC Parity and ECC NParity register 0: No effect
23.4.2
ECC Mode Register ECC_MR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 PAGESIZE 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* PAGESIZE: Page Size This field defines the page size of the NAND Flash device.
Page Size 00 01 10 11 Description 528 words 1056 words 2112 words 4224 words
A word has a value of 8 bits or 16 bits, depending on the NAND Flash or Smartmedia memory organization.
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23.4.3 ECC Status Register ECC_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 MULERR 25 - 17 - 9 - 1 ECCERR 24 - 16 - 8 - 0 RECERR
Register Name: Access Type:
31 - 23 - 15 - 7 -
* RECERR: Recoverable Error 0 = No Errors Detected 1 = Errors Detected. If MUL_ERROR is 0, a single correctable error was detected. Otherwise multiple uncorrected errors were detected * ECCERR: ECC Error 0 = No Errors Detected 1 = A single bit error occurred in the ECC bytes. Read both ECC Parity and ECC NParity register, the error occurred at the location which contains a 1 in the least significant 16 bits. * MULERR: Multiple Error 0 = No Multiple Errors Detected 1 = Multiple Errors Detected
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23.4.4 ECC Parity Register ECC_PR Read-only
30 - 22 - 14 6 WORDADDR 29 - 21 - 13 5 28 - 20 - 12 WORDADDR 7 4 3 2 BITADDR 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
During a page write, the value of the entire register must be written in the extra area used for redundancy (for a 512-byte page size: address 512-513) * BITADDR During a page read, this value contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. * WORDADDR During a page read, this value contains the word address (8-bit or 16-bit word depending on the memory plane organization) where an error occurred, if a single error was detected. If multiple errors were detected, this value is meaningless. 23.4.5 ECC NParity Register ECC_NPR Read-only
30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 NPARITY 7 4 NPARITY 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* NPARITY During a write, the value of this register must be written in the extra area used for redundancy (for a 512-byte page size: address 514-515)
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24. DMA Controller (DMAC)
24.1 Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMA data transfer. This is also known as a dual-access transfer. The DMAC is programmed via the AHB slave interface.
24.2
Block Diagram
Figure 24-1. DMA Controller (DMAC) Block Diagram
DMA Controller
AHB Slave
AHB Slave Interface
CFG
Interrupt Generator
irq_dma
Channel 1 Channel 0
AHB Master
AHB Master Interface
FIFO
SRC FSM
DST FSM
DMARQ0..3
Hardware Handshaking Interface
24.3
24.3.1
Functional Description
Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral).
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Memory: Source or destination that is always "ready" for a DMA transfer and does not require a handshaking interface to interact with the DMAC. A peripheral should be assigned as memory only if it does not insert more than 16 wait states. If more than 16 wait states are required, then the peripheral should use a handshaking interface (the default if the peripheral is not programmed to be memory) in order to signal when it is ready to accept or supply data. Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. If the source peripheral is not memory, then a source handshaking interface is assigned to the channel. If the destination peripheral is not memory, then a destination handshaking interface is assigned to the channel. Source and destination handshaking interfaces can be assigned dynamically by programming the channel registers. Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over the AHB bus. Slave interface: The AHB interface over which the DMAC is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. Handshaking interface: A set of signal registers that conform to a protocol and handshake between the DMAC and source or destination peripheral to control the transfer of a single or burst transaction between them. This interface is used to request, acknowledge, and control a DMAC transaction. A channel can receive a request through one of three types of handshaking interface: hardware, software, or peripheral interrupt. Hardware handshaking interface: Uses hardware signals to control the transfer of a single or burst transaction between the DMAC and the source or destination peripheral. Software handshaking interface: Uses software registers to control the transfer of a single or burst transaction between the DMAC and the source or destination peripheral. No special DMAC handshaking signals are needed on the I/O of the peripheral. This mode is useful for interfacing an existing peripheral to the DMAC without modifying it. Peripheral interrupt handshaking interface: A simple use of the hardware handshaking interface. In this mode, the interrupt line from the peripheral is tied to the dma_req input of the hardware handshaking interface. Other interface signals are ignored. Flow controller: The device (either the DMAC or source/destination peripheral) that determines the length of and terminates a DMA block transfer. If the length of a block is known before enabling the channel, then the DMAC should be programmed as the flow controller. If the length of a block is not known prior to enabling the channel, the source or destination peripheral needs to terminate a block transfer. In this mode, the peripheral is the flow controller. Flow control mode (DMAC_CFGx.FCMODE): Special mode that only applies when the destination peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral. Transfer hierarchy: Figure 24-2 on page 261 illustrates the hierarchy between DMAC transfers, block transfers, transactions (single or burst), and AMBA transfers (single or burst) for non-memory peripherals. Figure 24-3 on page 261 shows the transfer hierarchy for memory.
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Figure 24-2. DMAC Transfer Hierarchy for Non-Memory Peripheral
DMAC Transfer
DMA Transfer Level
Block
Block
Block
Block Transfer Level
Burst Transaction
Burst Transaction
Burst Transaction
Single Transaction
DMA Transaction Level
AMBA Burst Transfer
AMBA Burst Transfer
AMBA Burst Transfer
AMBA Single Transfer
AMBA Single Transfer
AMBA Transfer Level
Figure 24-3. DMAC Transfer Hierarchy for Memory
DMAC Transfer
DMA Transfer Level Block Transfer Level
Block
Block
Block
AMBA Burst Transfer
AMBA Burst Transfer
AMBA Burst Transfer
AMBA Single Transfer
AMBA Transfer Level
Block: A block of DMAC data. The amount of data (block length) is determined by the flow controller. For transfers between the DMAC and memory, a block is broken directly into a sequence of AMBA bursts and AMBA single transfers. For transfers between the DMAC and a non-memory peripheral, a block is broken into a sequence of DMAC transactions (single and bursts). These are in turn broken into a sequence of AMBA transfers. Transaction: A basic unit of a DMAC transfer as determined by either the hardware or software handshaking interface. A transaction is only relevant for transfers between the DMAC and a source or destination peripheral if the source or destination peripheral is a non-memory device. There are two types of transactions: single and burst. - Single transaction: The length of a single transaction is always 1 and is converted to a single AMBA transfer. - Burst transaction: The length of a burst transaction is programmed into the DMAC. The burst transaction is converted into a sequence of AMBA bursts and AMBA single transfers. DMAC executes each AMBA burst transfer by performing incremental bursts that are no longer than the maximum AMBA burst size set. The burst transaction length is under program control and normally bears some 261
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relationship to the FIFO sizes in the DMAC and in the source and destination peripherals. DMA transfer: Software controls the number of blocks in a DMAC transfer. Once the DMA transfer has completed, then hardware within the DMAC disables the channel and can generate an interrupt to signal the completion of the DMA transfer. You can then re-program the channel for a new DMA transfer. Single-block DMA transfer: Consists of a single block. Multi-block DMA transfer: A DMA transfer may consist of multiple DMAC blocks. Multi-block DMA transfers are supported through block chaining (linked list pointers), auto-reloading of channel registers, and contiguous blocks. The source and destination can independently select which method to use. - Linked lists (block chaining) - A linked list pointer (LLP) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next block (block descriptor) and an LLP register. The DMAC fetches the LLI at the beginning of every block when block chaining is enabled. - Auto-reloading - The DMAC automatically reloads the channel registers at the end of each block to the value when the channel was first enabled. - Contiguous blocks - Where the address between successive blocks is selected to be a continuation from the end of the previous block. Scatter: Relevant to destination transfers within a block. The destination AMBA address is incremented/decremented by a programmed amount when a scatter boundary is reached. The number of AMBA transfers between successive scatter boundaries is under software control. Gather: Relevant to source transfers within a block. The source AMBA address is incremented/decremented by a programmed amount when a gather boundary is reached. The number of AMBA transfers between successive gather boundaries is under software control. Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for the master bus interface for the duration of a DMA transfer, block, or transaction (single or burst). Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hlock for the duration of a DMA transfer, block, or transaction (single or burst). Channel locking is asserted for the duration of bus locking at a minimum. FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is greater than or equal to half full to send data to the destination peripheral. Thus, the channel can transfer the data using AMBA bursts, eliminating the need to arbitrate for the AHB master interface for each single AMBA transfer. When this mode is not enabled, the channel only waits until the FIFO can transmit/accept a single AMBA transfer before requesting the master bus interface. Pseudo fly-by operation: Typically, it takes two AMBA bus cycles to complete a transfer, one for reading the source and one for writing to the destination. However, when the source and destination peripherals of a DMA transfer are on different AMBA layers, it is possible for the DMAC to fetch data from the source and store it in the channel FIFO at the same time as the DMAC extracts data from the channel FIFO and writes it to the destination peripheral. This
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activity is known as pseudo fly-by operation. For this to occur, the master interface for both source and destination layers must win arbitration of their AHB layer. Similarly, the source and destination peripherals must win ownership of their respective master interfaces. 24.3.2 Memory Peripherals Figure 24-3 on page 261 shows the DMA transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data, and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus. Handshaking Interface Handshaking interfaces are used at the transaction level to control the flow of single or burst transactions. The operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow controller. The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over the AMBA bus. A non-memory peripheral can request a DMA transfer through the DMAC using one of two handshaking interfaces: * Hardware handshaking * Software handshaking Software selects between the hardware or software handshaking interface on a per-channel basis. Software handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished using a dedicated handshaking interface. 24.3.3.1 Software Handshaking When the slave peripheral requires the DMAC to perform a DMA transaction, it communicates this request by sending an interrupt to the CPU or interrupt controller. The interrupt service routine then uses the software registers to initiate and control a DMA transaction. These software registers are used to implement the software handshaking interface. The HS_SEL_SRC/HS_SEL_DST bit in the DMAC_CFGx channel configuration register must be set to enable software handshaking. When the peripheral is not the flow controller, then the last transaction registers DMAC_LstSrcReg and DMAC_LstDstReg are not used, and the values in these registers are ignored. Burst Transactions Writing a 1 to the DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] register is always interpreted as a burst transaction request, where x is the channel number. However, in order for a burst transaction request to start, software must write a 1 to the DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] register.
24.3.3
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You can write a 1 to the DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] and DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers in any order, but both registers must be asserted in order to initiate a burst transaction. Upon completion of the burst transaction, the hardware clears the DMAC_SglReqSrcReg[x]/DMAC_SglReqDstReg[x] and DMAC_ReqSrcReg[x]/DMAC_ReqDstReg[x] registers. Single Transactions Writing a 1 to the DMAC_SglReqSrcReg/DMAC_SglReqDstReg initiates a single transaction. Upon completion of the single transaction, both the DMAC_SglReqSrcReg/DMAC_SglReqDstReg and DMAC_ReqSrcReg/DMAC_ReqDstReg bits are cleared by hardware. Therefore, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg is ignored while a single transaction has been initiated, and the requested burst transaction is not serviced. Again, writing a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg register is always a burst transaction request. However, in order for a burst transaction request to start, the corresponding channel bit in the DMAC_SglReqSrcReg/DMAC_SglReqDstReg must be asserted. Therefore, to ensure that a burst transaction is serviced, you must write a 1 to the DMAC_ReqSrcReg/DMAC_ReqDstReg before writing a 1 to the DMAC_SglReqSrcReg/DMAC_SglReqDstReg register. Software can poll the relevant channel bit in the DMAC_SglReqSrcReg/ DMAC_SglReqDstReg and DMAC_ReqSrcReg/DMAC_ReqDstReg registers. When both are 0, then either the requested burst or single transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled and unmasked in order to generate an interrupt when the requested source or destination transaction has completed.
Note: The transaction-complete interrupts are triggered when both single and burst transactions are complete. The same transaction-complete interrupt is used for both single and burst transactions.
24.3.3.2
Hardware Handshaking There are 5 hardware handshaking interfaces connected to four external DMA requests (see Table 24-1 on page 264). Table 24-1.
Request DMAREQ0 DMAREQ1 DMAREQ2 DMAREQ3
Hardware Handshaking Connection
Definition External DMA Request 0 External DMA Request 1 External DMA Request 2 External DMA Request 3 Hardware Handshaking Interface 1 2 3 4
External DMA Request Definition When an external slave peripheral requires the DMAC to perform DMA transactions, it communicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to ensure a proper functionality (see "External DMA Request Timing" on page 265).
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The external nDMAREQx is asserted when the source threshold level is reached. After resynchronization, the rising edge of dma_req starts the transfer. dma_req is de-asserted when dma_ack is asserted. The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted again before a new transaction starts. For a source FIFO, an active edge is triggered on nDMAREQx when the source FIFO exceeds a watermark level. For a destination FIFO, an active edge is triggered on nDMAREQx when the destination FIFO drops below the watermark level. The source transaction length, CTLx.SRC_MSIZE, and destination transaction length, CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination peripherals. Figure 24-4. External DMA Request Timing
Hclk
DMA Transaction
nDMAREQx
dma_req
DMA Transfers DMA Transfers DMA Transfers
dma_ack
24.3.4
DMAC Transfer Types A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multiblock transfer, the DMAC_SARx/DMAC_DARx register in the DMAC is reprogrammed using either of the following methods: * Block chaining using linked lists * Auto-reloading * Contiguous address between blocks On successive blocks of a multi-block transfer, the DMAC_CTLx register in the DMAC is reprogrammed using either of the following methods: * Block chaining using linked lists * Auto-reloading When block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the DMAC_LLPx register in the DMAC is re-programmed using the following method: * Block chaining using linked lists A block descriptor (LLI) consists of following registers, DMAC_SARx, DMAC_DARx, DMAC_LLPx, DMAC_CTLx. These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the block transfer.
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24.3.4.1 Multi-block Transfers Block Chaining Using Linked Lists In this case, the DMAC re-programs the channel registers prior to the start of each block by fetching the block descriptor for that block from system memory. This is known as an LLI update. DMAC block chaining is supported by using a Linked List Pointer register (DMAC_LLPx) that stores the address in memory of the next linked list item. Each LLI (block descriptor) contains the corresponding block descriptor (DMAC_SARx, DMAC_DARx, DMAC_LLPx, DMAC_CTLx). To set up block chaining, a sequence of linked lists must be programmed in memory. The DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx registers are fetched from system memory on an LLI update. Figure 24-5 on page 266 shows how to use chained linked lists in memory to define multi-block transfers using block chaining. The Linked List multi-block transfers is initiated by programming DMAC_LLPx with LLPx(0) ( L L I ( 0 ) b a s e a d d r e s s ) a n d D M AC _ C T L x w i t h D M A C _ C T L x . L L P _ S _ E N a n d DMAC_CTLx.LLP_D_EN. Figure 24-5. Multi-block Transfer Using Linked Lists
LLI(0)
System Memory
LLI(1)
CTLx[63..32] CTLx[31..0] LLPx(1) DARx SARx
CTLx[63..32] CTLx[31..0] LLPx(2) DARx SARx LLPx(1) LLPx(2)
LLPx(0)
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Table 24-2. Programming of Transfer Types and Channel Register Update Method (DMAC State Machine Table)
LLP. Transfer Type LOC =0 1) Single Block or last transfer of multi-Block 2) AutoReload multi-block transfer with contiguous SAR 3) AutoReload multi-block transfer with contiguous DAR 4) AutoReload multi-block transfer Yes LLP_S_EN (DMAC_ CTLx) 0 RELOAD _SR (DMAC_ CFGx) 0 LLP_D_EN (DMAC_ CTLx) 0 RELOAD_ DS (DMAC_ CFGx) 0 DMAC_CTLx, DMAC_LLPx Update Method None, user reprograms DMAC_CTLx,D MAC_LLPx are reloaded from initial values. DMAC_CTLx,D MAC_LLPx are reloaded from initial values. DMAC_CTLx,D MAC_LLPx are reloaded from initial values. DMAC_CTLx,D MAC_LLPx loaded from next Linked List item DMAC_CTLx,D MAC_LLPx loaded from next Linked List item DMAC_CTLx,D MAC_LLPx loaded from next Linked List item DMAC_CTLx,D MAC_LLPx loaded from next Linked List item DMAC_CTLx,D MAC_LLPx loaded from next Linked List item DMAC_SARx Update Method None (single) DMAC_ DARx Update Method None (single)
- -
Yes
0
0
0
1
Contiguous
AutoReload
-
Yes
0
1
0
0
Auto-Reload
Contiguous
-
Yes
0
1
0
1
Auto-Reload
AutoReload
-
6) Linked List multi-block transfer with contiguous SAR 7) Linked List multi-block transfer with auto-reload SAR 8) Linked List multi-block transfer with contiguous DAR 9) Linked List multi-block transfer with auto-reload DAR
No
0
0
1
0
Contiguous
Linked List
-
No
0
1
1
0
Auto-Reload
Linked List
-
No
1
0
0
0
Linked List
Contiguous
-
No
1
0
0
1
Linked List
AutoReload
-
10) Linked List multi-block transfer
No
1
0
1
0
Linked List
Linked List
-
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Auto-reloading of Channel Registers During auto-reloading, the channel registers are reloaded with their initial values at the completion of each block and the new values used for the new block. Depending on the row number in Table 24-2 on page 267, some or all of the DMAC_SARx, DMAC_DARx and DMAC_CTLx channel registers are reloaded from their initial value at the start of a block transfer. Contiguous Address Between Blocks In this case, the address between successive blocks is selected to be a continuation from the end of the previous block. Enabling the source or destination address to be contiguous between blocks is a function of DMAC_CTLx.LLP_S_EN, DMAC_CFGx.RELOAD_SR, DMAC_CTLx.LLP_D_EN, and DMAC_CFGx.RELOAD_DS registers (see Figure 24-2 on page 267).
Note: Both DMAC_SARx and DMAC_DARx updates cannot be selected to be contiguous. If this functionality is required, the size of the Block Transfer (DMAC_CTLx.BLOCK_TS) must be increased. If this is at the maximum value, use Row 10 of Table 24-2 on page 267 and setup the LLI.DMAC_SARx address of the block descriptor to be equal to the end DMAC_SARx address of the previous block. Similarly, setup the LLI.DMAC_DARx address of the block descriptor to be equal to the end DMAC_DARx address of the previous block.
Suspension of Transfers Between Blocks At the end of every block transfer, an end of block interrupt is asserted if: * interrupts are enabled, DMAC_CTLx.INT_EN = 1 * the channel block interrupt is unmasked, DMAC_MaskBlock[n] = 0, where n is the channel number.
Note: The block complete interrupt is generated at the completion of the block transfer to the destination.
For rows 6, 8, and 10 of Table 24-2 on page 267, the DMA transfer does not stall between block transfers. For example, at the end of block N, the DMAC automatically proceeds to block N + 1. For rows 2, 3, 4, 7, and 9 of Table 24-2 on page 267 (DMAC_SARx and/or DMAC_DARx autoreloaded between block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted if the end of block interrupt is enabled and unmasked. The DMAC does not proceed to the next block transfer until a write to the block interrupt clear register, DMAC_ClearBlock[n], is performed by software. This clears the channel block complete interrupt. For rows 2, 3, 4, 7, and 9 of Table 24-2 on page 267 (DMAC_SARx and/or DMAC_DARx autoreloaded between block transfers), the DMA transfer does not stall if either: * interrupts are disabled, DMAC_CTLx.INT_EN = 0, or * the channel block interrupt is masked, DMAC_MaskBlock[n] = 1, where n is the channel number. Channel suspension between blocks is used to ensure that the end of block ISR (interrupt service routine) of the next-to-last block is serviced before the start of the final block commences. This ensures that the ISR has cleared the DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS bits before completion of the final block. The reload bits DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS should be cleared in the `end of block ISR' for the next-to-last block transfer.
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24.3.4.2 Ending Multi-block Transfers All multi-block transfers must end as shown in Row 1 of Table 24-2 on page 267. At the end of every block transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous block transferred was the last block and the DMA transfer is terminated. For rows 2,3 and 4 of Table 24-2 on page 267, (DMAC_LLPx = 0 and DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS is set), multi-block DMA transfers continue until both the DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS registers are cleared by software. They should be programmed to zero in the end of block interrupt service routine that services the next-to-last block transfer. This puts the DMAC into Row 1 state.
Note:
For rows 6, 8, and 10 (both DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS cleared) the user must setup the last block descriptor in memory such that both LLI.DMAC_CTLx.LLP_S_EN and LLI.DMAC_CTLx.LLP_D_EN are zero. For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block transfer should clear the DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS reload bits. The last block descriptor in memory should be set up so that both the LLI.DMAC_CTLx.LLP_S_EN and LLI.DMAC_CTLx.LLP_D_EN are zero.
24.3.5
Programming a Channel Three registers, the DMAC_LLPx, the DMAC_CTLx and DMAC_CFGx, need to be programmed to set up whether single or multi-block transfers take place, and which type of multiblock transfer is used. The different transfer types are shown in Table 24-2 on page 267. The "Update Method" column indicates where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next block transfer when multi-block DMAC transfers are enabled.
Note: In Table 24-2 on page 267, all other combinations of DMAC_LLPx.LOC = 0, DMAC_CTLx.LLP_S_EN, DMAC_CFGx.RELOAD_SR, DMAC_CTLx.LLP_D_EN, and DMAC_CFGx.RELOAD_DS are illegal, and causes indeterminate or erroneous behavior.
24.3.5.1 Programming Examples Single-block Transfer (Row 1) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3. Program the following channel registers: a. Write the starting source address in the DMAC_SARx register for channel x. b. c. Write the starting destination address in the DMAC_DARx register for channel x. Program DMAC_CTLx and DMAC_CFGx according to Row 1 as shown in Table 24-2 on page 267. Program the DMAC_LLPx register with `0'.
d. Write the control information for the DMA transfer in the DMAC_CTLx register for channel x. For example, in the register, you can program the following: - i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the DMAC_CTLx register.
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- ii. Set up the transfer characteristics, such as: - Transfer width for the source in the SRC_TR_WIDTH field. - Transfer width for the destination in the DST_TR_WIDTH field. - Source master layer in the SMS field where source resides. - Destination master layer in the DMS field where destination resides. - Incrementing/decrementing or fixed address for source in SINC field. - Incrementing/decrementing or fixed address for destination in DINC field. e. Write the channel configuration information into the DMAC_CFGx register for channel x. - i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests. Writing a `1' activates the software handshaking interface to handle source/destination requests. - ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. f. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel x.
g. If scatter is enabled (DMAC_CTLx.D_SCAT_EN, program the DMAC_DSRx register for channel x. 4. After the DMAC selected channel has been programmed, enable the channel by writing a `1' to the DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled. 5. Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. 6. Once the transfer completes, hardware sets the interrupts and disables the channel. At this time you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (DMAC_ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. Write the control information in the LLI.DMAC_CTLx register location of the block descriptor for each LLI in memory (see Figure 24-5 on page 266) for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the DMAC_CTLx register. b. Set up the transfer characteristics, such as: - i. Transfer width for the source in the SRC_TR_WIDTH field. - ii. Transfer width for the destination in the DST_TR_WIDTH field.
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- iii. Source master layer in the SMS field where source resides. - iv. Destination master layer in the DMS field where destination resides. - v. Incrementing/decrementing or fixed address for source in SINC field. - vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign the handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively.
4. Make sure that the LLI.DMAC_CTLx register locations of all LLI entries in memory (except the last) are set as shown in Row 10 of Table 24-2 on page 267. The LLI.DMAC_CTLx register of the last Linked List Item must be set as described in Row 1 of Table 24-2. Figure 24-7 on page 273 shows a Linked List example with two list items. 5. Make sure that the LLI.DMAC_LLPx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item. 6. Make sure that the LLI.DMAC_SARx/LLI.DMAC_DARx register locations of all LLI entries in memory point to the start source/destination block address preceding that LLI fetch. 7. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register locations of all LLI entries in memory are cleared. 8. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel x. 9. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx register for channel x. 10. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 11. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 10 as shown in Table 24-2 on page 267. 12. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked List item. 13. Finally, enable the channel by writing a `1' to the DMAC_ChEnReg.CH_EN bit. The transfer is performed. 14. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
Note: The LLI.DMAC_SARx, LLI. DMAC_DARx, LLI.DMAC_LLPx and LLI.DMAC_CTLx registers are fetched. The DMAC automatically reprograms the DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx channel registers from the DMAC_LLPx(0).
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15. Source and destination request single and burst DMA transactions to transfer the block of data (assuming non-memory peripheral). The DMAC acknowledges at the completion of every transaction (burst and single) in the block and carry out the block transfer. 16. The DMAC does not wait for the block interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current DMAC_LLPx register and automatically reprograms the DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx channel registers. The DMA transfer continues until the DMAC determines that the DMAC_CTLx and DMAC_LLPx registers at the end of a block transfer match that described in Row 1 of Table 24-2 on page 267. The DMAC then knows that the previous block transferred was the last block in the DMA transfer. The DMA transfer might look like that shown in Figure 24-6 on page 272. Figure 24-6. Multi-Block with Linked List Address for Source and Destination
Address of Source Layer
Address of Destination Layer
Block 2 SAR(2) DAR(2)
Block 2
Block 1 SAR(1) DAR(1)
Block 1
Block 0 SAR(0) Source Blocks DAR(0)
Block 0
Destination Blocks
If the user needs to execute a DMA transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum block size DMAC_CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in Figure 24-7 on page 273.
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Figure 24-7. Multi-Block with Linked Address for Source and Destination Blocks are Contiguous
Address of Source Layer
Address of Destination Layer
Block 2 DAR(3) Block 2 SAR(3) Block 2 SAR(2) Block 1 SAR(1) Block 0 SAR(0) Block 0 DAR(0) Block 1 DAR(1) Block 2 DAR(2)
Source Blocks
Destination Blocks
The DMA transfer flow is shown in Figure 24-8 on page 274.
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Figure 24-8. DMA Transfer Flow for Source and Destination Linked List Address
Channel enabled by software
LLI Fetch
Hardware reprograms SARx, DARx, CTLx, LLPx
DMAC block transfer
Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row1 of DMAC State Machine Table?
no
DMAC transfer Complete interrupt generated here
yes Channel Disabled by hardware
Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4) 1. Read the Channel Enable register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3. Program the following channel registers:
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a. Write the starting source address in the DMAC_SARx register for channel x. b. c. Write the starting destination address in the DMAC_DARx register for channel x. Program DMAC_CTLx and DMAC_CFGx according to Row 4 as shown in Table 24-2 on page 267. Program the DMAC_LLPx register with `0'.
d. Write the control information for the DMA transfer in the DMAC_CTLx register for channel x. For example, in the register, you can program the following: - i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the DMAC_CTLx register. - ii. Set up the transfer characteristics, such as: - Transfer width for the source in the SRC_TR_WIDTH field. - Transfer width for the destination in the DST_TR_WIDTH field. - Source master layer in the SMS field where source resides. - Destination master layer in the DMS field where destination resides. - Incrementing/decrementing or fixed address for source in SINC field. - Incrementing/decrementing or fixed address for destination in DINC field. e. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel x. f. If scatter is enabled (DMAC_CTLx.D_SCAT_EN), program the DMAC_DSRx register for channel x.
g. Write the channel configuration information into the DMAC_CFGx register for channel x. Ensure that the reload bits, DMAC_CFGx. RELOAD_SR and DMAC_CFGx.RELOAD_DS are enabled. - i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. - ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 4. After the DMAC selected channel has been programmed, enable the channel by writing a `1' to the DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled. 5. Source and destination request single and burst DMAC transactions to transfer the block of data (assuming non-memory peripherals). The DMAC acknowledges on completion of each burst/single transaction and carry out the block transfer. 6. When the block transfer has completed, the DMAC reloads the DMAC_SARx, DMAC_DARx and DMAC_CTLx registers. Hardware sets the Block Complete interrupt. The DMAC then samples the row number as shown in Table 24-2 on page 267. If the DMAC is in Row 1, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (DMAC_ChEnReg.CH_EN) bit until it is disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 7. The DMA transfer proceeds as follows:
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a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete interrupt is un-masked (DMAC_MaskBlock[x] = 1'b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the reload bits in the DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS registers. This put the DMAC into Row 1 as shown in Table 24-2 on page 267. If the next block is not the last block in the DMA transfer, then the reload bits should remain enabled to keep the DMAC in Row 4. b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt is masked (DMAC_MaskBlock[x] = 1'b0, where x is the channel number), then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case software must clear the reload bits in the DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS registers to put the DMAC into ROW 1 of Table 24-2 on page 267 before the last block of the DMA transfer has completed. The transfer is similar to that shown in Figure 24-9 on page 276. The DMA transfer flow is shown in Figure 24-10 on page 277.
Figure 24-9. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
Address of Source Layer Address of Destination Layer
Block0 Block1 Block2
SAR
DAR
BlockN
Source Blocks
Destination Blocks
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Figure 24-10. DMA Transfer Flow for Source and Destination Address Auto-reloaded
Channel Enabled by software
Block Transfer
Reload SARx, DARx, CTLx Block Complete interrupt generated here DMAC transfer Complete interrupt generated here
yes
Is DMAC in Row1 of DMAC State Machine Table?
Channel Disabled by hardware
no
CTLx.INT_EN=1 && MASKBLOCK[x]=1?
no
yes
Stall until block complete interrupt cleared by software
Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row7) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of linked list items (otherwise known as block descriptors) in memory. Write the control information in the LLI.DMAC_CTLx register location of the block descriptor for each LLI in memory for channel x. For example, in the register you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control peripheral by programming the TT_FC of the DMAC_CTLx register. b. Set up the transfer characteristics, such as: - i. Transfer width for the source in the SRC_TR_WIDTH field. - ii. Transfer width for the destination in the DST_TR_WIDTH field. - iii. Source master layer in the SMS field where source resides. - iv. Destination master layer in the DMS field where destination resides. - v. Incrementing/decrementing or fixed address for source in SINC field.
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- vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the starting source address in the DMAC_SARx register for channel x.
Note: The values in the LLI.DMAC_SARx register locations of each of the Linked List Items (LLIs) setup up in memory, although fetched during a LLI fetch, are not used.
4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively.
5. Make sure that the LLI.DMAC_CTLx register locations of all LLIs in memory (except the last) are set as shown in Row 7 of Table 24-2 on page 267 while the LLI.DMAC_CTLx register of the last Linked List item must be set as described in Row 1 of Table 24-2. Figure 24-5 on page 266 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_LLPx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_DARx register location of all LLIs in memory point to the start destination block address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register locations of all LLIs in memory is cleared. 9. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel x. 10. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 7 as shown in Table 24-2 on page 267. 13. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a `1' to the DMAC_ChEnReg.CH_EN bit. The transfer is performed. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
Note: The LLI.DMAC_SARx, LLI.DMAC_DARx, LLI. DMAC_LLPx and LLI.DMAC_CTLx registers are fetched. The LLI.DMAC_SARx register although fetched is not used.
16. Source and destination request single and burst DMAC transactions to transfer the block of data (assuming non-memory peripherals). DMAC acknowledges at the com-
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pletion of every transaction (burst and single) in the block and carry out the block transfer. 17. The DMAC reloads the DMAC_SARx register from the initial value. Hardware sets the block complete interrupt. The DMAC samples the row number as shown in Table 24-2 on page 267. If the DMAC is in Row 1 or 5, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. You can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (DMAC_ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1 or 5 as shown in Table 24-2 on page 267 the following steps are performed. 18. The DMA transfer proceeds as follows: a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete interrupt is un-masked (DMAC_MaskBlock[x] = 1'b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the DMAC_CFGx.RELOAD_SR source reload bit. This puts the DMAC into Row1 as shown in Table 24-2 on page 267. If the next block is not the last block in the DMA transfer, then the source reload bit should remain enabled to keep the DMAC in Row 7 as shown in Table 24-2 on page 267. b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt is masked (DMAC_MaskBlock[x] = 1'b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case, software must clear the source reload bit, DMAC_CFGx.RELOAD_SR, to put the device into Row 1 of Table 24-2 on page 267 before the last block of the DMA transfer has completed.
19. The DMAC fetches the next LLI from memory location pointed to by the current DMAC_LLPx register, and automatically reprograms the DMAC_DARx, DMAC_CTLx and DMAC_LLPx channel registers. Note that the DMAC_SARx is not re-programmed as the reloaded value is used for the next DMA block transfer. If the next block is the last block of the DMA transfer then the DMAC_CTLx and DMAC_LLPx registers just fetched from the LLI should match Row 1 of Table 24-2 on page 267. The DMA transfer might look like that shown in Figure 24-11 on page 280.
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Figure 24-11. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List Destination Address
Address of Source Layer
Address of Destination Layer
Block0 DAR(0) Block1 DAR(1) SAR Block2 DAR(2)
BlockN DAR(N)
Source Blocks
Destination Blocks
The DMA Transfer flow is shown in Figure on page 281
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DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destination Address
Channel Enabled by software
LLI Fetch Hardware reprograms DARx, CTLx, LLPx DMAC block transfer
Source/destination status fetch
Reload SARx Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes Is DMAC in Row1 or Row5 of DMAC State Machine Table?
Channel Disabled by hardware
no
CTLx.INT_EN=1 && MASKBLOCK[X]=1 ?
no
yes Stall until block interrupt Cleared by hardware
Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 3. Program the following channel registers:
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a. Write the starting source address in the DMAC_SARx register for channel x. b. c. Write the starting destination address in the DMAC_DARx register for channel x. Program DMAC_CTLx and DMAC_CFGx according to Row 3 as shown in Table 24-2 on page 267. Program the DMAC_LLPx register with `0'.
d. Write the control information for the DMA transfer in the DMAC_CTLx register for channel x. For example, in this register, you can program the following: - i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the DMAC_CTLx register. - ii. Set up the transfer characteristics, such as: - Transfer width for the source in the SRC_TR_WIDTH field. - Transfer width for the destination in the DST_TR_WIDTH field. - Source master layer in the SMS field where source resides. - Destination master layer in the DMS field where destination resides. - Incrementing/decrementing or fixed address for source in SINC field. - Incrementing/decrementing or fixed address for destination in DINC field. e. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel x. f. If scatter is enabled (DMAC_CTLx.D_SCAT_EN), program the DMAC_DSRx register for channel x.
g. Write the channel configuration information into the DMAC_CFGx register for channel x. - i. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. - ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripheral. This requires programming the SRC_PER and DEST_PER bits, respectively. 4. After the DMAC channel has been programmed, enable the channel by writing a `1' to the DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled. 5. Source and destination request single and burst DMAC transactions to transfer the block of data (assuming non-memory peripherals). The DMAC acknowledges at the completion of every transaction (burst and single) in the block and carries out the block transfer. 6. When the block transfer has completed, the DMAC reloads the DMAC_SARx register. The DMAC_DARx register remains unchanged. Hardware sets the block complete interrupt. The DMAC then samples the row number as shown in Table 24-2 on page 267. If the DMAC is in Row 1, then the DMA transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable (DMAC_ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed.
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7. The DMA transfer proceeds as follows: a. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete interrupt is un-masked (DMAC_MaskBlock[x] = 1'b1, where x is the channel number) hardware sets the block complete interrupt when the block transfer has completed. It then stalls until the block complete interrupt is cleared by software. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt service routine) should clear the source reload bit, DMAC_CFGx.RELOAD_SR. This puts the DMAC into Row1 as shown in Table 24-2 on page 267. If the next block is not the last block in the DMA transfer then the source reload bit should remain enabled to keep the DMAC in Row3 as shown in Table 24-2 on page 267. b. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt is masked (DMAC_MaskBlock[x] = 1'b0, where x is the channel number) then hardware does not stall until it detects a write to the block complete interrupt clear register but starts the next block transfer immediately. In this case software must clear the source reload bit, DMAC_CFGx.RELOAD_SR, to put the device into ROW 1 of Table 24-2 on page 267 before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 24-12 on page 283. The DMA Transfer flow is shown in Figure 24-13 on page 284. Figure 24-12. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address
Address of Source Layer Address of Destination Layer
Block2 DAR(2) Block1 DAR(1) Block0 SAR DAR(0)
Source Blocks
Destination Blocks
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Figure 24-13. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address
Channel Enabled by software
Block Transfer
Reload SARx, CTLx
Block Complete interrupt generated here DMAC Transfer Complete interrupt generated here yes
Is DMAC in Row1 of DMAC State Machine Table?
Channel Disabled by hardware
no
CTLx.INT_EN=1 && MASKBLOCK[x]=1?
no
yes Stall until Block Complete interrupt cleared by software
Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the linked list in memory. Write the control information in the LLI. DMAC_CTLx register location of the block descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: a. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control device by programming the TT_FC of the DMAC_CTLx register. b. Set up the transfer characteristics, such as: - i. Transfer width for the source in the SRC_TR_WIDTH field. - ii. Transfer width for the destination in the DST_TR_WIDTH field. - iii. Source master layer in the SMS field where source resides. - iv. Destination master layer in the DMS field where destination resides.
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- v. Incrementing/decrementing or fixed address for source in SINC field. - vi. Incrementing/decrementing or fixed address for destination DINC field. 3. Write the starting destination address in the DMAC_DARx register for channel x.
Note: The values in the LLI.DMAC_DARx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used.
4. Write the channel configuration information into the DMAC_CFGx register for channel x. a. Designate the handshaking interface type (hardware or software) for the source and destination peripherals. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a `0' activates the hardware handshaking interface to handle source/destination requests for the specific channel. Writing a `1' activates the software handshaking interface to handle source/destination requests. b. If the hardware handshaking interface is activated for the source or destination peripheral, assign handshaking interface to the source and destination peripherals. This requires programming the SRC_PER and DEST_PER bits, respectively.
5. Make sure that all LLI.DMAC_CTLx register locations of the LLI (except the last) are set as shown in Row 8 of Table 24-2 on page 267, while the LLI.DMAC_CTLx register of the last Linked List item must be set as described in Row 1 of Table 24-2. Figure 24-5 on page 266 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_LLPx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_SARx register location of all LLIs in memory point to the start source block address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register locations of all LLIs in memory is cleared. 9. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx register for channel x. 10. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts have been cleared. 12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 8 as shown in Table 24-2 on page 267 13. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a `1' to the DMAC_ChEnReg.CH_EN bit. The transfer is performed. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
Note: The LLI.DMAC_SARx, LLI.DMAC_DARx, LLI.DMAC_LLPx and LLI.DMAC_CTLx registers are fetched. The LLI.DMAC_DARx register location of the LLI although fetched is not used. The DMAC_DARx register in the DMAC remains unchanged.
16. Source and destination requests single and burst DMAC transactions to transfer the block of data (assuming non-memory peripherals). The DMAC acknowledges at the
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completion of every transaction (burst and single) in the block and carry out the block transfer. 17. The DMAC does not wait for the block interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by current DMAC_LLPx register and automatically reprograms the DMAC_SARx, DMAC_CTLx and DMAC_LLPx channel registers. The DMAC_DARx register is left unchanged. The DMA transfer continues until the DMAC samples the DMAC_CTLx and DMAC_LLPx registers at the end of a block transfer match that described in Row 1 of Table 24-2 on page 267. The DMAC then knows that the previous block transferred was the last block in the DMA transfer. The DMAC transfer might look like that shown in Figure 24-14 on page 286 Note that the destination address is decrementing. Figure 24-14. DMA Transfer with Linked List Source Address and Contiguous Destination Address
Address of Source Layer Address of Destination Layer
Block 2 SAR(2) Block 2 DAR(2) Block 1 SAR(1) Block 0 Block 0 SAR(0)
Source Blocks Destination Blocks
Block 1 DAR(1)
DAR(0)
The DMA transfer flow is shown in Figure 24-15 on page 287.
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Figure 24-15. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address
Channel Enabled by software
LLI Fetch
Hardware reprograms SARx, CTLx, LLPx
DMAC block transfer
Source/destination status fetch Block Complete interrupt generated here Is DMAC in Row 1 of Table 4 ? no
DMAC Transfer Complete interrupt generated here
yes Channel Disabled by hardware
24.3.6
Disabling a Channel Prior to Transfer Completion Under normal operation, software enables a channel by writing a `1' to the Channel Enable Register, DMAC_ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the DMAC_ChEnReg.CH_EN register bit. The recommended way for software to disable a channel without losing data is to use the CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register (DMAC_CFGx) register. 1. If software wishes to disable a channel prior to the DMA transfer completion, then it can set the DMAC_CFGx.CH_SUSP bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. Software can now poll the DMAC_CFGx.FIFO_EMPTY bit until it indicates that the channel FIFO is empty.
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3. The DMAC_ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is empty. When DMAC_CTLx.SRC_TR_WIDTH is less than DMAC_CTLx.DST_TR_WIDTH and the DMAC_CFGx.CH_SUSP bit is high, the DMAC_CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do not permit a single word of DMAC_CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_TR_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a `0' to the DMAC_CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement.
24.3.6.1
Abnormal Transfer Termination A DMAC DMA transfer may be terminated abruptly by software by clearing the channel enable bit, DMAC_ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the DMAC_ChEnReg.CH_EN bit is cleared over the AHB slave interface. Consider this as a request to disable the channel. The DMAC_ChEnReg.CH_EN must be polled and then it must be confirmed that the channel is disabled by reading back 0. A case where the channel is not be disabled after a channel disable request is where either the source or destination has received a split or retry response. The DMAC must keep re-attempting the transfer to the system HADDR that originally received the split or retry response until an OKAY response is returned. To do otherwise is an AMBA protocol violation. Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register (DMAC_DmaCfgReg[0]). Again, this does not mean that all channels are disabled immediately after the DMAC_DmaCfgReg[0] is cleared over the AHB slave interface. Consider this as a request to disable all channels. The DMAC_ChEnReg must be polled and then it must be confirmed that all channels are disabled by reading back `0'.
Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals such as a source FIFO this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an acknowledgement.
Note:
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24.4 DMA Controller (DMAC) User Interface
DMA Controller (DMAC) User Interface
Register Channel 0 Source Address Register Reserved Channel 0 Destination Address Register Reserved Channel 0 Linked List Pointer Register Reserved Channel 0 Control Register Low Channel 0 Control Register High Reserved Channel 0 Configuration Register Low Channel 0 Configuration Register High Channel 0 Source Gather Register Reserved Channel 0 Destination Scatter Register Reserved Channel 1 Source Address Register Reserved Channel 1 Destination Address Register Reserved Channel 1 Linked List Pointer Register Reserved Channel 1 Control Register Low Channel 1 Control Register High Reserved Channel 1 Configuration Register Low Channel 1 Configuration Register High Channel 1 Source Gather Register Reserved Channel 1 Destination Scatter Register Reserved Raw Status for IntTfr Interrupt Reserved Raw Status for IntBlock Interrupt Reserved Raw Status for IntSrcTran Interrupt DMAC_RawSrcTran Read 0x0 DMAC_RawBlock Read 0x0 DMAC_RawTfr Read 0x0 DMAC_DSR1 Read/Write 0x0 DMAC_CFG1L DMAC_CFG1H DMAC_SGR1 Read/Write Read/Write Read/Write 0x00000c20 0x00000004 0x0 DMAC_CTL1L DMAC_CTL1H Read/Write Read/Write DMAC_LLP1 Read/Write 0x0 DMAC_DAR1 Read/Write 0x0 DMAC_SAR1 Read/Write 0x0 DMAC_DSR0 Read/Write 0x0 DMAC_CFG0L DMAC_CFG0H DMAC_SGR0 Read/Write Read/Write Read/Write 0x00000c00 0x00000004 0x0 DMAC_CTL0L DMAC_CTL0H Read/Write Read/Write DMAC_LLP0 Read/Write DMAC_DAR0 Read/Write Register Name DMAC_SAR0 Access Read/Write Reset Value 0x0 0x0 0x0 -
Table 24-3.
Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 - 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x7C 0x70 0x74 0x78 - 0x94 0x98 0x9C 0xa0 0xa4 0xa8 0xac..0x2bc 0x2c0 0x2c4 0x2c8 0x2cc 0x2d0
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Table 24-3.
Offset 0x2d4 0x2d8 0x2dc 0x2e0 0x2e4 0x2e8 0x2ec 0x2f0 0x2f4 0x2f8 0x2fc 0x300 0x304 0x308 0x30c 0x310 0x314 0x318 0x31c 0x320 0x324 0x328 0x32c 0x330 0x334 0x338 0x33c 0x340 0x344 0x348 0x34c 0x350 0x354 0x358 0x35c 0x360
DMA Controller (DMAC) User Interface
Register Reserved Raw Status for IntDstTran Interrupt Reserved Raw Status for IntErr Interrupt Reserved Status for IntTfr Interrupt Reserved Status for IntBlock Interrupt Reserved Status for IntSrcTran Interrupt Reserved Status for IntDstTran Interrupt Reserved Status for IntErr Interrupt Reserved Mask for IntTfr Interrupt Reserved Mask for IntBlock Interrupt Reserved Mask for IntSrcTran Interrupt Reserved Mask for IntDstTran Interrupt Reserved Mask for IntErr Interrupt Reserved Clear for IntTfr Interrupt Reserved Clear for IntBlock Interrupt Reserved Clear for IntSrcTran Interrupt Reserved Clear for IntDstTran Interrupt Reserved Clear for IntErr Interrupt Reserved Status for each interrupt type DMAC_StatusInt Read 0x0 DMAC_ClearErr Write 0x0 DMAC_ClearDstTran Write 0x0 DMAC_ClearSrcTran Write 0x0 DMAC_ClearBlock Write 0x0 DMAC_ClearTfr Write 0x0 DMAC_MaskErr Read/Write 0x0 DMAC_MaskDstTran Read/Write 0x0 DMAC_MaskSrcTran Read/Write 0x0 DMAC_MaskBlock Read/Write 0x0 DMAC_MaskTfr Read/Write 0x0 DMAC_StatusErr Read 0x0 DMAC_StatusDstTran Read 0x0 DMAC_StatusSrcTran Read 0x0 DMAC_StatusBlock Read 0x0 DMAC_StatusTfr Read 0x0 DMAC_RawErr Read 0x0 DMAC_RawDstTran Read 0x0 Register Name Access Reset Value
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Table 24-3.
Offset 0x364 0x368 0x36c 0x370 0x374 0x378 0x37c 0x380 0x384 0x388 0x38c 0x390 0x394 0x398 0x39c 0x3a0 0x3a4 0x3a8 0x3ac 0x3b0 0x3b4 0x3b8 0x3b8
DMA Controller (DMAC) User Interface
Register Reserved Source Software Transaction Request Register Reserved Destination Software Transaction Request Register Reserved Single Source Transaction Request Register Reserved Single Destination Transaction Request Register Reserved Last Source Transaction Request Register Reserved Last Destination Transaction Request Register Reserved DMA Configuration Register Reserved Channel Enable Register Reserved DMA ID Register Reserved DMA Test Register Reserved DMA Version ID Register Reserved Read DMAC_DmaTestReg Read/Write DMAC_IdReg Read 0x203a125a DMAC_ChEnReg Read/Write 0x0 DMAC_DmaCfgReg Read/Write 0x0 DMAC_LstDstReg Read/Write 0x0 DMAC_LstSrcReg Read/Write 0x0 DMAC_SglReqDstReg Read/Write 0x0 DMAC_SglReqSrcReg Read/Write 0x0 DMAC_ReqDstReg Read/Write 0x0 DMAC_ReqSrcReg Read/Write 0x0 Register Name Access Reset Value
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24.4.1
Channel x Source Address Register
Name: DMAC_SARx Access: Read/Write Reset: 0x0
31 23 15 7 30 22 14 6 29 21 13 5 28 SADD 20 SADD 12 SADD 4 SADD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
The address offset for each channel is: [x *0x58] For example, SAR0: 0x000, SAR1: 0x058, etc. * SADD: Source Address of DMA transfer The starting AMBA source address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the source address of the current AMBA transfer. Updated after each source AMBA transfer. The SINC field in the DMAC_CTLx register determines whether the address increments, decrements, or is left unchanged on every source AMBA transfer throughout the block transfer.
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24.4.2 Channel x Destination Address Register Name: DMAC_DARx Access: Read/Write Reset: 0x0
31 23 15 7 30 22 14 6 29 21 13 5 28 DADD 20 DADD 12 DADD 4 DADD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
The address offset for each channel is: 0x08+[x * 0x58] For example, DAR0: 0x008, DAR1: 0x060, etc. * DADD: Destination Address of DMA transfer The starting AMBA destination address is programmed by software before the DMA channel is enabled or by a LLI update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the destination address of the current AMBA transfer. Updated after each destination AMBA transfer. The DINC field in the DMAC_CTLx register determines whether the address increments, decrements or is left unchanged on every destination AMBA transfer throughout the block transfer.
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24.4.3
Linked List Pointer Register for Channel x
Name: DMAC_LLPx Access: Read/Write Reset: 0x0
31 23 15 7 30 22 14 6 29 21 13 5 LOC 28 LOC 20 LOC 12 LOC 4 3 2 1 0 0 0 11 10 9 8 19 18 17 16 27 26 25 24
The address offset for each channel is: 0x10+[x * 0x58] For example, LLP0: 0x010, LLP1: 0x068, etc. * LOC: Address of the next LLI Starting address in memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary. The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if block chaining is enabled. The LLP register has two functions: 1. The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-block). If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type. It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists. 2. The DMAC_LLPx register is also used to point to the address where write back of the control and source/destination status information occurs after block completion.
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24.4.4 Control Register for Channel x Low Name: DMAC_CTLxL Access: Read/Write Reset: 0x0
31 - 23 DMS 15 SRC_MSIZE 7 DINC 30 - 22 14 6 29 - 21 TT_FC 13 5 SRC_TR_WIDTH 28 LLP_S_EN 20 12 DEST_MSIZE 4 27 LLP_D_EN 19 11 3 26 SMS 18 17 D_SCAT_EN S_GATH_EN 10 9 SINC 2 1 DST_TR_WIDTH 25 24 DMS 16 SRC_MSIZE 8 DINC 0 INT_EN
The address offset for each channel is: 0x18+[x * 0x58] For example, CTL0: 0x018, CTL1: 0x070, etc. This register contains fields that control the DMA transfer. The DMAC_CTLxL register is part of the block descriptor (linked list item) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. * INT_EN: Interrupt Enable Bit If set, then all five interrupt generating sources are enabled. * DST_TR_WIDTH: Destination Transfer Width * SRC_TR_WIDTH: Source Transfer Width
SRC_TR_WIDTH/DST_TR_WIDTH 000 001 010 Other Size (bits) 8 16 32 Reserved
* DINC: Destination Address Increment Indicates whether to increment or decrement the destination address on every destination AMBA transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, then set this field to "No change". 00 = Increment 01 = Decrement 1x = No change * SINC: Source Address Increment Indicates whether to increment or decrement the source address on every source AMBA transfer. If your device is fetching data from a source peripheral FIFO with a fixed address, then set this field to "No change". 00 = Increment 01 = Decrement 1x = No change * DEST_MSIZE: Destination Burst Transaction Length Number of data items, each of width DMAC_CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. * SRC_MSIZE: Source Burst Transaction Length
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Number of data items, each of width DMAC_CTLx.SRC_TR_WIDTH, to be read from the source every time a source burst transaction request is made from either the corresponding hardware or software handshaking interface. * S_GATH_EN: Source Gather Enable Bit 0 = Gather is disabled. 1 = Gather is enabled. Gather on the source side is only applicable when the DMAC_CTLx.SINC bit indicates an incrementing or decrementing address control. * D_SCAT_EN: Destination Scatter Enable Bit 0 = Scatter is disabled. 1 = Scatter is enabled. Scatter on the destination side is only applicable when the DMAC_CTLx.DINC bit indicates an incrementing or decrementing address control. * TT_FC: Transfer Type and Flow Control The following transfer types are supported. * Memory to Memory * Memory to Peripheral * Peripheral to Memory Flow Control can be assigned to the DMAC, the source peripheral, or the destination peripheral.
TT_FC 000 001 010 011 100 101 110 111 Transfer Type Memory to Memory Memory to Peripheral Peripheral to Memory Peripheral to Peripheral Peripheral to Memory Peripheral to Peripheral Memory to Peripheral Peripheral to Peripheral Flow Controller DMAC DMAC DMAC DMAC Peripheral Source Peripheral Peripheral Destination Peripheral
* DMS: Destination Master Select Identifies the Master Interface layer where the destination device (peripheral or memory) resides. 00 = AHB master 1 01 = Reserved 10 = Reserved 11 = Reserved * SMS: Source Master Select Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from. 00 = AHB master 1 01 = Reserved 10 = Reserved 11 = Reserved * LLP_D_EN Block chaining is only enabled on the destination side if the LLP_D_EN field is high and DMAC_LLPx.LOC is non-zero.
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* LLP_S_EN Block chaining is only enabled on the source side if the LLP_S_EN field is high and DMAC_LLPx.LOC is non-zero.
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24.4.5
Control Register for Channel x High
Name: DMAC_CTLxH Access: Read/Write Reset: 0x0
31 - 23 15 - 7 - 30 - 22 14 - 6 - 29 - 21 13 - 5 - 28 - 20 12 DONE 4 27 - 19 11 - 3 26 - 18 10 - 2 BLOCK_TS 25 - 17 9 - 1 24 - 16 8 - 0
* BLOCK_TS: Block Transfer Size When the DMAC is flow controller, this field is written by the user before the channel is enabled to indicate the block size. The number programmed into BLOCK_TS indicates the total number of single transactions to perform for every block transfer. The width of the single transaction is determined by DMAC_CTLx.SRC_TR_WIDTH. * DONE: Done Bit Software can poll the LLI DMAC_CTLx.DONE bit to see when a block transfer is complete. The LLI DMAC_CTLx.DONE bit should be cleared when the linked lists are setup in memory prior to enabling the channel.
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24.4.6 Configuration Register for Channel x Low Name: DMAC_CFGxL Access: Read/Write Reset: 0x0
31 RELOAD_DS 23 30 29 28 RELOAD_SR 22 21 20 MAX_ABRST 15 14 13 12 LOCK_B_L LOCK_CH_L 7 6 5 4 CH_PRIOR - 27 MAX_ABRST 19 SR_HS_POL 11 HS_SEL_SR 3 - 18 DS_HS_POL 10 HS_SEL_DS 2 - 17 LOCK_B 9 FIFO_EMPT 1 - 16 LOCK_CH 8 CH_SUSP 0 - 26 25 24
The address offset for each channel is: 0x40+[x * 0x58] For example, CFG0: 0x040, CFG1: 0x098, etc. * CH_PRIOR: Channel priority A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x - 1] A programmed value outside this range causes erroneous behavior. * CH_SUSP: Channel Suspend Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. Can also be used in conjunction with DMAC_CFGx.FIFO_EMPTY to cleanly disable a channel without losing any data. 0 = Not Suspended. 1 = Suspend. Suspend DMA transfer from the source. * FIFO_EMPTY Indicates if there is data left in the channel's FIFO. Can be used in conjunction with DMAC_CFGx.CH_SUSP to cleanly disable a channel. 1 = Channel's FIFO empty 0 = Channel's FIFO not empty * HS_SEL_DST: Destination Software or Hardware Handshaking Select This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware Initiated transaction requests are ignored. If the destination peripheral is memory, then this bit is ignored. * HS_SEL_SRC: Source Software or Hardware Handshaking Select This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this channel. 0 = Hardware handshaking interface. Software-initiated transaction requests are ignored. 1 = Software handshaking interface. Hardware-initiated transaction requests are ignored. If the source peripheral is memory, then this bit is ignored. * LOCK_CH_L: Channel Lock Level Indicates the duration over which DMAC_CFGx.LOCK_CH bit applies. 00 = Over complete DMA transfer 01 = Over complete DMA block transfer
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1x = Over complete DMA transaction * LOCK_B_L: Bus Lock Level Indicates the duration over which DMAC_CFGx.LOCK_B bit applies. 00 = Over complete DMA transfer 01 = Over complete DMA block transfer 1x = Over complete DMA transaction * LOCK_CH: Channel Lock Bit When the channel is granted control of the master bus interface and if the DMAC_CFGx.LOCK_CH bit is asserted, then no other channels are granted control of the master bus interface for the duration specified in DMAC_CFGx.LOCK_CH_L. Indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the duration specified in DMAC_CFGx.LOCK_CH_L. * LOCK_B: Bus Lock Bit When active, the AMBA bus master signal hlock is asserted for the duration specified in DMAC_CFGx.LOCK_B_L. * DS_HS_POL: Destination Handshaking Interface Polarity 0 = Active high 1 = Active low * SR_HS_POL: Source Handshaking Interface Polarity 0 = Active high 1 = Active low * MAX_ABRST: Maximum AMBA Burst Length Maximum AMBA burst length that is used for DMA transfers on this channel. A value of `0' indicates that software is not limiting the maximum AMBA burst length for DMA transfers on this channel. * RELOAD_SR: Automatic Source Reload The DMAC_SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. * RELOAD_DS: Automatic Destination Reload The DMAC_DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated.
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24.4.7 Configuration Register for Channel x High Name: DMAC_CFGxH Access: Read/Write Reset: 0x0
31 - 23 - 15 - 7 SRC_PER 30 - 22 - 14 6 - 29 - 21 - 13 DEST_PER 5 - 4 3 PROTCTL 2 28 - 20 - 12 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 SRC_PER 1 FIFO_MODE 24 - 16 - 8 0 FCMODE
* FCMODE: Flow Control Mode Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller. 0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled. 1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of data transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled. * FIFO_MODE: R/W 0x0 FIFO Mode Select Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. 0 = Space/data available for single AMBA transfer of the specified transfer width. 1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer. * PROTCTL: Protection Control bits used to drive the AMBA HPROT[3:1] bus. The AMBA Specification recommends that the default value of HPROT indicates a non-cached, nonbuffered, privileged data access. The reset value is used to indicate such an access. * HPROT[0] is tied high as all transfers are data accesses as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. SRC_PER: Source Hardware Handshaking Interface Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the DMAC_CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface via the assigned hardware handshaking interface. For correct DMAC operation, only one peripheral (source or destination) should be assigned to the same handshaking interface. * DEST_PER: Destination Hardware Handshaking Interface Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the DMAC_CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channel can then communicate with the destination peripheral connected to that interface via the assigned hardware handshaking interface. For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
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24.4.8
Source Gather Register for Channel x
Name: DMAC_SGRx Access: Read/Write Reset: 0x0
31 - 23 15 7 30 - 22 SGC 14 6 13 5 12 SGI 4 SGI 3 2 1 0 11 10 29 - 21 28 - 20 27 - 19 26 - 18 SGI 9 8 25 - 17 24 - 16
The address offset for each channel is: 0x48+[x * 0x58] For example, SGR0: 0x048, SGR1: 0x0a0, etc. The DMAC_CTLx.SINC field controls whether the address increments or decrements. When the DMAC_CTLx.SINC field indicates a fixed-address control, then the address remains constant throughout the transfer and the DMAC_SGRx register is ignored. * SGI: Source Gather Interval Source gather count field specifies the number of contiguous source transfers of DMAC_CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary. * SGC: Source gather count Source gather interval field (DMAC_SGRx.SGI) - specifies the source address increment/decrement in multiples of DMAC_CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer.
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24.4.9 Destination Scatter Register for Channel x Name: DMAC_DSRx Access: Read/Write Reset: 0x0
31 - 23 15 7 30 - 22 DSC 14 6 13 5 12 DSI 4 DSI 3 2 1 0 11 10 29 - 21 28 - 20 27 - 19 26 - 18 DSI 9 8 25 - 17 24 - 16
The address offset for each channel is: 0x50+[x * 0x58] For example, DSR0: 0x050, DSR1: 0x0a8, etc. The DMAC_CTLx.DINC field controls whether the address increments or decrements. When the DMAC_CTLx.DINC field indicates a fixed address control then the address remains constant throughout the transfer and the DMAC_DSRx register is ignored. * DSI: Destination Scatter Interval Destination scatter interval field (DMAC_DSRx.DSI) - specifies the destination address increment/decrement in multiples of DMAC_CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer. * DSC: Destination Scatter count Destination scatter count field (DMAC_DSRx.DSC) - specifies the number of contiguous destination transfers of DMAC_CTLx.DST_TR_WIDTH between successive scatter boundaries.
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24.4.10
Interrupt Registers
The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each channel, there are five types of interrupt sources: * IntTfr: DMA Transfer Complete Interrupt This interrupt is generated on DMA transfer completion to the destination peripheral. * IntBlock: Block Transfer Complete Interrupt This interrupt is generated on DMA block transfer completion to the destination peripheral. * IntSrcTran: Source Transaction Complete Interrupt This interrupt is generated after completion of the last AMBA transfer of the requested single/burst transaction from the handshaking interface on the source side. If the source for a channel is memory, then that channel never generates a IntSrcTran interrupt and hence the corresponding bit in this field is not set. * IntDstTran: Destination Transaction Complete Interrupt This interrupt is generated after completion of the last AMBA transfer of the requested single/burst transaction from the handshaking interface on the destination side. If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and hence the corresponding bit in this field is not set. * IntErr: Error Interrupt This interrupt is generated when an ERROR response is received from an AHB slave on the HRESP bus during a DMA transfer. In addition, the DMA transfer is cancelled and the channel is disabled.
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24.4.11 Interrupt Raw Status Registers Name: DMAC_RawTfr, DMAC_RawBlock, DMAC_RawSrcTran, DMAC_RawDstTran, DMAC_RawErr Access: Read Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 RAW1 24 - 16 - 8 - 0 RAW0
The address offset are DMAC_RawTfr - 0x2c0 DMAC_RawBlock - 0x2c8 DMAC_RawSrcTran - 0x2d0 DMAC_RawDstTran - 0x2d8 DMAC_RawErr - 0x2e0 * RAW[1:0]: Raw interrupt for each channel Interrupt events are stored in these Raw Interrupt Status Registers before masking: DMAC_RawTfr, DMAC_RawBlock, DMAC_RawSrcTran, DMAC_RawDstTran, DMAC_RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, DMAC_RawTfr[2] is Channel 2's raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in the DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr registers.
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24.4.12
Interrupt Status Registers
Name: DMAC_StatusTfr, DMAC_StatusBlock, DMAC_StatusSrcTran, DMAC_StatusDstTran, DMAC_StatusErr Access: Read Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 STATUS1 24 - 16 - 8 - 0 STATUS0
The address offset are DMAC_StatusTfr: 0x2e8 DMAC_StatusBlock: 0x2f0 DMAC_StatusSrcTran: 0x2f8 DMAC_StatusDstTran: 0x300 DMAC_StatusErr: 0x308 * STATUS[1:0] All interrupt events from all channels are stored in these Interrupt Status Registers after masking: DMAC_StatusTfr, DMAC_StatusBlock, DMAC_StatusSrcTran, DMAC_StatusDstTran, DMAC_StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, DMAC_StatusTfr[2] is Channel 2's status transfer complete interrupt.The contents of these registers are used to generate the interrupt signals leaving the DMAC.
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24.4.13 Interrupt Status Registers Name: DMAC_MaskTfr, DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr Access: Read/Write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 INT_M_WE1 1 INT_MASK1 24 - 16 - 8 INT_M_WE0 0 INT_MASK0
The address offset are DMAC_MaskTfr: 0x310 DMAC_MaskBlock: 0x318 DMAC_MaskSrcTran: 0x320 DMAC_MaskDstTran: 0x328 DMAC_MaskErr: 0x330 The contents of the Raw Status Registers are masked with the contents of the Mask Registers: DMAC_MaskTfr, DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, DMAC_MaskTfr[2] is the mask bit for Channel 2's transfer complete interrupt. A channel's INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AMBA write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the DMAC_MaskTfr register writes a 1 into DMAC_MaskTfr[0], while DMAC_MaskTfr[7:1] remains unchanged. Writing hex 00xx leaves DMAC_MaskTfr[7:0] unchanged. Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMAC to set the appropriate bit in the Status Registers. * INT_MASK[1:0]: Interrupt Mask 0 = Masked 1 = Unmasked * INT_M_WE[9:8]: Interrupt Mask Write Enable 0 = Write disabled 1 = Write enabled
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24.4.14
Interrupt Clear Registers
Name: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran,DMAC_ClearErr Access: Write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 CLEAR1 24 - 16 - 8 - 0 CLEAR0
The address offset are DMAC_ClearTfr: 0x338 DMAC_ClearBlock: 0x340 DMAC_ClearSrcTran: 0x348 DMAC_ClearDstTran: 0x350 DMAC_ClearErr: 0x358 * CLEAR[1:0]: Interrupt Clear 0 = No effect 1 = Clear interrupt Each bit in the Raw Status and Status registers is cleared on the same cycle by writing a 1 to the corresponding location in the Clear registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran, DMAC_ClearErr. Each Interrupt Clear register has a bit allocated per channel, for example, DMAC_ClearTfr[2] is the clear bit for Channel 2's transfer complete interrupt. Writing a 0 has no effect. These registers are not readable.
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24.4.15 Combined Interrupt Status Registers Name: DMAC_StatusInt Access: Read Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 ERR 27 - 19 - 11 - 3 DSTT 26 - 18 - 10 - 2 SRCT 25 - 17 - 9 - 1 BLOCK 24 - 16 - 8 - 0 TFR
The contents of each of the five Status Registers (DMAC_StatusTfr, DMAC_StatusBlock, DMAC_StatusSrcTran, DMAC_StatusDstTran, DMAC_StatusErr) is OR'd to produce a single bit per interrupt type in the Combined Status Register (DMAC_StatusInt). * TFR OR of the contents of DMAC_StatusTfr Register. * BLOCK OR of the contents of DMAC_StatusBlock Register. * SRCT OR of the contents of DMAC_StatusSrcTran Register. * DSTT OR of the contents of DMAC_StatusDstTran Register. * ERR OR of the contents of DMAC_StatusErr Register.
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24.4.16
Source Software Transaction Request Register
Name: DMAC_ReqSrcReg Access: Read/write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 REQ_WE1 1 SRC_REQ1 24 - 16 - 8 REQ_WE0 0 SRC_REQ0
A bit is assigned for each channel in this register. DMAC_ReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same AMBA write transfer. For example, writing 0x101 writes a 1 into DMAC_ReqSrcReg[0], while DMAC_ReqSrcReg[2:1] remains unchanged. Writing hex 0x0yy leaves DMAC_ReqSrcReg[2:0] unchanged. This allows software to set a bit in the DMAC_ReqSrcReg register without performing a read-modified write * SRC_REQ[1:0]: Source request * REQ_WE[9:8]: Request write enable 0 = Write disabled 1 = Write enabled
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24.4.17 Destination Software Transaction Request Register Name: DMAC_ReqDstReg Access: Read/write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 REQ_WE1 1 DST_REQ1 24 - 16 - 8 REQ_WE0 0 DST_REQ0
A bit is assigned for each channel in this register. DMAC_ReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel DST_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same AMBA write transfer. * DST_REQ[1:0]: Destination request * REQ_WE[9:8]: Request write enable 0 = Write disabled 1 = Write enabled
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24.4.18
Single Source Transaction Request Register
Name: DMAC_SglReqSrcReg Access: Read/write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 REQ_WE1 1 S_SG_REQ1 24 - 16 - 8 REQ_WE0 0 S_SG_REQ0
A bit is assigned for each channel in this register. DMAC_SglReqSrcReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel S_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same AMBA write transfer. * S_SG_REQ[1:0]: Source single request * REQ_WE[9:8]: Request write enable 0 = Write disabled 1 = Write enabled
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24.4.19 Single Destination Transaction Request Register Name: DMAC_SglReqDstReg Access: Read/write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 REQ_WE1 1 D_SG_REQ1 24 - 16 - 8 REQ_WE0 0 D_SG_REQ0
A bit is assigned for each channel in this register. DMAC_SglReqDstReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on the same AMBA write transfer. * D_SG_REQ[1:0]: Destination single request * REQ_WE[9:8]: Request write enable 0 = Write disabled 1 = Write enabled
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24.4.20
Last Source Transaction Request Register
Name: DMAC_LstSrcReqReg Access: Read/write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 LSTSR_WE1 1 LSTSRC1 24 - 16 - 8 LSTSR_WE0 0 LSTSRC0
A bit is assigned for each channel in this register. LstSrcReqReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSR_WE field is asserted on the same AMBA write transfer. * LSTSRC[1:0]: Source Last Transaction request * LSTSR_WE[9:8]: Source Last Transaction request write enable 0 = Write disabled 1 = Write enabled
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24.4.21 Last Destination Transaction Request Register Name: DMAC_LstDstReqReg Access: Read/write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 LSTDS_WE1 1 LSTDST1 24 - 16 - 8 LSTDS_WE0 0 LSTDST0
A bit is assigned for each channel in this register. LstDstReqReg[n] is ignored when software handshaking is not enabled for the source of channel n. A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDS_WE field is asserted on the same AMBA write transfer. * LSTDST[1:0]: Destination Last Transaction request * LSTDS_WE[9:8]: Destination Last Transaction request write enable 0 = Write disabled 1 = Write enabled
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24.4.22
DMAC Configuration Register
Name: DMAC_DmaCfgReg Access: Read/Write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 DMA_EN
* DMA_EN: DMA Controller Enable 0 = DMAC Disabled 1 = DMAC Enabled. This register is used to enable the DMAC, which must be done before any channel activity can begin. If the global channel enable bit is cleared while any channel is still active, then DMAC_DmaCfgReg.DMA_EN still returns `1' to indicate that there are channels still active until hardware has terminated all activity on all channels, at which point the DMAC_DmaCfgReg.DMA_EN bit returns `0'.
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24.4.23 DMAC Channel Enable Register Name: DMAC_ChEnReg Access: Read/Write Reset: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 CH_EN_WE1 1 CH_EN1 24 - 16 - 8 CH_EN_WE0 0 CH_EN0
* CH_EN[1:0] 0 = Disable the Channel 1 = Enable the Channel Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel. The DMAC_ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer has completed. * CH_EN_WE[9:8] The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on the same AMBA write transfer. For example, writing 0x101 writes a 1 into DMAC_ChEnReg[0], while DMAC_ChEnReg[7:1] remains unchanged.
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24.4.24
DMAC ID Register
Name: DMAC_IdReg Access: Read/Write Reset: 0x0
31 23 15 7 30 22 14 6 29 21 13 5 28 ID 20 ID 12 ID 4 ID 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* ID : 0x203a125a
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25. Peripheral DMA Controller (PDC)
25.1 Description
The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The PDC contains twenty channels. The full-duplex peripherals feature eighteen mono-directional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature two bi-directional channels. The user interface of each PDC channel is integrated into the user interface of the peripheral it serves. The user interface of mono directional channels (receive only or transmit only), contains two 32-bit memory pointers and two 16-bit counters, one set (pointer, counter) for current transfer and one set (pointer, counter) for next transfer. The bi-directional channel user interface contains four 32-bit memory pointers and four 16-bit counters. Each set (pointer, counter) is used by current transmit, next transmit, current receive and next receive. Using the PDC removes processor overhead by reducing its intervention during the transfer. This significantly reduces the number of clock cycles required for a data transfer, which improves microcontroller performance. To launch a transfer, the peripheral triggers its associated PDC channels by using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the peripheral itself.
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25.2
Block Diagram
Figure 25-1. Block Diagram
FULL DUPLEX PERIPHERAL THR PDC Channel A PDC
RHR
PDC Channel B
Control
Status & Control
HALF DUPLEX PERIPHERAL THR PDC Channel C RHR
Control
Control
Status & Control
RECEIVE or TRANSMIT PERIPHERAL RHR or THR PDC Channel D
Control
Status & Control
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25.3
25.3.1
Functional Description
Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel. The user interface of each PDC channel is integrated into the associated peripheral user interface. The user interface of a serial peripheral, whether it is full or half duplex, contains four 32-bit pointers (RPR, RNPR, TPR, TNPR) and four 16-bit counter registers (RCR, RNCR, TCR, TNCR). However, the transmit and receive parts of each type are programmed differently: the transmit and receive parts of a full duplex peripheral can be programmed at the same time, whereas only one part (transmit or receive) of a half duplex peripheral can be programmed at a time. 32-bit pointers define the access location in memory for current and next transfer, whether it is for read (transmit) or write (receive). 16-bit counters define the size of current and next transfers. It is possible, at any moment, to read the number of transfers left for each channel. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in the peripheral's Transfer Control Register. At the end of a transfer, the PDC channel sends status flags to its associated peripheral. These flags are visible in the peripheral status register (ENDRX, ENDTX, RXBUFF, and TXBUFE). Refer to Section 25.3.3 and to the associated peripheral user interface.
25.3.2
Memory Pointers Each full duplex peripheral is connected to the PDC by a receive channel and a transmit channel. Both channels have 32-bit memory pointers that point respectively to a receive area and to a transmit area in on- and/or off-chip memory. Each half duplex peripheral is connected to the PDC by a bidirectional channel. This channel has two 32-bit memory pointers, one for current transfer and the other for next transfer. These pointers point to transmit or receive data depending on the operating mode of the peripheral. Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented respectively by 1, 2 or 4 bytes. If a memory pointer address changes in the middle of a transfer, the PDC channel continues operating using the new address.
25.3.3
Transfer Counters Each channel has two 16-bit counters, one for current transfer and the other one for next transfer. These counters define the size of data to be transferred by the channel. The current transfer counter is decremented first as the data addressed by current memory pointer starts to be transferred. When the current transfer counter reaches zero, the channel checks its next transfer counter. If the value of next counter is zero, the channel stops transferring data and sets the appropriate flag. But if the next counter value is greater then zero, the values of the next pointer/next counter are copied into the current pointer/current counter and the channel resumes the transfer whereas next pointer/next counter get zero/zero as values. At the end of this transfer the PDC channel sets the appropriate flags in the Peripheral Status Register.
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The following list gives an overview of how status register flags behave depending on the counters' values: * ENDRX flag is set when the PERIPH_RCR register reaches zero. * RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. * ENDTX flag is set when the PERIPH_TCR register reaches zero. * TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the Peripheral Status Register. 25.3.4 Data Transfers The serial peripheral triggers its associated PDC channels' transfers using transmit enable (TXEN) and receive enable (RXEN) flags in the transfer control register integrated in the peripheral's user interface. When the peripheral receives an external data, it sends a Receive Ready signal to its PDC receive channel which then requests access to the Matrix. When access is granted, the PDC receive channel starts reading the peripheral Receive Holding Register (RHR). The read data are stored in an internal buffer and then written to memory. When the peripheral is about to send data, it sends a Transmit Ready to its PDC transmit channel which then requests access to the Matrix. When access is granted, the PDC transmit channel reads data from memory and puts them to Transmit Holding Register (THR) of its associated peripheral. The same peripheral sends data according to its mechanism. 25.3.5 PDC Flags and Peripheral Status Register Each peripheral connected to the PDC sends out receive ready and transmit ready flags and the PDC sends back flags to the peripheral. All these flags are only visible in the Peripheral Status Register. Depending on the type of peripheral, half or full duplex, the flags belong to either one single channel or two different channels. 25.3.5.1 Receive Transfer End This flag is set when PERIPH_RCR register reaches zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_RCR or PERIPH_RNCR. 25.3.5.2 Transmit Transfer End This flag is set when PERIPH_TCR register reaches zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. 25.3.5.3 Receive Buffer Full This flag is set when PERIPH_RCR register reaches zero with PERIPH_RNCR also set to zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
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25.3.5.4 Transmit Buffer Empty This flag is set when PERIPH_TCR register reaches zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
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25.4
Peripheral DMA Controller (PDC) User Interface
Memory Map
Register Receive Pointer Register Receive Counter Register Transmit Pointer Register Transmit Counter Register Receive Next Pointer Register Receive Next Counter Register Transmit Next Pointer Register Transmit Next Counter Register Transfer Control Register Transfer Status Register Name PERIPH _RPR PERIPH_RCR PERIPH_TPR PERIPH_TCR PERIPH_RNPR PERIPH_RNCR PERIPH_TNPR PERIPH_TNCR PERIPH_PTCR PERIPH_PTSR
(1)
Table 25-1.
Offset 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 Note:
Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write Read
Reset State 0 0 0 0 0 0 0 0 0 0
1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI, etc.)
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25.4.1 Receive Pointer Register PERIPH_RPR Read/Write
30 29 28 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
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25.4.2
Receive Counter Register PERIPH_RCR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RXCTR 7 6 5 4 RXCTR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the receiver 1 - 65535 = Starts peripheral data transfer if corresponding channel is active
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25.4.3 Transmit Pointer Register PERIPH_TPR Read/Write
30 29 28 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR.
25.4.4
Transmit Counter Register PERIPH_TCR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TXCTR 7 6 5 4 TXCTR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR. 0 = Stops peripheral data transfer to the transmitter 1- 65535 = Starts peripheral data transfer if corresponding channel is active
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25.4.5
Receive Next Pointer Register PERIPH_RNPR Read/Write
30 29 28 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
25.4.6
Receive Next Counter Register PERIPH_RNCR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RXNCTR 7 6 5 4 RXNCTR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
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25.4.7 Transmit Next Pointer Register PERIPH_TNPR Read/Write
30 29 28 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR.
25.4.8
Transmit Next Counter Register PERIPH_TNCR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TXNCTR 7 6 5 4 TXNCTR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR.
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25.4.9
Transfer Control Register PERIPH_PTCR Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 TXTDIS 1 RXTDIS 24 - 16 - 8 TXTEN 0 RXTEN
Register Name: Access Type:
31 - 23 - 15 - 7 -
* RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables PDC receiver channel requests if RXTDIS is not set. When a half duplex peripheral is connected to the PDC, enabling the receiver channel requests automatically disables the transmitter channel requests. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral. * RXTDIS: Receiver Transfer Disable 0 = No effect. 1 = Disables the PDC receiver channel requests. When a half duplex peripheral is connected to the PDC, disabling the receiver channel requests also disables the transmitter channel requests. * TXTEN: Transmitter Transfer Enable 0 = No effect. 1 = Enables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, it enables the transmitter channel requests only if RXTEN is not set. It is forbidden to set both TXTEN and RXTEN for a half duplex peripheral. * TXTDIS: Transmitter Transfer Disable 0 = No effect. 1 = Disables the PDC transmitter channel requests. When a half duplex peripheral is connected to the PDC, disabling the transmitter channel requests disables the receiver channel requests.
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25.4.10 Transfer Status Register PERIPH_PTSR Read
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 TXTEN 0 RXTEN
Register Name: Access Type:
31 - 23 - 15 - 7 -
* RXTEN: Receiver Transfer Enable 0 = PDC Receiver channel requests are disabled. 1 = PDC Receiver channel requests are enabled. * TXTEN: Transmitter Transfer Enable 0 = PDC Transmitter channel requests are disabled. 1 = PDC Transmitter channel requests are enabled.
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26. Clock Generator
26.1 Description
The Clock Generator is made up of 2 PLLs, a Main Oscillator, and a 32.768 kHz low-power Oscillator. It provides the following clocks: * SLCK, the Slow Clock, which is the only permanent clock within the system * MAINCK is the output of the Main Oscillator The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 27.9. However, the Clock Generator registers are named CKGR_. * PLLACK is the output of the Divider and PLL A block * PLLBCK is the output of the Divider and PLL B block
26.2
Slow Clock Crystal Oscillator
The Clock Generator integrates a 32.768 kHz low-power oscillator. The XIN32 and XOUT32 pins must be connected to a 32.768 kHz crystal. Two external capacitors must be wired as shown in Figure 26-1.
Figure 26-1. Typical Slow Clock Crystal Oscillator Connection
XIN32
32,768 Hz Crystal
XOUT32
GNDPLL
CL1
CL2
26.3
Main Oscillator
Figure 26-2 shows the Main Oscillator block diagram.
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Figure 26-2. Main Oscillator Block Diagram
MOSCEN
XIN XOUT
Main Oscillator
MAINCK Main Clock
OSCOUNT
SLCK Slow Clock
Main Oscillator Counter Main Clock Frequency Counter
MOSCS
MAINF MAINRDY
26.3.1
Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 26-3. The 1 k resistor is only required for crystals with frequencies lower than 8 MHz. For further details on the electrical characteristics of the Main Oscillator, see the section "DC Characteristics" of the product datasheet.
Figure 26-3. Typical Crystal Connection
XIN XOUT GND
1K
CL1
CL2
26.3.2
Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and decreases when the frequency rises. Main Oscillator Control To minimize the power required to start up the system, the main oscillator is disabled after reset and slow clock is selected. The software enables or disables the main oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared, indicating the main clock is off.
26.3.3
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When enabling the main oscillator, the user must initiate the main oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the main oscillator, the MOSCS bit in PMC_SR (Status Register) is cleared and the counter starts counting down on the slow clock divided by 8 from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the main clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor. 26.3.4 Main Clock Frequency Counter The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the MAINRDY bit in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 26.3.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.
26.4
Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 26-4 shows the block diagram of the divider and PLL blocks.
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Figure 26-4. Divider and PLL Blocks Block Diagram
DIVB MULB OUTB
MAINCK
Divider B
PLL B
PLLBCK
PLLRCB
DIVA
MULA
OUTA PLLACK
Divider A
PLL A
PLLRCA
PLLBCOUNT PLL B Counter
LOCKB
PLLACOUNT SLCK PLL A Counter
LOCKA
26.4.1
PLL Filter The PLL requires connection to an external second-order filter through the pin, either PPLRCA or PLLRCB. Figure 26-5 shows a schematic of these filters.
Figure 26-5. PLL Capacitors and Resistors
PLLRC PLL
R
C2 C1 GND
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. 26.4.2 Divider and Phase Lock Loop Programming The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus the corresponding PLL input clock is set to 0.
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The PLL allows multiplication of the divider's outputs. The PLL clock signal has a frequency that depends on the respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field. Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or LOCKB) in PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT or PLLBCOUNT) in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel.
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27. Power Management Controller (PMC)
27.1 Description
The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the ARM Processor. The Power Management Controller provides the following clocks: * MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller. * Processor Clock (PCK), switched off when entering processor in idle mode. * Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. * UHP Clock (UHPCK), required by USB Host Port operations. * Programmable Clock Outputs can be selected from the clocks provided by the clock generator and driven on the PCKx pins.
27.2
Master Clock Controller
The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock provides a Slow Clock signal to the whole device. Selecting the Main Clock saves power consumption of the PLLs. The Master Clock Controller is made up of a clock selector and a prescaler. It also contains a Master Clock divider which allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. The Master Clock divider can be programmed through the MDIV field in PMC_MCKR. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a highspeed clock to a lower one to inform the software when the change is actually done.
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Figure 27-1. Master Clock Controller
PMC_MCKR CSS SLCK MAINCK PLLACK PLLBCK To the Processor Clock Controller (PCK) Master Clock Prescaler Master Clock Divider MCK PMC_MCKR PRES PMC_MCKR MDIV
27.3
Processor Clock Controller
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock, which is automatically re-enabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus.
27.4
USB Clock Controller
The USB Source Clock is always generated from the PLL B output. If using the USB, the user must program the PLL to generate a 48 MHz, a 96 MHz or a 192 MHz signal with an accuracy of 0.25% depending on the USBDIV bit in CKGR_PLLBR (see Figure 27-2). When the PLL B output is stable, i.e., the LOCKB is set: * The USB host clock can be enabled by setting the UHP bit in PMC_SCER. To save power on this peripheral when it is not used, the user can set the UHP bit in PMC_SCDR. The UHP bit in PMC_SCSR gives the activity of this clock. The USB host port require both the 12/48 MHz signal and the Master Clock. The Master Clock may be controlled via the Peripheral Clock Controller.
Figure 27-2. USB Clock Controller
USBDIV USB Source Clock UDP Clock (UDPCK)
Divider /1,/2,/4
UDP
UHP Clock (UHPCK)
UHP
27.5
Peripheral Clock Controller
The Power Management Controller controls the clocks of each embedded peripheral by the way of the Peripheral Clock Controller. The user can individually enable and disable the Mas-
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ter Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral.
27.6
Programmable Clock Output Controller
The PMC controls 4 signals to be output on external pins PCKx. Each signal can be independently programmed via the PMC_PCKx registers. PCKx can be independently selected between the Slow clock, the PLL A output, the PLL B output and the main clock by writing the CSS field in PMC_PCKx. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the PRES (Prescaler) field in PMC_PCKx. Each output signal can be enabled and disabled by writing 1 in the corresponding bit, PCKx of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the PCKx bits of PMC_SCSR (System Clock Status Register). Moreover, like the PCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed.
27.7
Programming Sequence
1. Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR register. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR register. Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR register to be set. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to MOSCS has been enabled in the PMC_IER register.
Code Example:
write_register(CKGR_MOR,0x00000701)
Start Up Time = 8 * OSCOUNT / SLCK = 56 Slow Clock Cycles. Thus the main oscillator is enabled (MOSCS bit set) after 56 Slow Clock Cycles.
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2. Checking the Main Oscillator Frequency (Optional): In some situations the user may need an accurate measure of the main oscillator frequency. This measure can be accomplished via the CKGR_MCFR register. Once the MAINRDY field is set in CKGR_MCFR register, the user may read the MAINF field in CKGR_MCFR register. This provides the number of main clock cycles within sixteen slow clock cycles. 3. Setting PLL A and divider A: All parameters necessary to configure PLL A and divider A are located in the CKGR_PLLAR register. It is important to note that Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. The DIVA field is used to control the divider A itself. The user can program a value between 0 and 255. Divider A output is divider A input divided by DIVA. By default, DIVA parameter is set to 0 which means that divider A is turned off. The OUTA field is used to select the PLL A output frequency range. The MULA field is the PLL A multiplier factor. This parameter can be programmed between 0 and 2047. If MULA is set to 0, PLL A is turned off. Otherwise PLL A output frequency is PLL A input frequency multiplied by (MULA + 1). The PLLACOUNT field specifies the number of slow clock cycles before LOCKA bit is set in the PMC_SR register after CKGR_PLLAR register has been written. Once CKGR_PLLAR register has been written, the user is obliged to wait for the LOCKA bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKA has been enabled in the PMC_IER register. All parameters in CKGR_PLLAR can be programmed in a single write operation. If at some stage one of the following parameters, SRCA, MULA, DIVA is modified, LOCKA bit goes low to indicate that PLL A is not ready yet. When PLL A is locked, LOCKA is set again. User has to wait for LOCKA bit to be set before using the PLL A output clock. Code Example:
write_register(CKGR_PLLAR,0x20030605)
PLL A and divider A are enabled. PLL A input clock is main clock divided by 5. PLL An output clock is PLL A input clock multiplied by 4. Once CKGR_PLLAR has been written, LOCKA bit is set after six slow clock cycles.
4. Setting PLL B and divider B: All parameters needed to configure PLL B and divider B are located in the CKGR_PLLBR register. The DIVB field is used to control divider B itself. A value between 0 and 255 can be programmed. Divider B output is divider B input divided by DIVB parameter. By default DIVB parameter is set to 0 which means that divider B is turned off. The OUTB field is used to select the PLL B output frequency range.
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The MULB field is the PLL B multiplier factor. This parameter can be programmed between 0 and 2047. If MULB is set to 0, PLL B is turned off, otherwise the PLL B output frequency is PLL B input frequency multiplied by (MULB + 1). The PLLBCOUNT field specifies the number of slow clock cycles before LOCKB bit is set in the PMC_SR register after CKGR_PLLBR register has been written. Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in the PMC_IER register. All parameters in CKGR_PLLBR can be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is modified, LOCKB bit goes low to indicate that PLL B is not ready yet. When PLL B is locked, LOCKB is set again. The user is constrained to wait for LOCKB bit to be set before using the PLL A output clock. The USBDIV field is used to control the additional divider by 1, 2 or 4, which generates the USB clock(s).
Code Example:
write_register(CKGR_PLLBR,0x00040805)
If PLL B and divider B are enabled, the PLL B input clock is the main clock. PLL B output clock is PLL B input clock multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit is set after eight slow clock cycles.
5. Selection of Master Clock and Processor Clock The Master Clock and the Processor Clock are configurable via the PMC_MCKR register. The CSS field is used to select the Master Clock divider source. By default, the selected clock source is slow clock. The PRES field is used to control the Master Clock prescaler. The user can choose between different values (1, 2, 4, 8, 16, 32, 64). Master Clock output is prescaler input divided by PRES parameter. By default, PRES parameter is set to 1 which means that master clock is equal to slow clock. The MDIV field is used to control the Master Clock prescaler. It is possible to choose between different values (0, 1, 2). The Master Clock output is Processor Clock divided by 1, 2 or 4, depending on the value programmed in MDIV. By default, MDIV is set to 0, which indicates that the Processor Clock is equal to the Master Clock. Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been enabled in the PMC_IER register. The PMC_MCKR register must not be programmed in a single write operation. The preferred programming sequence for the PMC_MCKR register is as follows: * If a new value for CSS field corresponds to PLL Clock, - Program the PRES field in the PMC_MCKR register.
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- Wait for the MCKRDY bit to be set in the PMC_SR register. - Program the CSS field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. * If a new value for CSS field corresponds to Main Clock or Slow Clock, - Program the CSS field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. - Program the PRES field in the PMC_MCKR register. - Wait for the MCKRDY bit to be set in the PMC_SR register. If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit goes low to indicate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be set again before using the Master and Processor Clocks.
Note: IF PLLx clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), the MCKRDY flag goeso low while PLL is unlocked. Once PLL is locked again, LOCK (LOCKA or LOCKB) goes high and MCKRDY is set. While PLLA is unlocked, the Master Clock selection is automatically changed to Slow Clock.. While PLLB is unlocked, the Master Clock selection is automatically changed to Main Clock. For further information, see Section 27.8.2. "Clock Switching Waveforms" on page 346.
Code Example:
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011) wait (MCKRDY=1)
The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 6. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 4 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled. By default all Programmable clocks are disabled. PMC_PCKx registers are used to configure Programmable clocks. The CSS field is used to select the Programmable clock divider source. Four clock options are available: main clock, slow clock, PLLACK, PLLBCK. By default, the clock source selected is slow clock. The PRES field is used to control the Programmable clock prescaler. It is possible to choose between different values (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default, the PRES parameter is set to 1 which means that master clock is equal to slow clock.
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Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write operation. If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the Programmable clock and wait for the PCKRDYx bit to be set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32. 7. Enabling Peripheral Clocks Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via registers PMC_PCER and PMC_PCDR. Depending on the system used, 23 peripheral clocks can be enabled or disabled. The PMC_PCSR provides a clear view as to which peripheral clock is enabled.
Note:
Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.
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27.8
27.8.1
Clock Switching Details
Master Clock Switching Timings Table 27-1 and Table 27-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 27-1. Clock Switching Timings (Worst Case)
Main Clock SLCK PLL Clock
From To Main Clock
- 0.5 x Main Clock + 4.5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLCOUNT x SLCK + 2.5 x PLLx Clock
4 x SLCK + 2.5 x Main Clock - 2.5 x PLL Clock + 5 x SLCK + PLLCOUNT x SLCK
3 x PLL Clock + 4 x SLCK + 1 x Main Clock 3 x PLL Clock + 5 x SLCK 2.5 x PLL Clock + 4 x SLCK + PLLCOUNT x SLCK
SLCK
PLL Clock
Notes:
1. PLL designates either the PLL A or the PLL B Clock. 2. PLLCOUNT designates either PLLACOUNT or PLLBCOUNT.
Table 27-2.
Clock Switching Timings Between Two PLLs (Worst Case)
From PLLA Clock PLLB Clock
To PLLA Clock 2.5 x PLLA Clock + 4 x SLCK + PLLACOUNT x SLCK 3 x PLLB Clock + 4 x SLCK + 1.5 x PLLB Clock 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock 2.5 x PLLB Clock + 4 x SLCK + PLLBCOUNT x SLCK
PLLB Clock
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27.8.2
Clock Switching Waveforms
Figure 27-3. Switch Master Clock from Slow Clock to PLL Clock
Slow Clock
PLL Clock
LOCK
MCKRDY
Master Clock
Write PMC_MCKR
Figure 27-4. Switch Master Clock from Main Clock to Slow Clock
Slow Clock
Main Clock
MCKRDY
Master Clock
Write PMC_MCKR
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Figure 27-5. Change PLLA Programming
Slow Clock
PLLA Clock
LOCK
MCKRDY
Master Clock Slow Clock Write CKGR_PLLAR
Figure 27-6. Change PLLB Programming
Main Clock
PLLB Clock
LOCK
MCKRDY
Master Clock Main Clock Write CKGR_PLLBR
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Figure 27-7. Programmable Clock Output Programming
PLL Clock
PCKRDY
PCKx Output
Write PMC_PCKx
PLL Clock is selected
Write PMC_SCER
PCKx is enabled
Write PMC_SCDR
PCKx is disabled
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27.9 Power Management Controller (PMC) User Interface
Register Mapping
Register System Clock Enable Register System Clock Disable Register System Clock Status Register Reserved Peripheral Clock Enable Register Peripheral Clock Disable Register Peripheral Clock Status Register Reserved Main Oscillator Register Main Clock Frequency Register PLL A Register PLL B Register Master Clock Register Reserved Reserved Programmable Clock 0 Register Programmable Clock 1 Register ... Interrupt Enable Register Interrupt Disable Register Status Register Interrupt Mask Register Reserved Charge Pump Current Register Reserved Name PMC_SCER PMC_SCDR PMC _SCSR - PMC _PCER PMC_PCDR PMC_PCSR - CKGR_MOR CKGR_MCFR CKGR_PLLAR CKGR_PLLBR PMC_MCKR - - PMC_PCK0 PMC_PCK1 ... PMC_IER PMC_IDR PMC_SR PMC_IMR - PMC_PLLICPR - ... Write-only Write-only Read-only Read-only - Write-only - Access Write-only Write-only Read-only - Write-only Write-only Read-only - Read/Write Read-only ReadWrite ReadWrite Read/Write - - Read/Write Read/Write ... --0x08 0x0 - - - Reset Value - - 0x03 - - - 0x0 - 0x0 0x0 0x3F00 0x3F00 0x0 - - 0x0 0x0
Table 27-3.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0038 0x003C 0x0040 0x0044 ... 0x0060 0x0064 0x0068 0x006C
0x0070 - 0x007C 0x0080 0x0084 - 0x00FC
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27.9.1
PMC System Clock Enable Register PMC_SCER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCK3
3
PCK2
2
PCK1
1
PCK0
0
UDP
UHP
-
-
-
-
-
PCK
* PCK: Processor Clock Enable 0 = No effect. 1 = Enables the Processor clock. * UHP: USB Host Port Clock Enable 0 = No effect. 1 = Enables the 12 and 48 MHz clock of the USB Host Port. * UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output.
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27.9.2 PMC System Clock Disable Register PMC_SCDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCK3
3
PCK2
2
PCK1
1
PCK0
0
UDP
UHP
-
-
-
-
-
PCK
* PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor clock. This is used to enter the processor in Idle Mode. * UHP: USB Host Port Clock Disable 0 = No effect. 1 = Disables the 12 and 48 MHz clock of the USB Host Port. * UDP: USB Device Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port. * PCKx: Programmable Clock x Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output.
351
6249B-ATARM-14-Dec-06
27.9.3
PMC System Clock Status Register PMC_SCSR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCK3
3
PCK2
2
PCK1
1
PCK0
0
UDP
UHP
-
-
-
-
-
PCK
* PCK: Processor Clock Status 0 = The Processor clock is disabled. 1 = The Processor clock is enabled. * UHP: USB Host Port Clock Status 0 = The 12 and 48 MHz clock (UHPCK) of the USB Host Port is disabled. 1 = The 12 and 48 MHz clock (UHPCK) of the USB Host Port is enabled. * UDP: USB Device Port Clock Status 0 = The 48 MHz clock (UDPCK) of the USB Device Port is disabled. 1 = The 48 MHz clock (UDPCK) of the USB Device Port is enabled. * PCKx: Programmable Clock x Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled.
352
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6249B-ATARM-14-Dec-06
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27.9.4 PMC Peripheral Clock Enable Register PMC_PCER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
PID31
23
PID30
22
PID29
21
PID28
20
PID27
19
PID26
18
PID25
17
PID24
16
PID23
15
PID22
14
PID21
13
PID20
12
PID19
11
PID18
10
PID17
9
PID16
8
PID15
7
PID14
6
PID13
5
PID12
4
PID11
3
PID10
2
PID9
1
PID8
0
PID7
PID6
PID5
PID4
PID3
PID2
-
-
* PIDx: Peripheral Clock x Enable 0 = No effect. 1 = Enables the corresponding peripheral clock.
Note: Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet. Programming the control bits of the Peripheral ID that are not implemented has no effect on the behavior of the PMC.
27.9.5
PMC Peripheral Clock Disable Register PMC_PCDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
PID31
23
PID30
22
PID29
21
PID28
20
PID27
19
PID26
18
PID25
17
PID24
16
PID23
15
PID22
14
PID21
13
PID20
12
PID19
11
PID18
10
PID17
9
PID16
8
PID15
7
PID14
6
PID13
5
PID12
4
PID11
3
PID10
2
PID9
1
PID8
0
PID7
PID6
PID5
PID4
PID3
PID2
-
-
* PIDx: Peripheral Clock x Disable 0 = No effect. 1 = Disables the corresponding peripheral clock.
Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet.
353
6249B-ATARM-14-Dec-06
27.9.6
PMC Peripheral Clock Status Register PMC_PCSR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
PID31
23
PID30
22
PID29
21
PID28
20
PID27
19
PID26
18
PID25
17
PID24
16
PID23
15
PID22
14
PID21
13
PID20
12
PID19
11
PID18
10
PID17
9
PID16
8
PID15
7
PID14
6
PID13
5
PID12
4
PID11
3
PID10
2
PID9
1
PID8
0
PID7
PID6
PID5
PID4
PID3
PID2
-
-
* PIDx: Peripheral Clock x Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled.
Note: PID2 to PID31 refer to identifiers as defined in the section "Peripheral Identifiers" in the product datasheet.
354
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27.9.7 PMC Clock Generator Main Oscillator Register CKGR_MOR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 OSCOUNT 7 - 6 - 5 - 4 - 3 - 2 - 1 OSCBYPASS 0 MOSCEN 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0 = The Main Oscillator is disabled. 1 = The Main Oscillator is enabled. OSCBYPASS must be set to 0. When MOSCEN is set, the MOSCS flag is set once the Main Oscillator startup time is achieved. * OSCBYPASS: Oscillator Bypass 0 = No effect. 1 = The Main Oscillator is bypassed. MOSCEN must be set to 0. An external clock must be connected on XIN. When OSCBYPASS is set, the MOSCS flag in PMC_SR is automatically set. Clearing MOSCEN and OSCBYPASS bits allows resetting the MOSCS flag. * OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles multiplied by 8 for the Main Oscillator start-up time.
355
6249B-ATARM-14-Dec-06
27.9.8
PMC Clock Generator Main Clock Frequency Register CKGR_MCFR Read-only
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MAINF 7 6 5 4 MAINF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 MAINRDY 8
Register Name: Access Type:
31 - 23 - 15
* MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. * MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available.
356
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6249B-ATARM-14-Dec-06
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27.9.9 PMC Clock Generator PLL A Register CKGR_PLLAR Read/Write
30 - 22 29 1 21 28 - 20 MULA 15 OUTA 7 6 5 4 DIVA 3 14 13 12 11 PLLACOUNT 2 1 0 10 9 8 27 - 19 26 25 MULA 17 24
Register Name: Access Type:
31 - 23
18
16
Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR register. * DIVA: Divider A
DIVA 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the Main Clock divided by DIVA.
* PLLACOUNT: PLL A Counter Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. * OUTA: PLL A Clock Frequency Range To optimize clock performance, this field must be programmed as specified in "PLL Characteristics" in the Electrical Characteristics section of the product datasheet. * MULA: PLL A Multiplier 0 = The PLL A is deactivated. 1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1.
357
6249B-ATARM-14-Dec-06
27.9.10
PMC Clock Generator PLL B Register CKGR_PLLBR Read/Write
30 - 22 29 USBDIV 21 20 MULB 28 27 - 19 26 25 MULB 17 24
Register Name: Access Type:
31 - 23
18
16
15 OUTB 7
14
13
12
11 PLLBCOUNT
10
9
8
6
5
4 DIVB
3
2
1
0
Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC. * DIVB: Divider B
DIVB 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIVB.
* PLLBCOUNT: PLL B Counter Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written. * OUTB: PLLB Clock Frequency Range To optimize clock performance, this field must be programmed as specified in "PLL Characteristics" in the Electrical Characteristics section of the product datasheet. * MULB: PLL Multiplier 0 = The PLL B is deactivated. 1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1. * USBDIV: Divider for USB Clock
USBDIV 0 0 1 1 0 1 0 1 Divider for USB Clock(s) Divider output is PLL B clock output. Divider output is PLL B clock output divided by 2. Divider output is PLL B clock output divided by 4. Reserved.
358
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6249B-ATARM-14-Dec-06
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27.9.11 PMC Master Clock Register PMC_MCKR Read/Write
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2 1
MDIV
0
-
-
-
PRES
CSS
* CSS: Master Clock Selection
CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected PLL A Clock is selected PLL B Clock is selected
* PRES: Processor Clock Prescaler
PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Processor Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved
* MDIV: Master Clock Division
MDIV 0 0 1 1 0 1 0 1 Master Clock Division Master Clock is Processor Clock. Master Clock is Processor Clock divided by 2. Master Clock is Processor Clock divided by 4. Reserved.
359
6249B-ATARM-14-Dec-06
27.9.12
PMC Programmable Clock Register PMC_PCKx Read/Write
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
PRES
CSS
* CSS: Master Clock Selection
CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected PLL A Clock is selected PLL B Clock is selected
* PRES: Programmable Clock Prescaler
PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Programmable Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved
360
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6249B-ATARM-14-Dec-06
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27.9.13 PMC Interrupt Enable Register PMC_IER Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCKB
LOCKA
MOSCS
* MOSCS: Main Oscillator Status Interrupt Enable * LOCKA: PLL A Lock Interrupt Enable * LOCKB: PLL B Lock Interrupt Enable * MCKRDY: Master Clock Ready Interrupt Enable * PCKRDYx: Programmable Clock Ready x Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
361
6249B-ATARM-14-Dec-06
27.9.14
PMC Interrupt Disable Register PMC_IDR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCKB
LOCKA
MOSCS
* MOSCS: Main Oscillator Status Interrupt Disable * LOCKA: PLL A Lock Interrupt Disable * LOCKB: PLL B Lock Interrupt Disable * MCKRDY: Master Clock Ready Interrupt Disable * PCKRDYx: Programmable Clock Ready x Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
362
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
27.9.15 PMC Status Register PMC_SR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCKB
LOCKA
MOSCS
* MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. * LOCKA: PLL A Lock Status 0 = PLL A is not locked 1 = PLL A is locked. * LOCKB: PLL B Lock Status 0 = PLL B is not locked. 1 = PLL B is locked. * MCKRDY: Master Clock Status 0 = Master Clock is not ready. 1 = Master Clock is ready. * PCKRDYx: Programmable Clock Ready Status 0 = Programmable Clock x is not ready. 1 = Programmable Clock x is ready.
363
6249B-ATARM-14-Dec-06
27.9.16
PMC Interrupt Mask Register PMC_IMR Read-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
PCKRDY3
3
PCKRDY2
2
PCKRDY1
1
PCKRDY0
0
-
-
-
-
MCKRDY
LOCKB
LOCKA
MOSCS
* MOSCS: Main Oscillator Status Interrupt Mask * LOCKA: PLL A Lock Interrupt Mask * LOCKB: PLL B Lock Interrupt Mask * MCKRDY: Master Clock Ready Interrupt Mask * PCKRDYx: Programmable Clock Ready x Interrupt Mask 0 = The corresponding interrupt is enabled. 1 = The corresponding interrupt is disabled.
364
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6249B-ATARM-14-Dec-06
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27.9.17 PLL Charge Pump Current Register PMC_PLLICPR Write-only
30 29 28 27 26 25 24
Register Name: Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
ICPPLLB
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
-
-
-
-
-
-
ICPPLLA
* ICPPLLA: Charge pump current Must be set to 1. * ICPPLLB: Charge pump current Must be set to 1.
365
6249B-ATARM-14-Dec-06
366
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
28. Advanced Interrupt Controller (AIC)
28.1 Description
The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive. The fast forcing feature redirects any internal or external interrupt source to provide a fast interrupt rather than a normal interrupt.
367
6249B-ATARM-14-Dec-06
28.2
Block Diagram
Figure 28-1. Block Diagram
FIQ IRQ0-IRQn AIC ARM Processor Up to Thirty-two Sources nFIQ nIRQ
Embedded PeripheralEE Embedded
Peripheral Embedded
Peripheral
APB
28.3
Application Block Diagram
Figure 28-2. Description of the Application Block
OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts)
28.4
AIC Detailed Block Diagram
Figure 28-3. AIC Detailed Block Diagram
Advanced Interrupt Controller FIQ PIO Controller External Source Input Stage Fast Interrupt Controller ARM Processor nFIQ
nIRQ IRQ0-IRQn PIOIRQ Internal Source Input Stage Fast Forcing Interrupt Priority Controller Processor Clock Power Management Controller User Interface Wake Up
Embedded Peripherals
APB
368
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28.5 I/O Line Description
I/O Line Description
Pin Description Fast Interrupt Interrupt 0 - Interrupt n Type Input Input
Table 28-1.
Pin Name FIQ IRQ0 - IRQn
28.6
28.6.1
Product Dependencies
I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path.
28.6.2
Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
28.6.3
Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines, such as the System Timer, the Real Time Clock, the Power Management Controller and the Memory Controller. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
369
6249B-ATARM-14-Dec-06
28.7
28.7.1
Functional Description
Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low levelsensitive modes, or in positive edge-triggered or negative edge-triggered modes.
28.7.1.1
28.7.1.2
Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts. Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the "memorization" circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See "Priority Controller" on page 373.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR. Note that the automatic interrupt clear is disabled if the interrupt source has the Fast Forcing feature enabled as it is considered uniquely as a FIQ source. (For further details, See "Fast Forcing" on page 377.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read.
28.7.1.3
28.7.1.4
Interrupt Status For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (see "Priority Controller" on page 373) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems.
370
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28.7.1.5 Figure 28-4. Internal Interrupt Source Input Stage Internal Interrupt Source Input Stage
AIC_SMRI (SRCTYPE) Source i Level/ Edge AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller AIC_IECR
Edge
Detector Set Clear AIC_ISCR AIC_ICCR FF
AIC_IDCR
28.7.1.6
External Interrupt Source Input Stage
Figure 28-5. External Interrupt Source Input Stage
High/Low AIC_SMRi SRCTYPE Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Pos./Neg. Edge Detector Set AIC_ISCR AIC_ICCR Clear AIC_IDCR AIC_IECR
FF
371
6249B-ATARM-14-Dec-06
28.7.2
Interrupt Latencies Global interrupt latencies depend on several parameters, including: * The time the software masks the interrupts. * Occurrence, either at the processor level or at the AIC level. * The execution time of the instruction in progress when the interrupt occurs. * The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources.
28.7.2.1 Figure 28-6.
External Interrupt Edge Triggered Source External Interrupt Edge Triggered Source
MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge)
nIRQ Maximum IRQ Latency = 4 Cycles
nFIQ Maximum FIQ Latency = 4 Cycles
28.7.2.2 Figure 28-7.
External Interrupt Level Sensitive Source External Interrupt Level Sensitive Source
MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles
nFIQ Maximum FIQ Latency = 3 cycles
372
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28.7.2.3 Internal Interrupt Edge Triggered Source Figure 28-8. Internal Interrupt Edge Triggered Source
MCK
nIRQ
Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active
28.7.2.4
Internal Interrupt Level Sensitive Source
Figure 28-9. Internal Interrupt Level Sensitive Source
MCK
nIRQ
Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active
28.7.3 28.7.3.1
Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing). Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SMR (Source Mode Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first.
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The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 28.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the high priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 28.7.3.3 Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system's general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 28.7.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits.
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It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring
LDR PC, [PC, # -&F20]
When nIRQ is asserted, if the bit "I" of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: - Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. - De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. - Automatically clears the interrupt, if it has been programmed to be edge-triggered. - Pushes the current level and the current interrupt number on to the stack. - Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the "I" bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that are used and restoring them at the end. During this phase, an interrupt of higher priority than the current level restarts the sequence from step 1.
Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase.
7. The "I" bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the "I" bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has the effect of returning from the interrupt to whatever was
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being executed before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq.
Note: The "I" bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked).
28.7.4 28.7.4.1
Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled.
28.7.4.2
28.7.4.3
Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction:
LDR PC,[PC,# -&F20]
When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 28.7.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt:
LDR PC, [PC, # -&F20]
3. The user does not need nested fast interrupts. When nFIQ is asserted, if the bit "F" of CPSR is 0, the sequence is:
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1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR.
Note: The "F" bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 28.7.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source. When Fast Forcing is disabled, the interrupt sources are handled as described in the previous pages. When Fast Forcing is enabled, the edge/level programming and, in certain cases, edge detection of the interrupt source is still active but the source cannot trigger a normal interrupt to the processor and is not seen by the priority handler. If the interrupt source is programmed in level-sensitive mode and an active level is sampled, Fast Forcing results in the assertion of the nFIQ line to the core. If the interrupt source is programmed in edge-triggered mode and an active edge is detected, Fast Forcing results in the assertion of the nFIQ line to the core.
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The Fast Forcing feature does not affect the Source 0 pending bit in the Interrupt Pending Register (AIC_IPR). The FIQ Vector Register (AIC_FVR) reads the contents of the Source Vector Register 0 (AIC_SVR0), whatever the source of the fast interrupt may be. The read of the FVR does not clear the Source 0 when the fast forcing feature is used and the interrupt source should be cleared by writing to the Interrupt Clear Command Register (AIC_ICCR). All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus lost interrupts are prevented. The read of AIC_IVR does not clear the source that has the fast forcing feature enabled. The source 0, reserved to the fast interrupt, continues operating normally and becomes one of the Fast Interrupt sources. Figure 28-10. Fast Forcing
Source 0 _ FIQ Input Stage AIC_IMR AIC_IPR
Automatic Clear
nFIQ
Read FVR if Fast Forcing is disabled on Sources 1 to 31. AIC_FFSR Source n Input Stage Automatic Clear AIC_IMR AIC_IPR Priority Manager nIRQ
Read IVR if Source n is the current interrupt and if Fast Forcing is disabled on Source n.
28.7.5
Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences: * If an enabled interrupt with a higher priority than the current one is pending, it is stacked. * If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write
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(arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 28.7.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: * An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. * An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) * An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 28.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution.
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28.8
28.8.1
Advanced Interrupt Controller (AIC) User Interface
Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor support only a 4-Kbyte offset.
28.8.2
Register Mapping Register Mapping
Register Source Mode Register 0 Source Mode Register 1 --Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 --Source Vector Register 31 Interrupt Vector Register FIQ Interrupt Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register(2) Core Interrupt Status Register Reserved Reserved Interrupt Enable Command Register
(2) (2) (2)
Table 28-2.
Offset 0000 0x04 --0x7C 0x80 0x84 --0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C 0x140 0x144 0x148 Notes:
Name AIC_SMR0 AIC_SMR1 --AIC_SMR31 AIC_SVR0 AIC_SVR1 --AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR ----AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR --(2) (2)
Access Read/Write Read/Write --Read/Write Read/Write Read/Write --Read/Write Read-only Read-only Read-only Read-only Read-only Read-only ----Write-only Write-only Write-only Write-only Write-only Read/Write Read/Write --Write-only Write-only Read-only
Reset Value 0x0 0x0 --0x0 0x0 0x0 --0x0 0x0 0x0 0x0 0x0(1) 0x0 0x0 --------------0x0 0x0 ------0x0
Interrupt Disable Command Register Interrupt Clear Command Register(2) Interrupt Set Command Register
(2)
End of Interrupt Command Register Spurious Interrupt Vector Register Debug Control Register Reserved Fast Forcing Enable Register
AIC_FFER AIC_FFDR AIC_FFSR
Fast Forcing Disable Register
Fast Forcing Status Register(2)
1. The reset value of this register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 2. PID2...PID31 bit fields refer to the identifiers as defined in the section "Peripheral Identifiers" of the product datasheet.
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28.8.3 AIC Source Mode Register AIC_SMR0..AIC_SMR31 Read/Write 0x0
30 - 22 - 14 - 6 SRCTYPE 29 - 21 - 13 - 5 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 PRIOR 24 - 16 - 8 - 0
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx. * SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources.
SRCTYPE 0 0 1 1 0 1 0 1
Internal Interrupt Sources High level Sensitive Positive edge triggered High level Sensitive Positive edge triggered
External Interrupt Sources Low level Sensitive Negative edge triggered High level Sensitive Positive edge triggered
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28.8.4
AIC Source Vector Register AIC_SVR0..AIC_SVR31 Read/Write 0x0
30 29 28 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value:
31
* VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source.
28.8.5
AIC Interrupt Vector Register AIC_IVR Read-only 0x0
30 29 28 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value:
31
* IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU.
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28.8.6 AIC FIQ Vector Register AIC_FVR Read-only 0x0
30 29 28 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type: Reset Value:
31
* FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 28.8.7 AIC Interrupt Status Register AIC_ISR Read-only 0x0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 27 - 19 - 11 - 3 26 - 18 - 10 - 2 IRQID 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number.
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28.8.8
AIC Interrupt Pending Register AIC_IPR Read-only 0x0
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type: Reset Value:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is not pending. 1 = Corresponding interrupt is pending.
28.8.9
AIC Interrupt Mask Register AIC_IMR Read-only 0x0
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type: Reset Value:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled.
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28.8.10 AIC Core Interrupt Status Register AIC_CISR Read-only 0x0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 NIRQ 24 - 16 - 8 - 0 NIFQ
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. * NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active.
28.8.11
AIC Interrupt Enable Command Register AIC_IECR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID3: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt.
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28.8.12
AIC Interrupt Disable Command Register AIC_IDCR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt.
28.8.13
AIC Interrupt Clear Command Register AIC_ICCR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt.
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28.8.14 AIC Interrupt Set Command Register AIC_ISCR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 28.8.15 AIC End of Interrupt Command Register AIC_EOICR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment.
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28.8.16
AIC Spurious Interrupt Vector Register AIC_SPU Read/Write 0x0
30 29 28 SIQV 27 26 25 24
Register Name: Access Type: Reset Value:
31
23
22
21
20 SIQV
19
18
17
16
15
14
13
12 SIQV
11
10
9
8
7
6
5
4 SIQV
3
2
1
0
* SIQV: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt.
28.8.17
AIC Debug Control Register AIC_DEBUG Read/Write 0x0
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 GMSK 24 - 16 - 8 - 0 PROT
Register Name: Access Type: Reset Value:
31 - 23 - 15 - 7 -
* PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. * GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state.
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28.8.18 AIC Fast Forcing Enable Register AIC_FFER Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 -
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* SYS, PID2-PID31: Fast Forcing Enable 0 = No effect. 1 = Enables the fast forcing feature on the corresponding interrupt.
28.8.19
AIC Fast Forcing Disable Register AIC_FFDR Write-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 -
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* SYS, PID2-PID31: Fast Forcing Disable 0 = No effect. 1 = Disables the Fast Forcing feature on the corresponding interrupt.
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28.8.20 AIC Fast Forcing Status Register AIC_FFSR Read-only
30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 -
Register Name: Access Type:
31 PID31 23 PID23 15 PID15 7 PID7
* SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature is disabled on the corresponding interrupt. 1 = The Fast Forcing feature is enabled on the corresponding interrupt.
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29. Debug Unit (DBGU)
29.1 Description
The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel's ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two peripheral data controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM.
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29.2
Block Diagram
Figure 29-1. Debug Unit Functional Block Diagram
Peripheral Bridge Peripheral DMA Controller
APB
Debug Unit
DTXD
Transmit Power Management Controller
MCK
Baud Rate Generator Receive
Parallel Input/ Output
DRXD
COMMRX ARM Processor
nTRST
R
COMMTX
DCC Handler
Chip ID
ICE Access Handler Power-on Reset
force_ntrst
Interrupt Control
dbgu_irq
Table 29-1.
Pin Name DRXD DTXD
Debug Unit Pin Description
Description Debug Receive Data Debug Transmit Data Type Input Output
Figure 29-2. Debug Unit Application Example
Boot Program Debug Monitor Trace Manager
Debug Unit
RS232 Drivers Programming Tool Debug Console Trace Console
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29.3
29.3.1
Product Dependencies
I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit.
29.3.2
Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1. Interrupt Source Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 291. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered.
29.3.3
29.4
UART Operations
The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART.
29.4.1
Baud Rate Generator The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). MCK Baud Rate = --------------------16 x CD
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Figure 29-3. Baud Rate Generator
CD CD MCK 16-bit Counter
OUT
>1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock
29.4.2 29.4.2.1
Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost.
29.4.2.2
Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one.
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Figure 29-4. Start Bit Detection
Sampling Clock
DRXD
True Start Detection Baud Rate Clock
D0
Figure 29-5. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit period 1 bit period
DRXD
Sampling
D0 D1 True Start Detection
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
29.4.2.3
Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
Figure 29-6. Receiver Ready
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P
RXRDY
Read DBGU_RHR
29.4.2.4
Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
Figure 29-7. Receiver Overrun
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY OVRE
RSTSTA
29.4.2.5
Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received 395
6249B-ATARM-14-Dec-06
parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 29-8. Parity Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY PARE
Wrong Parity Bit
RSTSTA
29.4.2.6
Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1.
Figure 29-9. Receiver Framing Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY FRAME
Stop Bit Detected at 0
RSTSTA
29.4.3 29.4.3.1
Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters.
29.4.3.2
Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following
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figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 29-10. Character Transmission
Example: Parity enabled Baud Rate Clock DTXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
29.4.3.3
Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed.
Figure 29-11. Transmitter Control
DBGU_THR
Data 0 Data 1
Shift Register
Data 0
Data 1
DTXD
S
Data 0
P
stop
S
Data 1
P
stop
TXRDY TXEMPTY
Write Data 0 in DBGU_THR
Write Data 1 in DBGU_THR
29.4.4
Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt.
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The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 29.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 29-12. Test Modes
Automatic Echo Receiver RXD
Transmitter
Disabled
TXD
Local Loopback Receiver
Disabled
RXD
VDD Transmitter
Disabled
TXD
Remote Loopback Receiver
VDD Disabled RXD
Transmitter
Disabled
TXD
29.4.6
Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator.
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The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd
MCR
p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 29.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: * EXT - shows the use of the extension identifier register * NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size * ARCH - identifies the set of embedded peripheral * SRAMSIZ - indicates the size of the embedded SRAM * EPROC - indicates the embedded ARM processor * VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 29.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.
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29.5
Debug Unit (DBGU) User Interface
Debug Unit Memory Map
Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register Reserved PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR - DBGU_CIDR DBGU_EXID DBGU_FNR - - Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write - Read-only Read-only Read/Write - - Reset Value - 0x0 - - 0x0 - 0x0 - 0x0 - - - 0x0 - -
Table 29-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020
0x0024 - 0x003C 0x0040 0x0044 0x0048 0x004C - 0x00FC 0x0100 - 0x0124
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29.5.1 Name: Access Type:
31
Debug Unit Control Register DBGU_CR Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8 RSTSTA 0
-
7 TXDIS
-
6 TXEN
-
5 RXDIS
-
4 RXEN
-
3 RSTTX
-
2 RSTRX
-
1
-
-
* RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. * RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. * RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. * RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. * TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. * TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. * RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
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29.5.2 Name:
Debug Unit Mode Register DBGU_MR Read/Write
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15 CHMODE 7
-
14
-
13
-
12
-
11
-
10 PAR
-
9
-
8
-
6 5
-
4 3
-
1 0
2
-
-
-
-
-
-
-
-
* PAR: Parity Type
PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity
* CHMODE: Channel Mode
CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback
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29.5.3 Name: Access Type:
31 COMMRX 23
Debug Unit Interrupt Enable Register DBGU_IER Write-only
30 COMMTX 22 29 28 27 26 25 24
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Enable RXRDY Interrupt * TXRDY: Enable TXRDY Interrupt * ENDRX: Enable End of Receive Transfer Interrupt * ENDTX: Enable End of Transmit Interrupt * OVRE: Enable Overrun Error Interrupt * FRAME: Enable Framing Error Interrupt * PARE: Enable Parity Error Interrupt * TXEMPTY: Enable TXEMPTY Interrupt * TXBUFE: Enable Buffer Empty Interrupt * RXBUFF: Enable Buffer Full Interrupt * COMMTX: Enable COMMTX (from ARM) Interrupt * COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt.
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29.5.4 Name:
Debug Unit Interrupt Disable Register DBGU_IDR Write-only
30 COMMTX 22 29 28 27 26 25 24
Access Type:
31 COMMRX 23
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Disable RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Disable End of Receive Transfer Interrupt * ENDTX: Disable End of Transmit Interrupt * OVRE: Disable Overrun Error Interrupt * FRAME: Disable Framing Error Interrupt * PARE: Disable Parity Error Interrupt * TXEMPTY: Disable TXEMPTY Interrupt * TXBUFE: Disable Buffer Empty Interrupt * RXBUFF: Disable Buffer Full Interrupt * COMMTX: Disable COMMTX (from ARM) Interrupt * COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt.
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29.5.5 Name: Access Type:
31 COMMRX 23
Debug Unit Interrupt Mask Register DBGU_IMR Read-only
30 COMMTX 22 29 28 27 26 25 24
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Mask RXRDY Interrupt * TXRDY: Disable TXRDY Interrupt * ENDRX: Mask End of Receive Transfer Interrupt * ENDTX: Mask End of Transmit Interrupt * OVRE: Mask Overrun Error Interrupt * FRAME: Mask Framing Error Interrupt * PARE: Mask Parity Error Interrupt * TXEMPTY: Mask TXEMPTY Interrupt * TXBUFE: Mask TXBUFE Interrupt * RXBUFF: Mask RXBUFF Interrupt * COMMTX: Mask COMMTX Interrupt * COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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29.5.6 Name:
Debug Unit Status Register DBGU_SR Read-only
30 COMMTX 22 29 28 27 26 25 24
Access Type:
31 COMMRX 23
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 RXBUFF 4 ENDTX
-
11 TXBUFE 3 ENDRX
-
10
-
9 TXEMPTY 1 TXRDY
-
8
-
7 PARE
-
6 FRAME
-
5 OVRE
-
2
-
0 RXRDY
-
* RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. * TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. * ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. * ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. * OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. * PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. * TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. * TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. * RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active.
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* COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. * COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active.
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29.5.7 Name:
Debug Unit Receiver Holding Register DBGU_RHR Read-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4 RXCHR
-
3
-
2
-
1
-
0
* RXCHR: Received Character Last received character if RXRDY is set.
29.5.8 Name:
Debug Unit Transmit Holding Register DBGU_THR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4 TXCHR
-
3
-
2
-
1
-
0
* TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
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29.5.9 Name: Access Type:
31
Debug Unit Baud Rate Generator Register DBGU_BRGR Read/Write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 CD
-
11
-
10
-
9
-
8
7
6
5
4 CD
3
2
1
0
* CD: Clock Divisor
CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16)
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29.5.10 Name:
Debug Unit Chip ID Register DBGU_CIDR Read-only
30 29 NVPTYP 22 ARCH 21 20 19 18 SRAMSIZ 13 NVPSIZ2 12 11 10 NVPSIZ 5 4 3 2 VERSION 1 0 9 8 28 27 26 ARCH 17 16 25 24
Access Type:
31 EXT 23
15
14
7
6 EPROC
* VERSION: Version of the Device * EPROC: Embedded Processor
EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ESTM ARM7TDMI(R) ARM920TTM ARM926EJ-STM
* NVPSIZ: Nonvolatile Program Memory Size
NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved
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* NVPSIZ2 Second Nonvolatile Program Memory Size
NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved
* SRAMSIZ: Internal SRAM Size
SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes Reserved 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes
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* ARCH: Architecture Identifier
ARCH Hex 0x19 0x29 0x34 0x39 0x40 0x42 0x55 0x60 0x63 0x70 0x71 0x72 0x73 0x75 0x92 0xF0 Bin 0001 1001 0010 1001 0011 0100 0011 1001 0100 0000 0100 0010 0101 0101 0101 0000 0110 0011 0111 0000 0111 0001 0111 0010 0111 0011 0111 0101 1001 0010 1111 0001 Architecture AT91SAM9xx Series AT91SAM9XExx Series AT91x34 Series CAP9 Series AT91x40 Series AT91x42 Series AT91x55 Series AT91SAM7Axx Series AT91x63 Series AT91SAM7Sxx Series AT91SAM7XCxx Series AT91SAM7SExx Series AT91SAM7Lxx Series AT91SAM7Xxx Series AT91x92 Series AT75Cxx Series
* NVPTYP: Nonvolatile Program Memory Type
NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size
* EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.
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29.5.11 Name: Access Type:
31
Debug Unit Chip ID Extension Register DBGU_EXID Read-only
30 29 28 EXID 27 26 25 24
23
22
21
20 EXID
19
18
17
16
15
14
13
12 EXID
11
10
9
8
7
6
5
4 EXID
3
2
1
0
* EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
29.5.12 Name:
Debug Unit Force NTRST Register DBGU_FNR Read/Write
30 29 28 27 26 25 24
Access T ype:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0 FNTRST
-
-
-
-
-
-
-
* FNTRST: Force NTRST 0 = NTRST of the ARM processor's TAP controller is driven by power-on reset. 1 = NTRST of the ARM processor's TAP controller is held low.
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30. Parallel Input/Output (PIO) Controller
30.1 Description
The Parallel Input/Output (PIO) Controller manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: * An input change interrupt enabling level change detection on any I/O line. * A glitch filter providing rejection of pulses lower than one-half of clock cycle. * Multi-drive capability similar to an open drain I/O line. * Control of the the pull-up of the I/O line. * Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
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30.2
Block Diagram
Figure 30-1. Block Diagram
PIO Controller
AIC PIO Interrupt
PMC
PIO Clock
Data, Enable
Embedded Peripheral
Up to 32 peripheral IOs
PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31
APB
Figure 30-2. Application Block Diagram
On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals
PIO Controller
Keyboard Driver General Purpose I/Os External Devices
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30.3
30.3.1
Product Dependencies
Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e., not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.
30.3.2
External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.
30.3.3
30.3.4
Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
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30.4
Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 30-3. In this description each signal shown represents but one of up to 32 possible indexes.
Figure 30-3. I/O Line Control Logic
PIO_OER[0] PIO_OSR[0] PIO_ODR[0]
1
PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0]
Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output
0
0 0
1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0
0
1
PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0
1
1
PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0]
Pad 1
Peripheral A Input Peripheral B Input
PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1
PIO_ISR[0]
(Up to 32 possible inputs) PIO Interrupt
PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31]
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30.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e., PIO_PUSR resets at the value 0x0. 30.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e., PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 30.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 30.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not.
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When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 30.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OSWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 30.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multidriver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 30.4.7 Output Line Timings Figure 30-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 30-4 also shows when the feedback in PIO_PDSR is available.
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Figure 30-4. Output Line Timings
MCK
Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0
APB Access
APB Access
PIO_ODSR 2 cycles PIO_PDSR 2 cycles
30.4.8
Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
30.4.9
Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 30-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled.
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Figure 30-5. Input Glitch Filter Timing
MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle
30.4.10
Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled.
Figure 30-6. Input Change Interrupt Timings
MCK
Pin Level
PIO_ISR
Read PIO_ISR
APB Access
APB Access
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30.5 I/O Lines Programming Example
The programing example as shown in Table 30-1 below is used to define the following configuration. * 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), opendrain, with pull-up resistor * Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor * Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts * Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter * I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor * I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor * I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 30-1. Programming Example
Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0
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30.6
Parallel Input/Ouput (PIO) Controller User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically.
Table 30-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C
Register Mapping
Register PIO Enable Register PIO Disable Register PIO Status Register (1) Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register(2) Pin Data Status Register
(3)
Name PIO_PER PIO_PDR PIO_PSR
Access Write-only Write-only Read-only
Reset Value - - 0x0000 0000
PIO_OER PIO_ODR PIO_OSR
Write-only Write-only Read-only
- - 0x0000 0000
PIO_IFER PIO_IFDR PIO_IFSR
Write-only Write-only Read-only
- - 0x0000 0000
PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR
Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only
- - 0x0000 0000
Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register
(4)
- - 0x00000000 0x00000000 - - 0x00000000
PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR
Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved
PIO_PUDR PIO_PUER PIO_PUSR
Write-only Write-only Read-only
- - 0x00000000
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Table 30-2.
Offset 0x0070 0x0074 0x0078 0x007C to 0x009C 0x00A0 0x00A4 0x00A8 0x00AC Notes: 1. 2. 3. 4.
Register Mapping (Continued)
Register Peripheral A Select Register Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only - - 0x00000000
(5) (5) (5)
Name PIO_ASR PIO_BSR PIO_ABSR
Access Write-only Write-only Read-only
Reset Value - - 0x00000000
Reset value of PIO_PSR depends on the product implementation. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. Reset value of PIO_PDSR depends on the level of the I/O lines. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.
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30.6.1 Name:
PIO Controller PIO Enable Register PIO_PER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 30.6.2 Name: Access Type:
31
PIO Controller PIO Disable Register PIO_PDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
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30.6.3 Name: Access Type:
31
PIO Controller PIO Status Register PIO_PSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive).
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30.6.4 Name:
PIO Controller Output Enable Register PIO_OER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 30.6.5 Name: Access Type:
31
PIO Controller Output Disable Register PIO_ODR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line.
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30.6.6 Name: Access Type:
31
PIO Controller Output Status Register PIO_OSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output.
429
6249B-ATARM-14-Dec-06
30.6.7 Name:
PIO Controller Input Filter Enable Register PIO_IFER Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 30.6.8 Name: Access Type:
31
PIO Controller Input Filter Disable Register PIO_IFDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line.
430
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.9 Name: Access Type:
31
PIO Controller Input Filter Status Register PIO_IFSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line.
431
6249B-ATARM-14-Dec-06
30.6.10 Name:
PIO Controller Set Output Data Register PIO_SODR Write-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 30.6.11 Name: Access Type:
31
PIO Controller Clear Output Data Register PIO_CODR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line.
432
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.12 Name: Access Type:
31
PIO Controller Output Data Status Register PIO_ODSR Read-only or Read/Write
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1.
433
6249B-ATARM-14-Dec-06
30.6.13 Name:
PIO Controller Pin Data Status Register PIO_PDSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1.
434
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.14 Name: Access Type:
31
PIO Controller Interrupt Enable Register PIO_IER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 30.6.15 Name: Access Type:
31
PIO Controller Interrupt Disable Register PIO_IDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line.
435
6249B-ATARM-14-Dec-06
30.6.16 Name:
PIO Controller Interrupt Mask Register PIO_IMR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 30.6.17 Name: Access Type:
31
PIO Controller Interrupt Status Register PIO_ISR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
436
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.18 Name: Access Type:
31
PIO Multi-driver Enable Register PIO_MDER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 30.6.19 Name: Access Type:
31
PIO Multi-driver Disable Register PIO_MDDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line.
437
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.20 Name: Access Type:
31
PIO Multi-driver Status Register PIO_MDSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
438
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.21 Name: Access Type:
31
PIO Pull Up Disable Register PIO_PUDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 30.6.22 Name: Access Type:
31
PIO Pull Up Enable Register PIO_PUER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line.
439
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.23 Name: Access Type:
31
PIO Pull Up Status Register PIO_PUSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line.
440
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.24 Name: Access Type:
31
PIO Peripheral A Select Register PIO_ASR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 30.6.25 Name: Access Type:
31
PIO Peripheral B Select Register PIO_BSR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function.
441
6249B-ATARM-14-Dec-06
30.6.26 Name:
PIO Peripheral A B Status Register PIO_ABSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B.
442
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
30.6.27 Name: Access Type:
31
PIO Output Write Enable Register PIO_OWER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 30.6.28 Name: Access Type:
31
PIO Output Write Disable Register PIO_OWDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line.
443
6249B-ATARM-14-Dec-06
30.6.29 Name:
PIO Output Write Status Register PIO_OWSR Read-only
30 29 28 27 26 25 24
Access Type:
31
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
* P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line.
444
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
31. Serial Peripheral Interface (SPI)
31.1 Description
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the "master"' which controls the data flow, while the other devices act as "slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: * Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). * Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. * Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. * Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
445
6249B-ATARM-14-Dec-06
31.2
Block Diagram
Figure 31-1. Block Diagram
PDC APB SPCK MISO MCK SPI Interface PIO MOSI NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3
PMC
SPI Interrupt
31.3
Application Block Diagram
Figure 31-2. Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS
446
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
31.4 Signal Description
Signal Description
Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input
Table 31-1.
31.5
31.5.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.
31.5.2
Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI.
31.5.3
447
6249B-ATARM-14-Dec-06
31.6
31.6.1
Functional Description
Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.
31.6.2
Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 31-2 shows the four modes and corresponding parameter settings. Table 31-2. SPI Bus Protocol Mode
SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0
Figure 31-3 and Figure 31-4 show examples of data transfers.
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Figure 31-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8
SPCK (CPOL = 1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
MSB
6
5
4
3
2
1
LSB
*
NSS (to slave)
* Not defined, but normally MSB of previous character received.
Figure 31-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8
SPCK (CPOL = 1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
*
MSB
6
5
4
3
2
1
LSB
NSS (to slave)
* Not defined but normally LSB of previous character transmitted.
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31.6.3
Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writting the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 31-6 on page 452 shows a block diagram of the SPI when operating in Master Mode. Figure 31-6 on page 452 shows a flow chart describing how transfers are handled.
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31.6.3.1 Master Mode Block Diagram Figure 31-5. Master Mode Block Diagram
SPI_CSR0..3 SCBR Baud Rate Generator
MCK
SPCK
SPI Clock SPI_CSR0..3 BITS NCPHA CPOL MISO LSB
SPI_RDR RD
RDRF OVRES
Shift Register
MSB
MOSI
SPI_TDR TD SPI_CSR0..3 CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral SPI_RDR PCS NPCS3 NPCS2 NPCS1 TDRE
MSTR NPCS0 MODFDIS
MODF
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31.6.3.2
Master Mode Flow Diagram
Figure 31-6. Master Mode Flow Diagram S
SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ?
0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral
0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral
1
SPI_TDR(PCS) = NPCS ? no NPCS = 0xF
SPI_MR(PCS) = NPCS ? no NPCS = 0xF
1
NPCS = SPI_TDR(PCS)
Delay DLYBCS
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = SPI_MR(PCS), SPI_TDR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD) TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer RDRF = 1
Delay DLYBCT
0 TDRE ?
1
1 CSAAT ?
0 NPCS = 0xF
Delay DLYBCS
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31.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK) , by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 31.6.3.4 Transfer Delays Figure 31-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: * The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. * The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. * The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 31-7. Programmable Delays
Chip Select 1
Chip Select 2
SPCK DLYBCS DLYBS DLYBCT DLYBCT
31.6.3.5
Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways:
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* Fixed Peripheral Select: SPI exchanges data with only one peripheral * Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 31.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 31.6.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers.
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To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. Figure 31-8 shows different peripheral deselection cases and the effect of the CSAAT bit. Figure 31-8. Peripheral Deselection
CSAAT = 0 CSAAT = 1
TDRE
DLYBCT A DLYBCS PCS = A A A
DLYBCT A DLYBCS PCS = A A
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCT A DLYBCS PCS=A A A
DLYBCT A DLYBCS PCS = A A
NPCS[0..3]
Write SPI_TDR
TDRE NPCS[0..3]
DLYBCT A DLYBCS PCS = B B A
DLYBCT B DLYBCS PCS = B
Write SPI_TDR
31.6.3.8
Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
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31.6.4
SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit rises and the data transfer to SPI_RDR is aborted. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 31-9 shows a block diagram of the SPI when operating in Slave Mode.
Figure 31-9. Slave Mode Functional Block Diagram
SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock
Shift Register
MSB
MISO
SPI_TDR TD TDRE
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31.7 Serial Peripheral Interface (SPI) User Interface
SPI Register Mapping
Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 - - Read/Write Read/Write Read/Write Read/Write - - 0x0 0x0 0x0 0x0 - - Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0
Table 31-3.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C
0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00F8 0x004C - 0x00FC 0x100 - 0x124
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31.7.1 Name:
SPI Control Register SPI_CR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
LASTXFER
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
SWRST
-
-
-
-
-
SPIDIS
SPIEN
* SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. * SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its tranfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. * SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset. * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
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31.7.2 Name: Access Type:
31
SPI Mode Register SPI_MR Read/Write
30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
LLB
-
-
MODFDIS
PCSDEC
PS
MSTR
* MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. * PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. * PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14. * MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. * LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled ( LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) * PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) 459
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NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
If PCSDEC = 1: NPCS[3:0] output signals = PCS. * DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: DLYBCS Delay Between Chip Selects = ---------------------MCK
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31.7.3 Name: Access Type:
31
SPI Receive Data Register SPI_RDR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
RD
7 6 5 4 3 2 1 0
RD
* RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. * PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
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31.7.4 Name:
SPI Transmit Data Register SPI_TDR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
LASTXFER
16
-
15
-
14
-
13
-
12 11 10
PCS
9 8
TD
7 6 5 4 3 2 1 0
TD
* TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don't care) If PCSDEC = 1: NPCS[3:0] output signals = PCS * LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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31.7.5 Name: Access Type:
31
SPI Status Register SPI_SR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
SPIENS
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. * TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. * MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. * OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. * ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). * ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). * RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. * TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. * NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. * TXEMPTY: Transmission Registers Empty
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0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. * SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled.
Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC.
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31.7.6 Name: Access Type:
31
SPI Interrupt Enable Register SPI_IER Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Enable * TDRE: SPI Transmit Data Register Empty Interrupt Enable * MODF: Mode Fault Error Interrupt Enable * OVRES: Overrun Error Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * TXEMPTY: Transmission Registers Empty Enable * NSSR: NSS Rising Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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31.7.7 Name:
SPI Interrupt Disable Register SPI_IDR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Disable * TDRE: SPI Transmit Data Register Empty Interrupt Disable * MODF: Mode Fault Error Interrupt Disable * OVRES: Overrun Error Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * TXEMPTY: Transmission Registers Empty Disable * NSSR: NSS Rising Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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31.7.8 Name: Access Type:
31
SPI Interrupt Mask Register SPI_IMR Read-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
* RDRF: Receive Data Register Full Interrupt Mask * TDRE: SPI Transmit Data Register Empty Interrupt Mask * MODF: Mode Fault Error Interrupt Mask * OVRES: Overrun Error Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * TXEMPTY: Transmission Registers Empty Mask * NSSR: NSS Rising Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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31.7.9 Name: Access Type:
31
SPI Chip Select Register SPI_CSR0... SPI_CSR3 Read/Write
30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS
CSAAT
-
NCPHA
CPOL
* CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. * NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. * CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. * BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved
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BITS 1100 1101 1110 1111 Bits Per Transfer Reserved Reserved Reserved Reserved
* SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = -------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. * DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: Delay Before SPCK = DLYBS -----------------MCK * DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 x DLYBCT Delay Between Consecutive Transfers = -----------------------------------MCK
469
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32. Two-wire Interface (TWI)
32.1 Description
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byteoriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.
32.2
Block Diagram
Figure 32-1. Block Diagram
APB Bridge
TWCK PIO Two-wire Interface TWD
PMC
MCK
TWI Interrupt
AIC
32.3
Application Block Diagram
Figure 32-2. Application Block Diagram
VDD R TWD TWCK R
Host with TWI Interface
AT24LC16 U1 Slave 1
AT24LC16 U2 Slave 2
LCD Controller U3 Slave 3
471
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32.3.1
I/O Lines Description
Table 32-1.
Pin Name TWD TWCK
I/O Lines Description
Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output
32.4
32.4.1
Product Dependencies
I/O Lines Both TWD and TWCK are bi-directional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 32-2 on page 471). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: * Program the PIO controller to: - Dedicate TWD and TWCK as peripheral lines. - Define TWD and TWCK as open-drain.
32.4.2
Power Management * Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock.
32.4.3
Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI.
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32.5
32.5.1
Functional Description
Transfer format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 32-4 on page 473). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 32-3 on page 473). * A high-to-low transition on the TWD line while TWCK is high defines the START condition. * A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 32-3.
START and STOP Conditions
TWD
TWCK Start Stop
Figure 32-4. Transfer Format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
32.5.2
Modes of Operation The TWI has two modes of operation: * Master transmitter mode * Master receiver mode The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.
32.5.3
Transmitting Data After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation (transmit operation). If the bit is 1, it indicates a request for data read (receive operation). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse
473
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and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 32-6 below). The master generates a stop condition to end the transfer. The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address). The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). Figure 32-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address TWD
S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
Two bytes internal address TWD
S DADR W A IADR(15:8) A IADR(7:0) A DATA A P
One byte internal address TWD
S DADR W A IADR(7:0) A DATA A P
Figure 32-6. Master Write with One Byte Internal Address and Multiple Data Bytes
TWD S DADR W A IADR(7:0) A DATA A DATA A DATA A P
TXCOMP Write THR TXRDY Write THR Write THR Write THR
Figure 32-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A S DADR R A
DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A S DADR R A DATA
N
P
N
P
One byte internal address TWD S DADR W A IADR(7:0) A S DADR R A DATA N P
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Figure 32-8. Master Read with One Byte Internal Address and Multiple Data Bytes
TWD S DADR W A IADR(7:0) A S DADR R A DATA A DATA N P
TXCOMP Write START Bit RXRDY Write STOP Bit
Read RHR
Read RHR
* S = Start * P = Stop * W = Write * R = Read * A = Acknowledge * N = Not Acknowledge * DADR= Device Address * IADR = Internal Address Figure 32-9 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 32-9. Internal Address Usage
S T A R T W R I T E S T O P
Device Address 0 M S B
FIRST WORD ADDRESS
SECOND WORD ADDRESS
DATA
LRA S/C BW K
M S B
A C K
LA SC BK
A C K
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32.5.4
Read/Write Flowcharts The following flowcharts shown in Figure 32-10 on page 476 and in Figure 32-11 on page 477 give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
Figure 32-10. TWI Write in Master Mode
START
Set TWI clock: TWI_CWGR = clock
Set the control register: - Master enable TWI_CR = MSEN
Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Write ==> bit MREAD = 0
Internal address size = 0? Set theinternal address TWI_IADR = address
Yes Load transmit register TWI_THR = Data to send Start the transfer TWI_CR = START
Read status register
TWI_THR = data to send TXRDY = 0? Yes
Data to send? Yes
Stop the transfer TWI_CR = STOP
Read status register
TXCOMP = 0?
Yes
END
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Figure 32-11. TWI Read in Master Mode
START
Set TWI clock: TWI_CWGR = clock
Set the control register: - Master enable - Slave disable TWI_CR = MSEN
Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Read ==> bit MREAD = 0
Internal address size = 0? Set the internal address TWI_IADR = address
Yes Start the transfer TWI_CR = START
Read status register
RXRDY = 0?
Yes
Data to read? Yes
Stop the transfer TWI_CR = STOP
Read status register
TXCOMP = 0?
Yes
END
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32.6
32.6.1
TWI User Interface
Register Mapping Two-wire Interface (TWI) User Interface
Register Control Register Master Mode Register Reserved Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Name TWI_CR TWI_MMR TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR - Access Write-only Read/Write Read/Write Read/Write Read-only Write-only Write-only Read-only Read-only Read/Write - Reset Value N/A 0x0000 0x0000 0x0000 0x0008 N/A N/A 0x0000 0x0000 0x0000 -
Table 32-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034
0x0038 - 0x00FC
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32.6.2 TWI Control Register TWI_CR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 MSDIS 26 - 18 - 10 - 2 MSEN 25 - 17 - 9 - 1 STOP 24 - 16 - 8 - 0 START
Register Name: Access Type:
31 - 23 - 15 - 7 SWRST
* START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. * STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode. In single data byte master read or write, the START and STOP must both be set. In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission. In master read mode, if a NACK bit is received, the STOP is automatically performed. In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. * MSEN: TWI Master Transfer Enabled 0 = No effect. 1 = If MSDIS = 0, the master data transfer is enabled. * MSDIS: TWI Master Transfer Disabled 0 = No effect. 1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. * SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
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32.6.3
TWI Master Mode Register TWI_MMR Read/Write
30 - 22 29 - 21 28 - 20 27 - 19 DADR 11 - 3 - 26 - 18 25 - 17 24 - 16
Register Name: Address Type:
31 - 23 - 15 - 7 -
14 - 6 -
13 - 5 -
12 MREAD 4 -
10 - 2 -
9 IADRSZ 1 -
8
0 -
* IADRSZ: Internal Device Address Size
IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address (Byte command protocol) One-byte internal device address Two-byte internal device address Three-byte internal device address
* MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. * DADR: Device Address The device address is used in Master Mode to access slave devices in read or write mode.
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32.6.4 TWI Internal Address Register TWI_IADR Read/Write
30 - 22 29 - 21 28 - 20 IADR 15 14 13 12 IADR 7 6 5 4 IADR 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type:
31 - 23
* IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. - Low significant byte address in 10-bit mode addresses. 32.6.5 TWI Clock Waveform Generator Register TWI_CWGR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CHDIV 7 6 5 4 CLDIV 3 2 1 0 27 - 19 - 11 26 - 18 25 - 17 CKDIV 9 24 - 16
Register Name: Access Type:
31 - 23 - 15
10
8
* CLDIV: Clock Low Divider The SCL low period is defined as follows:
T low = ( ( CLDIV x 2
CKDIV
) + 3 ) x T MCK
* CHDIV: Clock High Divider The SCL high period is defined as follows:
T high = ( ( CHDIV x 2
CKDIV
) + 3 ) x T MCK
* CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods.
32.6.6
TWI Status Register TWI_SR 481
Register Name:
6249B-ATARM-14-Dec-06
Access Type:
31 - 23 - 15 - 7 -
Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
* TXCOMP: Transmission Completed 0 = In master, during the length of the current frame. In slave, from START received to STOP received. 1 = When both holding and shift registers are empty and STOP condition has been sent (in Master), or when MSEN is set (enable TWI). * RXRDY: Receive Holding Register Ready 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in theTWI_RHR since the last read. * TXRDY: Transmit Holding Register Ready 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). * NACK: Not Acknowledged 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
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32.6.7 TWI Interrupt Enable Register TWI_IER Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt. 32.6.8 TWI Interrupt Disable Register TWI_IDR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * NACK: Not Acknowledge 0 = No effect. 1 = Disables the corresponding interrupt.
483
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32.6.9
TWI Interrupt Mask Register TWI_IMR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 TXRDY 25 - 17 - 9 - 1 RXRDY 24 - 16 - 8 NACK 0 TXCOMP
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TXCOMP: Transmission Completed * RXRDY: Receive Holding Register Ready * TXRDY: Transmit Holding Register Ready * NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
32.6.10
TWI Receive Holding Register TWI_RHR Read-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RXDATA: Master or Slave Receive Holding Data
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32.6.11 TWI Transmit Holding Register TWI_THR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXDATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* TXDATA: Master or Slave Transmit Holding Data
485
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33. Universal Synchronous/Asynchronous Receiver/Transmitter
33.1 Description
The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
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33.2
Block Diagram
Figure 33-1. USART Block Diagram
Peripheral DMA Controller Channel Channel
USART
PIO Controller
RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS
PMC MCK MCK/DIV Baud Rate Generator SCK
DIV
User Interface SLCK
APB
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33.3 Application Block Diagram
Figure 33-2. Application Block Diagram
PPP Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver
USART
RS232 Drivers
RS485 Drivers
Smart Card Slot
IrDA Transceivers
Serial Port
Differential Bus
33.4
I/O Lines Description
I/O Line Description
Description Serial Clock Transmit Serial Data Receive Serial Data Clear to Send Request to Send Type I/O I/O Input Input Output Low Low Active Level
Table 33-1.
Name SCK TXD RXD CTS RTS
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33.5
33.5.1
Product Dependencies
I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
33.5.2
Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled.
33.5.3
Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
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33.6 Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: * 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.5 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling receiver frequency - Optional hardware handshaking - Optional break management - Optional multidrop serial communication * High-speed 5- to 9-bit full-duplex synchronous serial communication - MSB- or LSB-first - 1 or 2 stop bits - Parity even, odd, marked, space or none - By 8 or by 16 over-sampling frequency - Optional hardware handshaking - Optional break management - Optional multidrop serial communication * RS485 with driver control signal * ISO7816, T0 or T1 protocols for interfacing with smart cards - NACK handling, error counter with repetition and iteration limit * InfraRed IrDA Modulation and Demodulation * Test modes - Remote loopback, local loopback, automatic echo 33.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: * the Master Clock MCK * a division of the Master Clock, the divider being product dependent, but generally set to 8 * the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. 491
6249B-ATARM-14-Dec-06
Figure 33-3. Baud Rate Generator
USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC
SCK
33.6.1.1
Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate.
SelectedClock Baudrate = -------------------------------------------( 8 ( 2 - Over )CD )
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. Baud Rate Calculation Example Table 33-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 33-2. Baud Rate Example (OVER = 0)
Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 6 8 8 12 13 20 20 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% Error
Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000
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Table 33-2. Baud Rate Example (OVER = 0) (Continued)
Expected Baud Rate 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 Calculation Result 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 CD 23 24 30 39 40 40 52 53 54 65 81 98 114 Actual Baud Rate 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 Error 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06%
Source Clock 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000
The baud rate is calculated with the following formula: BaudRate = MCK CD x 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.
ExpectedBaudRate Error = 1 - -------------------------------------------------- ActualBaudRate
33.6.1.2
Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula:
SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 - Over ) CD + FP ------ 8
The modified architecture is presented below:
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Figure 33-4. Fractional Baud Rate Generator
FP
USCLKS MCK MCK/DIV SCK Reserved
CD
Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC
0 1 2 3 16-bit Counter glitch-free logic
>1 1
0
0
33.6.1.3
Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
BaudRate = SelectedClock ------------------------------------CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 33.6.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula:
Di B = ----- x f Fi
where: * B is the bit rate * Di is the bit-rate adjustment factor * Fi is the clock frequency division factor * f is the ISO7816 clock frequency (Hz)
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Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 33-3. Table 33-3.
DI field Di (decimal)
Binary and Decimal Values for Di
0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 33-4. Table 33-4.
FI field Fi (decimal
Binary and Decimal Values for Fi
0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048
Table 33-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 33-5.
Fi/Di 1 2 4 8 16 32 12 20
Possible Values for the Fi/Di Ratio
372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 33-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock.
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Figure 33-5. Elementary Time Unit (ETU)
FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD
1 ETU
33.6.2
Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The reset commands have the same effect as a hardware reset on the corresponding logic. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally.
33.6.3 33.6.3.1
Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only.
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Figure 33-6. Character Transmit
Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises. Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost. Figure 33-7. Transmitter Status
Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Write US_THR TXRDY
TXEMPTY
33.6.3.2
Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the
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transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 33-8 and Figure 33-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 33-8. Asynchronous Start Detection
Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling
Start Detection RXD Sampling
1
2
3
4
5
6
01 Start Rejection
7
2
3
4
Figure 33-9. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate Clock RXD Start Detection
16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
33.6.3.3
Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 33-10 illustrates a character reception in synchronous mode.
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Figure 33-10. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock
RXD Sampling
Start
D0
D1
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
33.6.3.4
Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
Figure 33-11. Receiver Status
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
RSTSTA = 1
Write US_CR Read US_RHR
RXRDY OVRE
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33.6.3.5
Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see "Multidrop Mode" on page 501. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 33-6 shows an example of the parity bit for the character 0x41 (character ASCII "A") depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 33-6.
Character A A A A A
Parity Bit Examples
Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 33-12 illustrates the parity bit status setting and clearing.
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Figure 33-12. Parity Error
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit
RSTSTA = 1
Write US_CR PARE
RXRDY
33.6.3.6
Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0.
33.6.3.7
Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 33-13, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted.
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Figure 33-13. Timeguard Operations
TG = 4 Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
TG = 4
Write US_THR TXRDY
TXEMPTY
Table 33-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 33-7. Maximum Timeguard Length Depending on Baud Rate
Bit time s 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21
Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200
33.6.3.8
Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: * Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state
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on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. * Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 33-14 shows the block diagram of the Receiver Time-out feature. Figure 33-14. Receiver Time-out Block Diagram
Baud Rate Clock TO
1 STTTO
D
Q
Clock
16-bit Time-out Counter Load
16-bit Value = TIMEOUT
Character Received RETTO
Clear
0
Table 33-8 gives the maximum time-out period for some standard baud rates. Table 33-8. Maximum Time-out Period
Bit Time s 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962
Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400
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Table 33-8.
Maximum Time-out Period (Continued)
Bit Time 18 17 5 Time-out 1 170 1 138 328
Baud Rate 56000 57600 200000
33.6.3.9
Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1.
Figure 33-15. Framing Error Status
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
RSTSTA = 1
Write US_CR FRAME
RXRDY
33.6.3.10
Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes.
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The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 33-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 33-16. Break Transmission
Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Break Transmission STPBRK = 1
End of Break
STTBRK = 1 Write US_CR TXRDY
TXEMPTY
33.6.3.11
Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit.
33.6.3.12
Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 33-17.
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Figure 33-17. Connection with a Remote Device for Hardware Handshaking
USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 33-18 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 33-18. Receiver Behavior when Operating with Hardware Handshaking
RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1
Figure 33-19 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 33-19. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
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33.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 33.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see "Baud Rate Generator" on page 491). The USART connects to a smart card as shown in Figure 33-20. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 33-20. Connection of a Smart Card to the USART
USART SCK TXD CLK I/O Smart Card
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to "USART Mode Register" on page 518 and "PAR: Parity Type" on page 519. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 33.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 33-21.
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If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 33-22. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 33-21. T = 0 Protocol without Parity Error
Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit
Figure 33-22. T = 0 Protocol with Parity Error
Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1
Repetition
Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION.
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When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 33.6.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 33-23. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 33-23. Connection to IrDA Transceivers
33.6.5
USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD
IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed.
509
6249B-ATARM-14-Dec-06
33.6.5.1
IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 33-9. Table 33-9.
Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s
IrDA Pulse Duration
Pulse Duration (3/16) 78.13 s 19.53 s 9.77 s 4.88 s 3.26 s 1.63 s
Figure 33-24 shows an example of character transmission. Figure 33-24. IrDA Modulation
Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1
TXD
Bit Period
3 16 Bit Period
33.6.5.2
IrDA Baud Rate Table 33-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of 1.87% must be met. Table 33-10. IrDA Baud Rate Error
Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 CD 2 11 18 22 4 22 36 43 6 33 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88
510
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Table 33-10. IrDA Baud Rate Error (Continued)
Peripheral Clock 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13
33.6.5.3
IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 33-25 illustrates the operations of the IrDA demodulator.
Figure 33-25. IrDA Demodulator Operations
MCK
RXD
Counter Value
6
Receiver Input
43 Pulse Rejected
5
2
6
6
5
4
3
2
1
0
Pulse Accepted
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly.
511
6249B-ATARM-14-Dec-06
33.6.6
RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 33-26.
Figure 33-26. Typical Connection to a RS485 Bus
USART
RXD
TXD RTS
Differential Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 33-27 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 33-27. Example of RTS Drive with Timeguard
TG = 4 Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Write US_THR TXRDY
TXEMPTY
RTS
512
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33.6.7 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 33.6.7.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin.
Figure 33-28. Normal Mode Configuration
RXD Receiver
TXD Transmitter
33.6.7.2
Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 33-29. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active.
Figure 33-29. Automatic Echo Mode Configuration
RXD Receiver
TXD Transmitter
33.6.7.3
Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 33-30. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state.
Figure 33-30. Local Loopback Mode Configuration
RXD Receiver
Transmitter
1
TXD
513
6249B-ATARM-14-Dec-06
33.6.7.4
Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 33-31. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission.
Figure 33-31. Remote Loopback Mode Configuration
Receiver 1 RXD
TXD Transmitter
514
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33.7 USART User Interface
USART Memory Map
Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR - US_FIDI US_NER - US_IF - - Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write - Read/Write Read-only - Read/Write - - Reset State - - - - 0x0 - 0x0 - 0x0 0x0 0x0 - 0x174 - - 0x0 - -
Table 33-11.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028
0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x5C - 0xFC 0x100 - 0x128
515
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33.7.1 Name:
USART Control Register US_CR Write-only
30 - 22 - 14 RSTNACK 6 TXEN 29 - 21 - 13 RSTIT 5 RXDIS 28 - 20 - 12 SENDA 4 RXEN 27 - 19 RTSDIS 11 STTTO 3 RSTTX 26 - 18 RTSEN 10 STPBRK 2 RSTRX 25 - 17 - 9 STTBRK 1 - 24 - 16 - 8 RSTSTA 0 -
Access Type:
31 - 23 - 15 RETTO 7 TXDIS
* RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. * RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. * RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. * RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. * TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. * TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. * RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, and RXBRK in US_CSR. * STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted.
516
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* STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. * STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. * SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. * RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. * RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. * RETTO: Rearm Time-out 0: No effect 1: Restart Time-out * RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. * RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1.
517
6249B-ATARM-14-Dec-06
33.7.2 Name:
USART Mode Register US_MR Read/Write
30 - 22 - 14 CHMODE 7 CHRL 6 5 USCLKS 29 - 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 - 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24
Access Type:
31 - 23 - 15
18 CLKO 10 PAR 2
16 MSBF 8 SYNC 0
1 USART_MODE
* USART_MODE
USART_MODE 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 0 x Mode of the USART Normal RS485 Hardware Handshaking Reserved IS07816 Protocol: T = 0 Reserved IS07816 Protocol: T = 1 Reserved IrDA Reserved
* USCLKS: Clock Selection
USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK / DIV Reserved SCK
518
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* CHRL: Character Length
CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits
* SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. * PAR: Parity Type
PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode
* NBSTOP: Number of Stop Bits
NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved
* CHMODE: Channel Mode
CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin.
* MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. * MODE9: 9-bit Character Length 0: CHRL defines character length.
519
6249B-ATARM-14-Dec-06
1: 9-bit character length. * CKLO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. * OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. * INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. * DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. * MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. * FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
520
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33.7.3 Name: USART Interrupt Enable Register US_IER Write-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 - 10 ITERATION 2 RXBRK 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 - 15 - 7 PARE
* RXRDY: RXRDY Interrupt Enable * TXRDY: TXRDY Interrupt Enable * RXBRK: Receiver Break Interrupt Enable * ENDRX: End of Receive Transfer Interrupt Enable * ENDTX: End of Transmit Interrupt Enable * OVRE: Overrun Error Interrupt Enable * FRAME: Framing Error Interrupt Enable * PARE: Parity Error Interrupt Enable * TIMEOUT: Time-out Interrupt Enable * TXEMPTY: TXEMPTY Interrupt Enable * ITERATION: Iteration Interrupt Enable * TXBUFE: Buffer Empty Interrupt Enable * RXBUFF: Buffer Full Interrupt Enable * NACK: Non Acknowledge Interrupt Enable * CTSIC: Clear to Send Input Change Interrupt Enable
521
6249B-ATARM-14-Dec-06
33.7.4 Name:
USART Interrupt Disable Register US_IDR Write-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 - 10 ITERATION 2 RXBRK 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 - 15 - 7 PARE
* RXRDY: RXRDY Interrupt Disable * TXRDY: TXRDY Interrupt Disable * RXBRK: Receiver Break Interrupt Disable * ENDRX: End of Receive Transfer Interrupt Disable * ENDTX: End of Transmit Interrupt Disable * OVRE: Overrun Error Interrupt Disable * FRAME: Framing Error Interrupt Disable * PARE: Parity Error Interrupt Disable * TIMEOUT: Time-out Interrupt Disable * TXEMPTY: TXEMPTY Interrupt Disable * ITERATION: Iteration Interrupt Disable * TXBUFE: Buffer Empty Interrupt Disable * RXBUFF: Buffer Full Interrupt Disable * NACK: Non Acknowledge Interrupt Disable * CTSIC: Clear to Send Input Change Interrupt Disable
522
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33.7.5 Name: USART Interrupt Mask Register US_IMR Read-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 - 10 ITERATION 2 RXBRK 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 - 15 - 7 PARE
* RXRDY: RXRDY Interrupt Mask * TXRDY: TXRDY Interrupt Mask * RXBRK: Receiver Break Interrupt Mask * ENDRX: End of Receive Transfer Interrupt Mask * ENDTX: End of Transmit Interrupt Mask * OVRE: Overrun Error Interrupt Mask * FRAME: Framing Error Interrupt Mask * PARE: Parity Error Interrupt Mask * TIMEOUT: Time-out Interrupt Mask * TXEMPTY: TXEMPTY Interrupt Mask * ITERATION: Iteration Interrupt Mask * TXBUFE: Buffer Empty Interrupt Mask * RXBUFF: Buffer Full Interrupt Mask * NACK: Non Acknowledge Interrupt Mask * CTSIC: Clear to Send Input Change Interrupt Mask
523
6249B-ATARM-14-Dec-06
33.7.6 Name:
USART Channel Status Register US_CSR Read-only
30 - 22 - 14 - 6 FRAME 29 - 21 - 13 NACK 5 OVRE 28 - 20 - 12 RXBUFF 4 ENDTX 27 - 19 CTSIC 11 TXBUFE 3 ENDRX 26 - 18 - 10 ITERATION 2 RXBRK 25 - 17 - 9 TXEMPTY 1 TXRDY 24 - 16 - 8 TIMEOUT 0 RXRDY
Access Type:
31 - 23 CTS 15 - 7 PARE
* RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. * TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. * RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. * ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. * ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. * OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. * FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. * PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. 524
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* TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). * TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There is at least one character in either US_THR or the Transmit Shift Register. * ITERATION: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSIT. 1: Maximum number of repetitions has been reached since the last RSIT. * TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. * RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. * NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. * CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. * CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1.
525
6249B-ATARM-14-Dec-06
33.7.7 Name:
USART Receive Holding Register US_RHR Read-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 RXCHR 0
Access Type:
31 - 23 - 15 RXSYNH 7
* RXCHR: Received Character Last character received if RXRDY is set. * RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 33.7.8 Name: USART Transmit Holding Register US_THR Write-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TXCHR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 TXCHR 0
Access Type:
31 - 23 - 15 TXSYNH 7
* TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. * TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC.
526
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33.7.9 Name: USART Baud Rate Generator Register US_BRGR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CD 7 6 5 4 CD 3 2 1 0 27 - 19 - 11 26 - 18 25 - 17 FP 9 24 - 16
Access Type:
31 - 23 - 15
10
8
* CD: Clock Divider
USART_MODE ISO7816 CD OVER = 0 0 1 to 65535 Baud Rate = Selected Clock/16/CD SYNC = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816
* FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8.
527
6249B-ATARM-14-Dec-06
33.7.10 Name:
USART Receiver Time-out Register US_RTOR Read/Write
30 29 28 27 26 25 24
Access Type:
31
- 23 - 15
- 22 - 14
- 21 - 13
- 20 - 12 TO
- 19 - 11
- 18 - 10
- 17 - 9
- 16 - 8
7
6
5
4 TO
3
2
1
0
* TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
528
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33.7.11 Name: USART Transmitter Timeguard Register US_TTGR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TG 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Access Type:
31 - 23 - 15 - 7
* TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
529
6249B-ATARM-14-Dec-06
33.7.12 Name:
USART FI DI RATIO Register US_FIDI Read/Write 0x174
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FI_DI_RATIO 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FI_DI_RATIO 1 24 - 16 - 8
Access Type: Reset Value :
31 - 23 - 15 - 7
2
0
* FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
530
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6249B-ATARM-14-Dec-06
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33.7.13 Name: USART Number of Errors Register US_NER Read-only
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 NB_ERRORS 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Access Type:
31 - 23 - 15 - 7
* NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
531
6249B-ATARM-14-Dec-06
33.7.14 Name:
USART IrDA FILTER Register US_IF Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 IRDA_FILTER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Access Type:
31 - 23 - 15 - 7
* IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
532
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34. Serial Synchronous Controller (SSC)
34.1 Description
The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC's high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: * CODEC's in master or slave mode * DAC through dedicated serial interface, particularly I2S * Magnetic card reader
533
6249B-ATARM-14-Dec-06
34.2
Block Diagram
Figure 34-1. Block Diagram
System Bus
APB Bridge
PDC Peripheral Bus TF TK TD SSC Interface PIO RF RK Interrupt Control RD
PMC
MCK
SSC Interrupt
34.3
Application Block Diagram
Figure 34-2. Application Block Diagram
OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management
Serial AUDIO
Codec
Line Interface
534
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34.4 Pin Name List
I/O Lines Description
Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output
Table 34-1.
Pin Name RF RK RD TF TK TD
34.5
34.5.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.
34.5.2
Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.
34.5.3
34.6
Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2.
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Figure 34-3. SSC Functional Block Diagram
Transmitter
Clock Output Controller
TK
MCK
Clock Divider
TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller
TX clock
Frame Sync Controller
TF
Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register
TD
APB User Interface
Load Shift
Receiver
Clock Output Controller
RK
RK Input TX Clock RF TF Start Selector
Receive Clock RX Clock Controller
Frame Sync Controller
RF
Receive Shift Register Receive Holding Register Receive Sync Holding Register
RD
RX PDC PDC Interrupt Control
Load Shift
AIC
34.6.1
Clock Management The transmitter clock can be generated by: * an external clock received on the TK I/O pad * the receiver clock * the internal clock divider The receiver clock can be generated by: * an external clock received on the RK I/O pad * the transmitter clock * the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers.
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34.6.1.1 Clock Divider
Figure 34-4. Divided Clock Block Diagram
Clock Divider SSC_CMR MCK /2
12-bit Counter
Divided Clock
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 34-5. Divided Clock Generation
Master Clock
Divided Clock DIV = 1 Divided Clock Frequency = MCK/2
Master Clock
Divided Clock DIV = 3 Divided Clock Frequency = MCK/6
Table 34-2.
Maximum MCK / 2 Minimum MCK / 8190
34.6.1.2
Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin 537
6249B-ATARM-14-Dec-06
(CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 34-6. Transmitter Clock Management
TK (pin)
MUX Receiver Clock
Tri_state Controller
Clock Output
Divider Clock CKO Data Transfer
CKS
INV MUX
Tri-state Controller
Transmitter Clock
CKI
CKG
34.6.1.3
Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results.
Figure 34-7. Receiver Clock Management
RK (pin) Tri-state Controller
MUX Transmitter Clock
Clock Output
Divider Clock CKO Data Transfer
CKS
INV MUX
Tri-state Controller
Receiver Clock
CKI
CKG
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34.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: - Master Clock divided by 2 if Receiver Frame Synchro is input - Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: - Master Clock divided by 6 if Transmit Frame Synchro is input - Master Clock divided by 2 if Transmit Frame Synchro is output 34.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See "Start" on page 540. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See "Frame Sync" on page 542. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 34-8. Transmitter Block Diagram
SSC_CR.TXEN
SSC_SR.TXEN
SSC_CR.TXDIS SSC_TFMR.DATDEF
1 RF Transmitter Clock TF SSC_TFMR.MSBF 0
SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD
Start Selector
Transmit Shift Register
SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR
0
1
SSC_TSHR
SSC_TFMR.FSLEN
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34.6.3
Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See "Start" on page 540. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See "Frame Sync" on page 542. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register.
Figure 34-9. Receiver Block Diagram
SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS
RF Receiver Clock
TF
SSC_RFMR.MSBF
SSC_RFMR.DATNB
Start Selector
Receive Shift Register
RD
SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN
SSC_RHR SSC_RFMR.DATLEN
34.6.4
Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: * Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. * Synchronously with the transmitter/receiver * On detection of a falling/rising edge on TF/RF * On detection of a low level/high level on TF/RF * On detection of a level change or an edge on TF/RF
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A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Figure 34-10. Transmit Start Mode
TK TF (Input)
Start = Low Level on TF
TD (Output) TD (Output)
X
BO
B1 STTDLY
Start = Falling Edge on TF
X
BO
B1 STTDLY X BO B1 STTDLY
Start = High Level on TF
TD (Output) TD (Output) TD (Output) TD (Output) X
Start = Rising Edge on TF
BO
B1 STTDLY
Start = Level Change on TF
X
BO
B1
BO
B1 STTDLY
Start = Any Edge on TF
X
BO
B1
BO
B1 STTDLY
Figure 34-11. Receive Pulse/Edge Start Modes
RK RF (Input)
Start = Low Level on RF
RD (Input) RD (Input)
X
BO
B1 STTDLY
Start = Falling Edge on RF
X
BO
B1 STTDLY X BO B1 STTDLY
Start = High Level on RF
RD (Input) RD (Input) RD (Input) RD (Input) X
Start = Rising Edge on RF
BO
B1 STTDLY
Start = Level Change on RF
X
BO
B1
BO
B1 STTDLY
Start = Any Edge on RF
X
BO
B1
BO
B1 STTDLY
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34.6.5
Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. * Programmable low or high levels during data transfer are supported. * Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR.
34.6.5.1
Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out.
34.6.5.2
Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 34-12. Receive Compare Modes
RK
34.6.6
RD (Input)
CMP0
CMP1
CMP2
CMP3 Start
Ignored
B0
B1
B2
FSLEN Up to 16 Bits (4 in This Example)
STDLY
DATLEN
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34.6.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: * the event that starts the data transfer (START) * the delay in number of bit periods between the start event and the first data bit (STTDLY) * the length of the data (DATLEN) * the number of data to be transferred for each start event (DATNB). * the length of synchronization transferred for each start event (FSLEN) * the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.
34.6.7
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Table 34-3.
Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR
Data Frame Registers
Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN SSC_RCMR SSC_RCMR PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay
Figure 34-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start PERIOD TF/RF
(1)
Start
FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data
From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored
TD (If FSDEN = 0) RD
DATNB
Note:
1. Example of input on falling edge of TF/RF.
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Figure 34-14. Transmit Frame Format in Continuous Mode
Start
TD
Data From SSC_THR DATLEN
Data From SSC_THR DATLEN
Default
Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR
Note:
1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.
Figure 34-15. Receive Frame Format in Continuous Mode
Start = Enable Receiver
RD
Data To SSC_RHR DATLEN
Data To SSC_RHR DATLEN
Note:
1. STTDLY is set to 0.
34.6.8
Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.
34.6.9
Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC.
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Figure 34-16. Interrupt Block Diagram
SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear
SSC Interrupt
34.7
SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.
Figure 34-17. Audio Application Block Diagram
Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER
Clock SCK Word Select WS
Data SD
MSB Left Channel
LSB
MSB Right Channel
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Figure 34-18. Codec Application Block Diagram
Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC
Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend
Serial Data In
Figure 34-19. Time Slot Application Block Diagram
SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot
CODEC Second Time Slot
Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend
Serial Data in
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34.8
Synchronous Serial Controller (SSC) User Interface
Register Mapping
Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Register Name SSC_CR SSC_CMR - - SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR - - SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR - - Access Write Read/Write - - Read/Write Read/Write Read/Write Read/Write Read Write - - Read Read/Write Read/Write Read/Write Read Write Write Read - - Reset - 0x0 - - 0x0 0x0 0x0 0x0 0x0 - - - 0x0 0x0 0x0 0x0 0x000000CC - - 0x0 - -
Table 34-4.
Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124
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34.8.1 Name: SSC Control Register SSC_CR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 TXDIS 1 RXDIS 24 - 16 - 8 TXEN 0 RXEN
Access Type:
31 - 23 - 15 SWRST 7 -
* RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. * RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception. * TXEN: Transmit Enable 0: No effect. 1: Enables Transmit if TXDIS is not set. * TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. * SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR.
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34.8.2 Name:
SSC Clock Mode Register SSC_CMR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DIV 27 - 19 - 11 26 - 18 - 10 DIV 3 2 1 0 25 - 17 - 9 24 - 16 - 8
Access Type:
31 - 23 - 15 - 7
* DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
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34.8.3 Name: SSC Receive Clock Mode Register SSC_RCMR Read/Write
30 29 28 PERIOD 23 22 21 20 STDDLY 15 - 7 CKG 14 - 6 13 - 5 CKI 12 STOP 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24
Access Type:
31
* CKS: Receive Clock Selection
CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved
* CKO: Receive Clock Output Mode Selection
CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK Pin Input-only Output Output
* CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal.
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* CKG: Receive Clock Gating Selection
CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved
* START: Receive Start Selection
START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved
* STOP: Receive Stop Selection 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. * STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. * PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
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34.8.4 Name: SSC Receive Frame Mode Register SSC_RFMR Read/Write
30 - 22 29 - 21 FSOS 13 - 5 LOOP 28
-
Access Type:
31 - 23 - 15 - 7 MSBF
27 - 19
26 - 18 FSLEN
25 - 17
24 FSEDGE 16
20
14 - 6 -
12 - 4
11
10 DATNB
9
8
3
2 DATLEN
1
0
* DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. * LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. * MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. * DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). * FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + 1 Receive Clock periods.
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* FSOS: Receive Frame Sync Output Selection
FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined
* FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection
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34.8.5 Name: SSC Transmit Clock Mode Register SSC_TCMR Read/Write
30 29 28 PERIOD 23 22 21 20 STTDLY 15 - 7 CKG 14 - 6 13 - 5 CKI 12 - 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24
Access Type:
31
* CKS: Transmit Clock Selection
CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved
* CKO: Transmit Clock Output Mode Selection
CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output
* CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal.
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* CKG: Transmit Clock Gating Selection
CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved
* START: Transmit Start Selection
START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved
* STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. * PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
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34.8.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Read/Write
30 - 22 29 - 21 FSOS 13 - 5 DATDEF 28
-
Access Type:
31 - 23 FSDEN 15 - 7 MSBF
27 - 19
26 - 18 FSLEN
25 - 17
24 FSEDGE 16
20
14 - 6 -
12 - 4
11
10 DATNB
9
8
3
2 DATLEN
1
0
* DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. * DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. * MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. * DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). * FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + 1 Transmit Clock periods.
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* FSOS: Transmit Frame Sync Output Selection
FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined
* FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. * FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register).
FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection
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34.8.7 Name: SSC Receive Holding Register SSC_RHR Read-only
30 29 28 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Access Type:
31
* RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
34.8.8 Name:
SSC Transmit Holding Register SSC_THR Write-only
30 29 28 TDAT 27 26 25 24
Access Type:
31
23
22
21
20 TDAT
19
18
17
16
15
14
13
12 TDAT
11
10
9
8
7
6
5
4 TDAT
3
2
1
0
* TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
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6249B-ATARM-14-Dec-06
34.8.9 Name:
SSC Receive Synchronization Holding Register SSC_RSHR Read-only
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RSDAT 7 6 5 4 RSDAT 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Access Type:
31 - 23 - 15
* RSDAT: Receive Synchronization Data
34.8.10 Name:
SSC Transmit Synchronization Holding Register SSC_TSHR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TSDAT 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Access Type:
31 - 23 - 15
7
6
5
4 TSDAT
3
2
1
0
* TSDAT: Transmit Synchronization Data
560
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34.8.11 Name: SSC Receive Compare 0 Register SSC_RC0R Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CP0 7 6 5 4 CP0 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Access Type:
31 - 23 - 15
* CP0: Receive Compare Data 0
561
6249B-ATARM-14-Dec-06
34.8.12 Name:
SSC Receive Compare 1 Register SSC_RC1R Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CP1 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Access Type:
31 - 23 - 15
7
6
5
4 CP1
3
2
1
0
* CP1: Receive Compare Data 1
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34.8.13 Name: SSC Status Register SSC_SR Read-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 RXEN 9 CP1 1 TXEMPTY 24 - 16 TXEN 8 CP0 0 TXRDY
Access Type:
31 - 23 - 15 - 7 RXBUFF
* TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty. * TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from TSR. 1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. * ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. * TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. * RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. * OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. * ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. * RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0.
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6249B-ATARM-14-Dec-06
* CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. * CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. * TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. * RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. * TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled. * RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled.
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34.8.14 Name: SSC Interrupt Enable Register SSC_IER Write-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY
Access Type:
31 - 23 - 15 - 7 RXBUFF
* TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. * TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. * ENDTX: End of Transmission Interrupt Enable 0: No effect. 1: Enables the End of Transmission Interrupt. * TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Buffer Empty Interrupt * RXRDY: Receive Ready Interrupt Enable 0: No effect. 1: Enables the Receive Ready Interrupt. * OVRUN: Receive Overrun Interrupt Enable 0: No effect. 1: Enables the Receive Overrun Interrupt. * ENDRX: End of Reception Interrupt Enable 0: No effect. 1: Enables the End of Reception Interrupt. * RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt.
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* CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. * CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. * TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. * RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt.
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34.8.15 Name: SSC Interrupt Disable Register SSC_IDR Write-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY
Access Type:
31 - 23 - 15 - 7 RXBUFF
* TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. * TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. * ENDTX: End of Transmission Interrupt Disable 0: No effect. 1: Disables the End of Transmission Interrupt. * TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Buffer Empty Interrupt. * RXRDY: Receive Ready Interrupt Disable 0: No effect. 1: Disables the Receive Ready Interrupt. * OVRUN: Receive Overrun Interrupt Disable 0: No effect. 1: Disables the Receive Overrun Interrupt. * ENDRX: End of Reception Interrupt Disable 0: No effect. 1: Disables the End of Reception Interrupt. * RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt.
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* CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. * CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. * TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. * RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt.
568
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34.8.16 Name: SSC Interrupt Mask Register SSC_IMR Read-only
30 - 22 - 14 - 6 ENDRX 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 RXSYN 3 TXBUFE 26 - 18 - 10 TXSYN 2 ENDTX 25 - 17 - 9 CP1 1 TXEMPTY 24 - 16 - 8 CP0 0 TXRDY
Access Type:
31 - 23 - 15 - 7 RXBUF
* TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled. * TXEMPTY: Transmit Empty Interrupt Mask 0: The Transmit Empty Interrupt is disabled. 1: The Transmit Empty Interrupt is enabled. * ENDTX: End of Transmission Interrupt Mask 0: The End of Transmission Interrupt is disabled. 1: The End of Transmission Interrupt is enabled. * TXBUFE: Transmit Buffer Empty Interrupt Mask 0: The Transmit Buffer Empty Interrupt is disabled. 1: The Transmit Buffer Empty Interrupt is enabled. * RXRDY: Receive Ready Interrupt Mask 0: The Receive Ready Interrupt is disabled. 1: The Receive Ready Interrupt is enabled. * OVRUN: Receive Overrun Interrupt Mask 0: The Receive Overrun Interrupt is disabled. 1: The Receive Overrun Interrupt is enabled. * ENDRX: End of Reception Interrupt Mask 0: The End of Reception Interrupt is disabled. 1: The End of Reception Interrupt is enabled. * RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled.
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* CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. * CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. * TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. * RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled.
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35. AC'97 Controller (AC'97C)
35.1 Description
The AC`97 Controller is the hardware implementation of the AC'97 digital controller (DC'97) compliant with AC'97 Component Specification 2.2. The AC'97 Controller communicates with an audio codec (AC'97) or a modem codec (MC'97) via the AC-link digital serial interface. All digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the AC-link protocol. The AC'97 Controller features a Peripheral DMA Controller (PDC) for audio streaming transfers. It also supports variable sampling rate and four Pulse Code Modulation (PCM) sample resolutions of 10, 16, 18 and 20 bits.
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35.2
Block Diagram
Figure 35-1. Functional Block Diagram
MCK Clock Domain Slot Number AC97 Slot Controller SYNC
Slot Number 16/20 bits Slot #0 AC97 Tag Controller Receive Shift Register Slot #0,1 AC97 CODEC Channel Transmit Shift Register Receive Shift Register SDATA_IN AC97 Channel A AC97C_CATHR AC97C_CARHR Slot #3...12 Receive Shift Register Transmit Shift Register Transmit Shift Register
M U X
Slot #1,2 SDATA_OUT
AC97C_COTHR AC97C_CORHR
Slot #2
D E
BITCLK
AC97 Channel B AC97C Interrupt AC97C_CBTHR Slot #3...12 AC97C_CBRHR Receive Shift Register Transmit Shift Register
M U X
MCK
User Interface Bit Clock Domain
APB Interface
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35.3 Pin Name List
I/O Lines Description
Pin Description 12.288-MHz bit-rate clock Receiver Data (Referred as SDATA_IN in AC-link spec) 48-KHz frame indicator and synchronizer Transmitter Data (Referred as SDATA_OUT in AC-link spec) Type Input Input Output Output
Table 35-1.
Pin Name AC97CK AC97RX AC97FS AC97TX
The AC`97 reset signal provided to the primary codec can be generated by a PIO.
35.4
Application Block Diagram
Figure 35-2. Application Block diagram
AC 97 Controller
AC-link
PIOx AC97_RESET
AC'97 Primary Codec
AC97_SYNC AC97FS AC97_BITCLK AC97CK AC97_SDATA_OUT AC97_SDATA_IN AC97RX
AC97TX
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35.5
35.5.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the AC`97 Controller receiver, the PIO controller must be configured in order for the AC97C receiver I/O lines to be in AC`97 Controller peripheral mode. Before using the AC`97 Controller transmitter, the PIO controller must be configured in order for the AC97C transmitter I/O lines to be in AC`97 Controller peripheral mode.
35.5.2
Power Management The AC`97 Controller is not continuously clocked. Its interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the AC'97 Controller clock. The AC'97 Controller has two clock domains. The first one is supplied by PMC and is equal to MCK. The second one is AC97CK which is sent by the AC97 Codec (Bit clock). Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be higher than the AC97CK (Bit Clock) clock frequency.
35.5.3
Interrupt The AC'97 Controller interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the AC97C. All AC'97 Controller interrupts can be enabled/disabled by writing to the AC'97 Controller Interrupt Enable/Disable Registers. Each pending and unmasked AC'97 Controller interrupt will assert the interrupt line. The AC'97 Controller interrupt service routine can get the interrupt source in two steps: * Reading and ANDing AC'97 Controller Interrupt Mask Register (AC97C_IMR) and AC'97 Controller Status Register (AC97C_SR). * Reading AC'97 Controller Channel x Status Register (AC97C_CxSR).
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35.6
35.6.1
Functional Description
Protocol overview AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple input and output Pulse Code Modulation PCM audio streams, as well as control register accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots.
Figure 35-3. Bidirectional AC-link Frame with Slot Assignment
Slot # AC97FS
CMD ADDR CMD DATA PCM L Front PCM R Front LINE 1 DAC PCM Center PCM L SURR PCM R SURR PCM LFE LINE 2 DAC HSET DAC IO CTRL
0
1
2
3
4
5
6
7
8
9
10
11
12
AC97TX (Controller Output)
TAG
AC97RX (Codec output)
TAG
STATUS ADDR
STATUS DATA
PCM LEFT
PCM RIGHT
LINE 1 DAC
PCM MIC
RSVED
RSVED
RSVED
LINE 2 ADC
HSET ADC
IO STATUS
Table 35-2.
Slot # 0 1 2 3,4 5 6, 7, 8 9 10 11 12
AC-link Output Slots Transmitted from the AC'97C Controller
Pin Description TAG Command Address Port Command Data Port PCM playback Left/Right Channel Modem Line 1 Output Channel PCM Center/Left Surround/Right Surround PCM LFE DAC Modem Line 2 Output Channel Modem Handset Output Channel Modem GPIO Control Channel
Table 35-3.
Slot # 0 1 2 3,4 5 6 7, 8, 9
AC-link Input Slots Transmitted from the AC'97C Controller
Pin Description TAG Status Address Port Status Data Port PCM playback Left/Right Channel Modem Line 1 ADC Dedicated Microphone ADC Vendor Reserved
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Table 35-3.
Slot # 10 11 12
AC-link Input Slots Transmitted from the AC'97C Controller
Pin Description Modem Line 2 ADC Modem Handset Input ADC Modem IO Status
35.6.1.1 Slot Description Tag Slot The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The next 12 bit positions sampled by the AC'97 Controller indicate which of the corresponding 12 time slots contain valid data. The slot's last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec. The 16-bit wide tag slot of the output frame is automatically generated by the AC`97 Controller according to the transmit request of each channel and to the SLOTREQ from the previous input frame, sent by the AC`97 Codec, in Variable Sample Rate mode. Codec Slot 1 The command/status slot is a 20-bit wide slot used to control features, and monitors status for AC`97 Codec functions. The control interface architecture supports up to sixty-four 16-bit wide read/write registers. Only the even registers are currently defined and addressed. Slot 1's bitmap is the following: * Bit 19 is for read/write command, 1= read, 0 = write. * Bits [18:12] are for control register index. * Bits [11:0] are reserved. Codec Slot 2 Slot 2 is a 20-bit wide slot used to carry 16-bit wide AC97 Codec control register data. If the current command port operation is a read, the entire slot time is stuffed with zeros. Its bitmap is the following: * Bits [19:4] are the control register data * Bits [3:0] are reserved and stuffed with zeros. Data Slots [3:12] Slots [3:12] are 20-bit wide data slots, they usually carry audio PCM or/and modem I/O data.
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35.6.2 AC`97 Controller Channel Organization The AC'97 Controller features a Codec channel and 2 logical channels; Channel A and Channel B. The Codec channel controls AC`97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. Channel A and Channel B transfer data to/from AC97 codec. All audio samples and modem data must transit by these two channels. However, Channel A is connected to PDC channels thus making it suitable for audio streaming applications. Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by either Channel A or Channel B. The slot to channel assignment is configured by two registers: * AC'97 Controller Input Channel Assignment Register (AC97C_ICA) * AC'97 Controller Output Channel Assignment Register (AC97C_OCA) The AC'97 Controller Input Channel Assignment Register (AC97C_ICA) configures the input slot to channel assignment. The AC'97 Controller Output Channel Assignment Register (AC97C_OCA) configures the output slot to channel assignment. A slot can be left unassigned to a channel by the AC'97 Controller. Slots 0, 1,and 2 cannot be assigned to Channel A or to Channel B through the AC97C_OCA and AC97C_ICA Registers. The width of sample data, that transit via Channel A and Channel B varies and can take one of these values; 10, 16, 18 or 20 bits. Figure 35-4. Logical Channel Assignment
Slot # AC97FS 0 1 2 3 4 5 6 7 8 9 10 11 12
AC97TX (Controller Output)
TAG
CMD ADDR
CMD DATA
PCM L Front
PCM R Front
LINE 1 DAC
PCM Center
PCM L SURR
PCM R SURR
PCM LFE
LINE 2 DAC
HSET DAC
IO CTRL
Codec Channel
Channel A
AC97C_OCA = 0x0000_0209
AC97RX (Codec output)
TAG
STATUS ADDR
STATUS DATA
PCM LEFT
PCM RIGHT
LINE 1 DAC
PCM MIC
RSVED
RSVED
RSVED
LINE 2 ADC
HSET ADC
IO STATUS
Codec Channel AC97C_ICA = 0x0000_0009
Channel A
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35.6.2.1
AC97 Controller Setup The following operations must be performed in order to bring the AC'97 Controller into an operating state: 1. Enable the AC97 Controller clock in the PMC controller. 2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (AC97C_MR). 3. Configure the input channel assignment by controlling the AC'97 Controller Input Assignment Register (AC97C_ICA). 4. Configure the output channel assignment by controlling the AC'97 Controller Input Assignment Register (AC97C_OCA). 5. Configure sample width for Channel A and Channel B by writing the SIZE bit field in AC97C Channel A Mode Register (AC97C_CAMR) and AC97C Channel B Mode Register (AC97C_CBMR). The application can write 10, 16, 18,or 20-bit wide PCM samples through the AC'97 interface and they will be transferred into 20-bit wide slots. 6. Configure data Endianness for Channel A and Channel B by writing CEM bit field in AC97C_CAMR and AC97C_CBMR registers. Data on the AC-link are shifted MSB first. The application can write little- or big-endian data to the AC'97 Controller interface. 7. Configure the PIO controller to drive the RESET signal of the external Codec. The RESET signal must fulfill external AC97 Codec timing requirements. 8. Enable Channel A and/or Channel B by writing CEN bit field in AC97C_CAMR and AC97C_CBMR registers.
35.6.2.2
Transmit Operation The application must perform the following steps in order to send data via a channel to the AC97 Codec: * Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status Register (AC97_CxSR). x being one of the 2 channels. * Write data to the AC'97 Controller Channel x Transmit Holding Register (AC97C_CxTHR). Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically set by the AC'97 Controller which allows the application to start a new write action. The application can also wait for an interrupt notice associated with TXRDY in order to send data. The interrupt remains active until TXRDY flag is cleared..
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Figure 35-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x
Slot # AC97FS AC97TX (Controller Output)
TAG CMD ADDR CMD DATA PCM L Front PCM R Front LINE 1 DAC PCM Center PCM L SURR PCM R SURR PCM LFE LINE 2 DAC HSET DAC IO CTRL
0
1
2
3
4
5
6
7
8
9
10
11
12
TXRDYCx (AC97C_SR)
TXEMPTY (AC97C_SR) Write access to AC97C_THRx
PCM L Front transfered to the shift register PCM R Front transfered to the shift register
The TXEMPTY flag in the AC'97 Controller Channel x Status Register (AC97C_CxSR) is set when all requested transmissions for a channel have been shifted on the AC-link. The application can either poll TXEMPTY flag in AC97C_CxSR or wait for an interrupt notice associated with the same flag. In most cases, the AC'97 Controller is embedded in chips that target audio player devices. In such cases, the AC`97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating system. In order to avoid these polling drawbacks, the application can perform audio streams by using PDC connected to channel A, which reduces processor overhead and increases performance especially under an operating system. The PDC transmit counter values must be equal to the number of PCM samples to be transmitted, each sample goes in one slot. 35.6.2.3 AC`97 Output Frame The AC'97 Controller outputs a thirteen-slot frame on the AC-Link. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application performs control and status monitoring actions on AC97 Codec control/status registers. Slots [3:12] are used according to the content of the AC'97 Controller Output Channel Assignment Register (AC97C_OCA). If the application performs many transmit requests on a channel, some of the slots associated to this channel or all of them will carry valid data. Receive Operation The AC'97 Controller can also receive data from AC`97 Codec. Data is received in the channel's shift register and then transferred to the AC'97 Controller Channel x Read Holding Register. To read the newly received data, the application must perform the following steps: * Poll RXRDY flag in AC'97 Controller Channel x Status Register (AC97C_CxSR). x being one of the 2 channels. * Read data from AC'97 Controller Channel x Read Holding Register.
35.6.2.4
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The application can also wait for an interrupt notice in order to read data from AC97C_CxRHR. The interrupt remains active until RXRDY is cleared by reading AC97C_CxSR. The RXRDY flag in AC97C_CxSR is set automatically when data is received in the Channel x shift register. Data is then shifted to AC97C_CxRHR. Figure 35-6. Audio Transfer (PCM L Front, PCM R Front) on Channel x
Slot # AC97FS
STATUS ADDR STATUS DATA PCM LEFT PCM RIGHT LINE 1 DAC PCM MIC LINE 2 ADC HSET ADC IO STATUS
0
1
2
3
4
5
6
7
8
9
10
11
12
AC97RX (Codec output) RXRDYCx (AC97C_SR) Read access to AC97C_RHRx
TAG
RSVED
RSVED
RSVED
If the previously received data has not been read by the application, the new data overwrites the data already waiting in AC97C_CxRHR, therefore the OVRUN flag in AC97C_CxSR is raised. The application can either poll the OVRUN flag in AC97C_CxSR or wait for an interrupt notice. The interrupt remains active until the OVRUN flag in AC97C_CxSR is set. The AC'97 Controller can also be used in sound recording devices in association with an AC97 Codec. The AC`97 Controller may also be exposed to heavy PCM transfers. The application can usethe PDC connected to channel A in order to reduce processor overhead and increase performance especially under an operating system. The PDC receive counter values must be equal to the number of PCM samples to be received, each sample goes in one slot. 35.6.2.5 AC`97 Input Frame The AC'97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used according to AC'97 Controller Output Channel Assignment Register (AC97C_ICA) content. The AC'97 Controller will not receive any data from any slot if AC97C_ICA is not assigned to a channel in input. Configuring and Using Interrupts Instead of polling flags in AC'97 Controller Global Status Register (AC97C_SR) and in AC'97 Controller Channel x Status Register (AC97C_CxSR), the application can wait for an interrupt notice. The following steps show how to configure and use interrupts correctly: * Set the interruptible flag in AC'97 Controller Channel x Mode Register (AC97C_CxMR). * Set the interruptible event and channel event in AC'97 Controller Interrupt Enable Register (AC97C_IER). The interrupt handler must read both AC'97 Controller Global Status Register (AC97C_SR) and AC'97 Controller Interrupt Mask Register (AC97C_IMR) and AND them to get the real interrupt source. Furthermore, to get which event was activated, the interrupt handler has to
35.6.2.6
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read AC'97 Controller Channel x Status Register (AC97C_CxSR), x being the channel whose event triggers the interrupt. The application can disable event interrupts by writing in AC'97 Controller Interrupt Disable Register (AC97C_IDR). The AC`97 Controller Interrupt Mask Register (AC97C_IMR) shows which event can trigger an interrupt and which one cannot. 35.6.2.7 Endianness Endianness can be managed automatically for each channel, except for the Codec channel, by writing to Channel Endianness Mode (CEM) in AC97C_CxMR. This enables transferring data on AC-link in Big Endian format without any additional operation. To Transmit a Word Stored in Big Endian Format on AC-link Word to be written in AC'97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (as it is stored in memory or microprocessor register).
31 Byte0[7:0] 24 23 Byte1[7:0] 16 15 Byte2[7:0] 8 7 Byte3[7:0] 0
Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit).
31 - 24 23 - 20 19 16 Byte2[3:0] 15 Byte1[7:0] 8 7 Byte0[7:0] 0
Data transmitted on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}. To Transmit A Halfword Stored in Big Indian Format on AC-link Halfword to be written in AC'97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
31 - 24 23 - 16 15 Byte0[7:0] 8 7 Byte1[7:0] 0
Halfword stored in AC'97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit).
31 - 24 23 - 16 15 Byte1[7:0] 8 7 Byte0[7:0] 0
Data emitted on related slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}. To Transmit a10-bit Sample Stored in Big Endian Format on AC-link Halfword to be written in AC'97 Controller Channel x Transmit Holding Register (AC97C_CxTHR).
31 - 24 23 - 16 15 Byte0[7:0] 8 7 {0x00, Byte1[1:0]} 0
Halfword stored in AC'97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit).
31 - 24 23 - 16 15 - 10 9 8 Byte1 [1:0] 7 Byte0[7:0] 0
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6249B-ATARM-14-Dec-06
Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}. To Receive Word transfers Data received on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}. Word stored in AC'97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data).
31 - 24 23 - 20 19 16 Byte2[3:0] 15 Byte1[7:0] 8 7 Byte0[7:0] 0
Data is read from AC'97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when Channel x data size is greater than 16 bits and when big-endian mode is enabled (data written to memory).
31 Byte0[7:0] 24 23 Byte1[7:0] 16 15 {0x0, Byte2[3:0]} 8 7 0x00 0
To Receive Halfword Transfers Data received on appropriate slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}. Halfword stored in AC'97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data).
31 - 24 23 - 16 15 Byte1[7:0] 8 7 Byte0[7:0] 0
Data is read from AC'97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when data size is equal to 16 bits and when big-endian mode is enabled.
31 - 24 23 - 16 15 Byte0[7:0] 8 7 Byte1[7:0] 0
To Receive 10-bit Samples Data received on appropriate slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.Halfword stored in AC'97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data)
31 - 24 23 - 16 15 - 10 9 8 Byte1 [1:0] 7 Byte0[7:0] 0
Data read from AC'97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when data size is equal to 10 bits and when big-endian mode is enabled.
31 - 24 23 - 16 15 Byte0[7:0] 8 7 0x00 3 1 0 Byte1 [1:0]
35.6.3
Variable Sample Rate The problem of variable sample rate can be summarized by a simple example. When passing a 44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. The new AC'97 standard approach calls for the addition of "on-demand" slot request flags. The AC`97 Codec examines its sample rate control register, the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output
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frame and then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97 Codec to the AC'97 Controller in slot 1/SLOTREQ in every audio input frame. Each time the AC`97 controller sees one or more of the newly defined slot request flags set active (low) in a given audio input frame, it must pass along the next PCM sample for the corresponding slot(s) in the AC-link output frame that immediately follows. The variable Sample Rate mode is enabled by performing the following steps: * Setting the VRA bit in the AC'97 Controller Mode Register (AC97C_MR). * Enable Variable Rate mode in the AC`97 Codec by performing a transfer on the Codec channel. Slot 1 of the input frame is automatically interpreted as SLOTREQ signaling bits. The AC'97 Controller will automatically fill the active slots according to both SLOTREQ and AC97C_OCA register in the next transmitted frame. 35.6.4 35.6.4.1 Power Management Powering Down the AC-Link The AC97 Codecs can be placed in low power mode. The application can bring AC97 Codec to a power down state by performing sequential writes to AC97 Codec powerdown register . Both the bit clock (clock delivered by AC97 Codec, AC97CK) and the input line (AC97RX) are held at a logic low voltage level. This puts AC97 Codec in power down state while all its registers are still holding current values. Without the bit clock, the AC-link is completely in a power down state. The AC'97 Controller should not attempt to play or capture audio data until it has awakened AC97 Codec. To set the AC'97 Codec in low power mode, the PR4 bit in the AC'97 Codec powerdown register (Codec address 0x26) must be set to 1. Then the primary Codec drives both AC97CK and AC97RX to a low logic voltage level. The following operations must be done to put AC97 Codec in low power mode: * Disable Channel A clearing CEN in the AC97C_CAMR register. * Disable Channel B clearing CEN field in the AC97C_CBMR register. * Write 0x2680 value in the AC97C_COTHR register. * Poll the TXEMPTY flag in AC97C_CxSR registers for the 2 channels. At this point AC97 Codec is in low power mode. 35.6.4.2 Waking up the AC-link There are two methods to bring the AC-link out of low power mode. Regardless of the method, it is always the AC97 Controller that performs the wake-up.
Wake-up Tiggered by the AC'97 Controller The AC'97 Controller can wake up the AC97 Codec by issuing either a cold or a warm reset. The AC'97 Controller can also wake up the AC97 Codec by asserting AC97FS signal, however this action should not be performed for a minimum period of four audio frames following the frame in which the powerdown was issued. Wake-up Triggered by the AC97 Codec
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This feature is implemented in AC97 modem codecs that need to report events such as CallerID and wake-up on ring. The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously (regarding AC97FS) detected by the AC'97 Controller. If WKUP bit is enabled in AC97C_IMR register, an interrupt is triggered that wakes up the AC`97 Controller which should then immediately issue a cold or a warm reset. If the processor needs to be awakened by an external event, the AC97RX signal must be externally connected to the WAKEUP entry of the system controller. Figure 35-7. AC'97 Power-Down/Up Sequence
Wake Event Power Down Frame AC97CK Sleep State Warm Reset New Audio Frame
AC97FS
AC97TX
TAG
Write to 0x26
Data PR4
TAG
Slot1
Slot2
AC97RX
TAG
Write to 0x26
Data PR4
TAG
Slot1
Slot2
35.6.4.3
AC97 Codec Reset There are three ways to reset an AC97 Codec.
Cold AC'97 Reset A cold reset is generated by asserting the RESET signal low for the minimum specified time (depending on the AC97 Codec) and then by de-asserting RESET high. AC97CK and AC97FS is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers on AC-link can resume. The RESET signal will be controlled via a PIO line. This is how an application should perform a cold reset: * Clear and set ENA flag in the AC97C_MR register to reset the AC'97 Controller * Clear PIO line output controlling the AC'97 RESET signal * Wait for the minimum specified time * Set PIO line output controlling the AC'97 RESET signal AC97CK, the clock provided by AC97 Codec, is detected by the controller. Warm AC'97 Reset A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is signaled by driving AC97FX signal high for a minimum of 1us in the absence of AC97CK. In the absence of AC97CK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to signal a warm reset to AC97 Codec. This is the right way to perform a warm reset: * Set WRST in the AC97C_MR register.
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* Wait for at least 1 us * Clear WRST in the AC97C_MR register. The application can check that operations have resumed by checking SOF flag in the AC97C_SR register or wait for an interrupt notice if SOF is enabled in AC97C_IMR.
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35.7
AC'97 Controller (AC97C) User Interface
Register Mapping
Register Reserved Mode Register Reserved Input Channel Assignment Register Output Channel Assignment Register Reserved Channel A Receive Holding Register Channel A Transmit Holding Register Channel A Status Register Channel A Mode Register Channel B Receive Holding Register Channel B Transmit Holding Register Channel B Status Register Channel B Mode Register Codec Receive Holding Register Codec Transmit Holding Register Codec Status Register Codec Mode Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Register Name - AC97C_MR - AC97C_ICA AC97C_OCA - AC97C_CARHR AC97C_CATHR AC97C_CASR AC97C_CAMR AC97C_CBRHR AC97C_CBTHR AC97C_CBSR AC97C_CBMR AC97C_CORHR AC'97C_COTHR AC'97C_COSR AC'97C_COMR AC97C_SR AC97C_IER AC97C_IDR AC97C_IMR - AC97C_CARPR, AC97C_CARCR, AC97C_CATPR, AC97C_CATCR, AC97C_CARNPR, AC97C_CARNCR, AC97C_CATNPR, AC97C_CATNCR, AC97C_CAPTCR, AC97C_CAPTSR Access - Read/Write - Read/Write Read/Write - Read Write Read Read/Write Read Write Read Read/Write Read Write Read Read/Write Read Write Write Read - Reset - 0x0 - 0x0 0x0 - 0x0 - 0x0 0x0 0x0 - 0x0 0x0 0x0 - 0x0 0x0 0x0 - - 0x0 -
Table 35-4.
Offset 0x0-0x4 0x8 0xC 0x10 0x14 0x18-0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60-0xFB
0x100- 0x124
Reserved for Peripheral Data Controller (PDC), registers related to Channel A transfers
-
-
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35.7.1 Name: Access Type:
31 - 23 - 15 - 7 -
AC'97 Controller Mode Register AC97C_MR Read-Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 VRA 25 - 17 - 9 - 1 WRST 24 - 16 - 8 - 0 ENA
* VRA: Variable Rate (for Data Slots 3-12) 0: Variable Rate is inactive. (48 KHz only) 1: Variable Rate is active. * WRST: Warm Reset 0: Warm Reset is inactive. 1: Warm Reset is active. * ENA: AC'97 Controller Global Enable 0: No effect. AC'97 function as well as access to other AC'97 Controller registers are disabled. 1: Activates the AC'97 function. 35.7.2 AC'97 Controller Input Channel Assignment Register AC97C_ICA Read/Write
30 - 22 CHID10 14 6 CHID5 29 21 13 CHID7 5 28 CHID12 20 12 4 CHID4 27 19 CHID9 11 3 26 18 10 CHID6 2 25 CHID11 17 CHID8 9 1 CHID3 8 CHID5 0 24 16
Register Name: Access Type:
31 - 23 15 CHID8 7
* CHIDx: Channel ID for the input slot x
CHIDx 0x0 0x1 0x2 Selected Receive Channel None. No data will be received during this Slot x Channel A data will be received during this slot time. Channel B data will be received during this slot time
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35.7.3
AC'97 Controller Output Channel Assignment Register AC97C_OCA Read/Write
30 - 22 CHID10 14 6 CHID5 29 21 13 CHID7 5 28 CHID12 20 12 4 CHID4 27 19 CHID9 11 3 26 18 10 CHID6 2 25 CHID11 17 CHID8 9 1 CHID3 8 CHID5 0 24 16
Register Name: Access Type:
31 - 23 15 CHID8 7
* CHIDx: Channel ID for the output slot x
CHIDx 0x0 0x1 0x2 Selected Transmit Channel None. No data will be transmitted during this Slot x Channel A data will be transferred during this slot time. Channel B data will be transferred during this slot time
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35.7.4 AC'97 Controller Codec Channel Receive Holding Register AC97C_CORHR Read-only
30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 SDATA 7 4 SDATA 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* SDATA: Status Data Data sent by the CODEC in the third AC'97 input frame slot (Slot 2).
35.7.5
AC'97 Controller Codec Channel Transmit Holding Register AC97C_COTHR Write-only
30 - 22 14 6 29 - 21 13 5 28 - 20 12 CDATA 7 4 CDATA 3 2 1 0 27 - 19 CADDR 11 26 - 18 10 25 - 17 9 24 - 16 8
Register Name: Access Type:
31 - 23 READ 15
* READ: Read/Write command 0: Write operation to the CODEC register indexed by the CADDR address. 1: Read operation to the CODEC register indexed by the CADDR address. This flag is sent during the second AC'97 frame slot * CADDR: CODEC control register index Data sent to the CODEC in the second AC'97 frame slot. * CDATA: Command Data Data sent to the CODEC in the third AC'97 frame slot (Slot 2).
591
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35.7.6
AC'97 Controller Channel A, Channel B Receive Holding Register AC97C_CARHR, AC97C_CBRHR Read-only
30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 RDATA 7 4 RDATA 3 2 1 0 27 - 19 11 26 - 18 RDATA 10 9 8 25 - 17 24 - 16
Register Name: Access Type:
31 - 23 - 15
* RDATA: Receive Data Received Data on channel x.
35.7.7
AC'97 Controller Channel A, Channel B Transmit Holding Register AC97C_CATHR, AC97C_CBTHR Write-only
30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 TDATA 7 4 TDATA 3 2 1 0 27 - 19 11 26 - 18 TDATA 10 9 8 25 - 17 24 - 16
Register Name: Access Type:
31 - 23 - 15
* TDATA: Transmit Data Data to be sent on channel x.
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35.7.8 AC'97 Controller Channel A Status Register AC97C_CASR Read-only
30 - 22 - 14 ENDRX 6 - 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 TXBUFE 3 - 26 - 18 - 10 ENDTX 2 UNRUN 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY
Register Name: Access Type:
31 - 23 - 15 RXBUFF 7 -
35.7.9
AC'97 Controller Channel B Status Register AC97C_CBSR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 UNRUN 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY
Register Name: Access Type:
31 - 23 - 15 - 7 -
35.7.10
AC'97 Controller Codec Channel Status Register AC97C_COSR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 UNRUN 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty. * TXEMPTY: Channel Transmit Empty 0: Data remains in the Channel Transmit Register or is currently transmitted from the Channel Transmit Shift Register. 1: Data in the Channel Transmit Register have been loaded in the Channel Transmit Shift Register and sent to the codec. * UNRUN: Transmit Underrun Active only when Variable Rate Mode is enabled (VRA bit set in the AC97C_MR register). Automatically cleared by a processor read operation. 0: No data has been requested from the channel since the last read of the Status Register, or data has been available each time the CODEC requested new data from the channel since the last read of the Status Register. 593
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1: Data has been emitted while no valid data to send has been previously loaded into the Channel Transmit Shift Register since the last read of the Status Register. * RXRDY: Channel Receive Ready 0: Channel Receive Holding Register is empty. 1: Data has been received and loaded in Channel Receive Holding Register. * OVRUN: Receive Overrun Automatically cleared by a processor read operation. 0: No data has been loaded in the Channel Receive Holding Register while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in the Channel Receive Holding Register while previous data has not yet been read since the last read of the Status Register. * ENDRX: End of Reception for Channel x 0: The register AC97C_CxRCR has not reached 0 since the last write in AC97C_CxRCR or AC97C_CxRNCR. 1: The register AC97C_CxRCR has reached 0 since the last write in AC97C_CxRCR or AC97C_CxRNCR. * RXBUFF: Receive Buffer Full for Channel x 0: AC97C_CxRCR or AC97C_CxRNCR have a value other than 0. 1: Both AC97C_CxRCR and AC97C_CxRNCR have a value of 0. * ENDTX: End of Transmission for Channel x 0: The register AC97C_CxTCR has not reached 0 since the last write in AC97C_CxTCR or AC97C_CxNCR. 1: The register AC97C_CxTCR has reached 0 since the last write in AC97C_CxTCR or AC97C_CxTNCR. * TXBUFE: Transmit Buffer Empty for Channel x 0: AC97C_CxTCR or AC97C_CxTNCR have a value other than 0. 1: Both AC97C_CxTCR and AC97C_CxTNCR have a value of 0.
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35.7.11 AC'97 Controller Channel A Mode Register AC97C_CAMR Read/Write
30 - 22 PDCEN 14 ENDRX 6 - 29 - 21 CEN 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 TXBUFE 3 - 26 - 18 CEM 10 ENDTX 2 UNRUN 25 - 17 SIZE 9 - 1 TXEMPTY 8 - 0 TXRDY 24 - 16
Register Name: Access Type:
31 - 23 - 15 RXBUFF 7 -
35.7.12
AC'97 Controller Channel B Mode Register AC97C_CBMR Read/Write
30 - 22 - 14 - 6 - 29 - 21 CEN 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 - 3 - 26 - 18 CEM 10 - 2 UNRUN 25 - 17 SIZE 9 - 1 TXEMPTY 8 - 0 TXRDY 24 - 16
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CEM: Channel x Endian Mode 0: Transferring data through Channel x is straightforward (Little-endian). 1: Transferring data through Channel x from/to a memory is performed with from/to Big-endian format translation. * SIZE: Channel x Data Size SIZE Encoding
SIZE 0x0 0x1 0x2 0x3 Note: Selected Channel 20 bits 18bits 16 bits 10 bits
Each time slot in the data phase is 20 bits long. For example, if a 16-bit sample stream is being played to an AC97 DAC, the first 16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC'97 Controller fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the implemented DAC's resolution (16-, 18-, or 20-bit).
* CEN: Channel x Enable 0: Data transfer is disabled on Channel x. 1: Data transfer is enabled on Channel x. * PDCCEN: Peripheral Data Controller Channel Enable 0: Channel x is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated. 1: Channel x is transferred through a Peripheral Data Controller Channel. Related PDC flags are taken into account or generated. 595
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35.7.13
AC'97 Controller Codec Channel Mode Register AC97C_COMR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 OVRUN 28 - 20 - 12 - 4 RXRDY 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 UNRUN 25 - 17 - 9 - 1 TXEMPTY 24 - 16 - 8 - 0 TXRDY
Register Name: Access Type:
31 - 23 - 15 - 7 -
* TXRDY: Channel Transmit Ready Interrupt Enable * TXEMPTY: Channel Transmit Empty Interrupt Enable * UNRUN: Transmit Underrun Interrupt Enable * RXRDY: Channel Receive Ready Interrupt Enable * OVRUN: Receive Overrun Interrupt Enable * ENDRX: End of Reception for channel x Interrupt Enable * RXBUFF: Receive Buffer Full for channel x Interrupt Enable * ENDTX: End of Transmission for channel x Interrupt Enable * TXBUFE: Transmit Buffer Empty for channel x Interrupt Enable 0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt. 1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt.
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35.7.14 AC'97 Controller Status Register AC97C_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CBEVT 27 - 19 - 11 - 3 CAEVT 26 - 18 - 10 - 2 COEVT 25 - 17 - 9 - 1 WKUP 24 - 16 - 8 - 0 SOF
Register Name: Access Type:
31 - 23 - 15 - 7 -
WKUP and SOF flags in AC97C_SR register are automatically cleared by a processor read operation. * SOF: Start Of Frame 0: No Start of Frame has been detected since the last read of the Status Register. 1: At least one Start of frame has been detected since the last read of the Status Register. * WKUP: Wake Up detection 0: No Wake-up has been detected. 1: At least one rising edge on SDATA_IN has been asynchronously detected. That means AC'97 Codec has notified a wake-up. * COEVT: CODEC Channel Event A Codec channel event occurs when AC97C_COSR AND AC97C_COMR is not 0. COEVT flag is automatically cleared when the channel event condition is cleared. 0: No event on the CODEC channel has been detected since the last read of the Status Register. 1: At least one event on the CODEC channel is active. * CAEVT: Channel A Event A channel A event occurs when AC97C_CASR AND AC97C_CAMR is not 0. CAEVT flag is automatically cleared when the channel event condition is cleared. 0: No event on the channel A has been detected since the last read of the Status Register. 1: At least one event on the channel A is active. * CBEVT: Channel B Event A channel B event occurs when AC97C_CBSR AND AC97C_CBMR is not 0. CBEVT flag is automatically cleared when the channel event condition is cleared. 0: No event on the channel B has been detected since the last read of the Status Register. 1: At least one event on the channel B is active.
597
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35.7.15
AC'97 Controller Interrupt Enable Register AC97C_IER Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 CBEVT 27 - 19 - 11 - 3 CAEVT 26 - 18 - 10 - 2 COEVT 25 - 17 - 9 - 1 WKUP 24 - 16 - 8 - 0 SOF
Register Name: Access Type:
31 - 23 - 15 - 7 -
* SOF: Start Of Frame * WKUP: Wake Up * COEVT: Codec Event * CAEVT: Channel A Event * CBEVT: Channel B Event 0: No effect. 1: Enables the corresponding interrupt.
35.7.16
AC'97 Controller Interrupt Disable Register AC97C_IDR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 CBEVT 27 - 19 - 11 - 3 CAEVT 26 - 18 - 10 - 2 COEVT 25 - 17 - 9 - 1 WKUP 24 - 16 - 8 - 0 SOF
Register Name: Access Type:
31 - 23 - 15 - 7 -
* SOF: Start Of Frame * WKUP: Wake Up * COEVT: Codec Event * CAEVT: Channel A Event * CBEVT: Channel B Event 0: No effect. 1: Disables the corresponding interrupt.
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35.7.17 AC'97 Controller Interrupt Mask Register AC97C_IMR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 CBEVT 27 - 19 - 11 - 3 CAEVT 26 - 18 - 10 - 2 COEVT 25 - 17 - 9 - 1 WKUP 24 - 16 - 8 - 0 SOF
Register Name: Access Type:
31 - 23 - 15 - 7 -
* SOF: Start Of Frame * WKUP: Wake Up * COEVT: Codec Event * CAEVT: Channel A Event * CBEVT: Channel B Event 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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36. Timer Counter (TC)
36.1 Description
The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 36-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2
Table 36-1.
Name
Timer Counter Clock Assignment
Definition MCK/2 MCK/8 MCK/32 MCK/128 SLCK
TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5
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36.2
Block Diagram
Figure 36-1. Timer Counter Block Diagram
Parallel I/O Controller TCLK0
TIMER_CLOCK2
TIMER_CLOCK1
TIOA1
TIMER_CLOCK3
TCLK0 TCLK1 TCLK2 TIOA0 TIOB0
TIOA2 TCLK1
XC0 XC1 XC2 TC0XC0S
Timer/Counter Channel 0
TIOA
TIOA0
TIOB
TIMER_CLOCK4 TIMER_CLOCK5
TCLK2
TIOB0
SYNC
INT0
TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S
SYNC
Timer/Counter Channel 1
TIOA
TIOA1
TIOB
TIOB1 INT1
TIOA1 TIOB1
TCLK0 TCLK1 TCLK2 TIOA0 TIOA1
XC0 XC1 XC2 TC2XC2S
Timer/Counter Channel 2
TIOA
TIOA2
TIOB
TIOB2
SYNC
TIOA2 TIOB2
INT2
Timer Counter Advanced Interrupt Controller
Table 36-2.
Signal Name Description
Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal
Block/Channel
Channel Signal
TIOB INT SYNC
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36.3 Pin Name List
Table 36-3.
Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2
TC Pin List
Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O
36.4
36.4.1
Product Dependencies
I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions.
36.4.2
Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC.
36.4.3
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36.5
36.5.1
Functional Description
TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 36-5 on page 617. 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock.
36.5.2
36.5.3
Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 36-2 on page 605. Each channel can independently select an internal or external clock source for its counter: * Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 * External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 36-3 on page 605
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock
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Figure 36-2. Clock Chaining Selection
TC0XC0S Timer/Counter Channel 0 TIOA1 TIOA2 XC0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 TIOA0
TCLK0
SYNC
TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA0 TIOA2 XC0 = TCLK2 XC1 XC2 = TCLK2 TIOB1 TIOA1
SYNC
TC2XC2S
Timer/Counter Channel 2 XC0 = TCLK0 TIOA2
TCLK2 TIOA0 TIOA1
XC1 = TCLK1 XC2 TIOB2
SYNC
Figure 36-3. Clock Selection
TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI
Selected Clock
BURST
1
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36.5.4
Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 36-4. * The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. * The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Figure 36-4. Clock Control
Selected Clock Trigger
CLKSTA
CLKEN
CLKDIS
Q Q S R
S R
Counter Clock
Stop Event
Disable Event
36.5.5
TC Operating Modes Each channel can independently operate in two different modes: * Capture Mode provides measurement on signals. * Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger.
36.5.6
Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes:
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* Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. * SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. * Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 36.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 36-5 shows the configuration of the TC channel when programmed in Capture Mode. 36.5.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 36.5.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
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Figure 36-5. Capture Mode
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TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 LDBSTOP BURST Register C Capture Register A SWTRG CLK RESET SYNC Trig ABETRG ETRGEDG MTIOB Edge Detector LDRA Edge Detector If RA is Loaded LDRB Edge Detector
TC1_SR
CLKI
CLKSTA
CLKEN
CLKDIS
Q Q S R
S R
LDBDIS
1 16-bit Counter OVF
Capture Register B
Compare RC =
CPCTRG
TIOB
ETRGS
COVFS
LOVRS
LDRAS
LDRBS
CPCS
MTIOA If RA is not loaded or RB is Loaded
TC1_IMR
TIOA
Timer/Counter Channel
INT
AT91SAM9263 Preliminary
36.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 36-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 36.5.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
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Figure 36-6. Waveform Mode
TIMER_CLOCK5 XC0 XC1 XC2
Q
S R
CPCSTOP
Output Controller
WAVSEL EEVT BEEVT EEVTEDG Edge Detector TIOB TC1_IMR TC1_SR ENETRG ETRGS COVFS CPCS CPAS CPBS
Output Controller
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SYNC
TCCLKS CLKSTA TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 CLKI CLKEN CLKDIS ACPC
Q
S
CPCDIS
R
ACPA
MTIOA
AEEVT
TIOA
BURST WAVSEL
Register A
Register B
Register C ASWTRG
1
16-bit Counter
CLK RESET OVF
Compare RA =
Compare RB =
Compare RC =
SWTRG
BCPC Trig BCPB MTIOB
TIOB
BSWTRG
Timer/Counter Channel
INT
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36.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 36-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 36-7. WAVSEL= 00 without trigger
Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
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Figure 36-8. WAVSEL= 00 with trigger
Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
36.5.11.2
WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 36-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR).
Figure 36-9. WAVSEL = 10 Without Trigger
Counter Value 0xFFFF Counter cleared by compare match with RC RC RB
RA
Waveform Examples TIOB
Time
TIOA
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Figure 36-10. WAVSEL = 10 With Trigger
Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger
RA
Waveform Examples TIOB
Time
TIOA
36.5.11.3
WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
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Figure 36-11. WAVSEL = 01 Without Trigger
Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 36-12. WAVSEL = 01 With Trigger
Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF
Counter incremented by trigger
RA
Waveform Examples TIOB
Time
TIOA
36.5.11.4
WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
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Figure 36-13. WAVSEL = 11 Without Trigger
Counter Value 0xFFFF Counter decremented by compare match with RC RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 36-14. WAVSEL = 11 With Trigger
Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger
RA
Waveform Examples TIOB
Time
TIOA
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36.5.12
External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL.
36.5.13
Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.
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36.6 Timer Counter (TC) User Interface
TC Global Memory Map
Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 36-5 See Table 36-5 See Table 36-5 Write-only Read/Write - 0 Reset Value
Table 36-4.
Offset 0x00 0x40 0x80 0xC0 0xC4
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 36-5. The offset of each of the channel registers in Table 36-5 is in relation to the offset of the corresponding channel as mentioned in Table 36-5.
Table 36-5.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0xFC Notes:
TC Channel Memory Map
Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR - Read-only Read/Write(1) Read/Write
(1)
Name TC_CCR TC_CMR
Access Write-only Read/Write
Reset Value - 0 - - 0 0 0 0 0 - - 0 -
Read/Write Read-only Write-only Write-only Read-only -
1. Read-only if WAVE = 0
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36.6.1 TC Block Control Register Register Name: TC_BCR Access Type:
31 - 23 - 15 - 7 -
Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 SYNC
* SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
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36.6.2 TC Block Mode Register Register Name: TC_BMR Access Type:
31 - 23 - 15 - 7 -
Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 TC2XC2S 28 - 20 - 12 - 4 27 - 19 - 11 - 3 TCXC1S 26 - 18 - 10 - 2 25 - 17 - 9 - 1 TC0XC0S 24 - 16 - 8 - 0
* TC0XC0S: External Clock Signal 0 Selection
TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2
* TC1XC1S: External Clock Signal 1 Selection
TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2
* TC2XC2S: External Clock Signal 2 Selection
TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1
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36.6.3 TC Channel Control Register Register Name: TC_CCR Access Type:
31 - 23 - 15 - 7 -
Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SWTRG 25 - 17 - 9 - 1 CLKDIS 24 - 16 - 8 - 0 CLKEN
* CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. * CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. * SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started.
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36.6.4 TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type:
31 - 23 - 15 WAVE = 0 7 LDBDIS
Read/Write
30 - 22 - 14 CPCTRG 6 LDBSTOP 29 - 21 - 13 - 5 BURST 28 - 20 - 12 - 4 11 - 3 CLKI 27 - 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 - 18 25 - 17 LDRA 8 24 - 16
* TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2
* CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
* LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. * LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs.
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* ETRGEDG: External Trigger Edge Selection
ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge
* ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. * CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. * WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). * LDRA: RA Loading Selection
LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA
* LDRB: RB Loading Selection
LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA
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36.6.5 TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type:
31 BSWTRG 23 ASWTRG 15 WAVE = 1 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS
Read/Write
30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24
* TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2
* CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. * BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
* CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. * CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC.
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* EEVTEDG: External Event Edge Selection
EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge
* EEVT: External Event Selection
EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input (1) output output output
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
* ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. * WAVSEL: Waveform Selection
WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare
* WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. * ACPA: RA Compare Effect on TIOA
ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle
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* ACPC: RC Compare Effect on TIOA
ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle
* AEEVT: External Event Effect on TIOA
AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle
* ASWTRG: Software Trigger Effect on TIOA
ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle
* BCPB: RB Compare Effect on TIOB
BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle
* BCPC: RC Compare Effect on TIOB
BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle
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* BEEVT: External Event Effect on TIOB
BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle
* BSWTRG: Software Trigger Effect on TIOB
BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle
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36.6.6 TC Counter Value Register Register Name: TC_CV Access Type:
31 - 23 - 15
Read-only
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 CV 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 CV
3
2
1
0
* CV: Counter Value CV contains the counter value in real time.
36.6.7 TC Register A Register Name: TC_RA Access Type:
31 - 23 - 15
Read-only if WAVE = 0, Read/Write if WAVE = 1
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RA 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RA
3
2
1
0
* RA: Register A RA contains the Register A value in real time.
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36.6.8 TC Register B Register Name: TC_RB Access Type:
31 - 23 - 15
Read-only if WAVE = 0, Read/Write if WAVE = 1
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RB 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RB
3
2
1
0
* RB: Register B RB contains the Register B value in real time.
36.6.9 TC Register C Register Name: TC_RC Access Type:
31 - 23 - 15
Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RC 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
7
6
5
4 RC
3
2
1
0
* RC: Register C RC contains the Register C value in real time.
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36.6.10 TC Status Register Register Name: TC_SR Access Type:
31 - 23 - 15 - 7 ETRGS
Read-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 MTIOB 10 - 2 CPAS 25 - 17 MTIOA 9 - 1 LOVRS 24 - 16 CLKSTA 8 - 0 COVFS
* COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. * LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. * CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. * CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. * LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. * LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. * ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. * CLKSTA: Clock Enabling Status 0 = Clock is disabled.
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1 = Clock is enabled. * MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. * MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
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36.6.11 TC Interrupt Enable Register Register Name: TC_IER Access Type:
31 - 23 - 15 - 7 ETRGS
Write-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
* COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. * CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. * CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. * CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. * LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. * ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt.
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36.6.12 TC Interrupt Disable Register Register Name: TC_IDR Access Type:
31 - 23 - 15 - 7 ETRGS
Write-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
* COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. * LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). * CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). * CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). * CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. * LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). * LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). * ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt.
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36.6.13 TC Interrupt Mask Register Register Name: TC_IMR Access Type:
31 - 23 - 15 - 7 ETRGS
Read-only
30 - 22 - 14 - 6 LDRBS 29 - 21 - 13 - 5 LDRAS 28 - 20 - 12 - 4 CPCS 27 - 19 - 11 - 3 CPBS 26 - 18 - 10 - 2 CPAS 25 - 17 - 9 - 1 LOVRS 24 - 16 - 8 - 0 COVFS
* COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. * LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. * CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. * CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. * CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. * LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. * LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. * ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled.
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37. Controller Area Network (CAN)
37.1 Description
The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec. CAN controller accesses are made through configuration registers. 16 independent message objects (mailboxes) are implemented. Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). For the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. An interrupt is generated when the buffer is full. According to the mailbox configuration, the first message received can be locked in the CAN controller registers until the application acknowledges it, or this message can be discarded by new received messages. Any mailbox can be programmed for transmission. Several transmission mailboxes can be enabled in the same time. A priority can be defined for each mailbox independently. An internal 16-bit timer is used to stamp each received and sent message. This timer starts counting as soon as the CAN controller is enabled. This counter can be reset by the application or automatically after a reception in the last mailbox in Time Triggered Mode. The CAN controller offers optimized features to support the Time Triggered Communication (TTC) protocol.
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37.2
Block Diagram
Figure 37-1. CAN Block Diagram
Controller Area Network
CANRX CAN Protocol Controller
PIO
CANTX
Error Counter
Mailbox Priority Encoder
Control & Status MB0 MB1 MCK PMC
MBx
(x = number of mailboxes - 1)
CAN Interrupt User Interface
Internal Bus
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37.3 Application Block Diagram
Application Block Diagram
Figure 37-2.
Layers
CAN-based Profiles CAN-based Application Layer CAN Data Link Layer CAN Physical Layer
Implementation
Software Software CAN Controller Transceiver
37.4
I/O Lines Description
I/O Lines Description
Description CAN Receive Serial Data CAN Transmit Serial Data Type Input Output
Table 37-1.
Name CANRX CANTX
37.5
37.5.1
Product Dependencies
I/O Lines The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller.
37.5.2
Power Management The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN. A Low-power Mode is defined for the CAN controller: If the application does not require CAN operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Low-power Mode to complete the current transfer. After restarting the clock, the application must disable the Low-power Mode of the CAN controller.
37.5.3
Interrupt The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the CAN interrupt requires the AIC to be programmed first. Note that it is not recommended to use the CAN interrupt line in edge-sensitive mode.
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37.6
37.6.1
CAN Controller Features
CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types: * Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame. * Remote frames: A destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node then sends a data frame as a response to this node request. * Error frames: An error frame is generated by any node that detects a bus error. * Overload frames: They provide an extra delay between the preceding and the successive data frames or remote frames. The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0 Part A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link Layer and part of the physical layer are automatically handled by the CAN controller itself. The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is assigned to each mailbox. The CAN controller encapsulates or decodes data messages to build or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application.
37.6.2
Mailbox Organization The CAN module has 16 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match the standard frame identifier or the extended frame identifier. This identifier is defined for the first time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID. Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the MOT field of the CAN_MMRx register.
37.6.2.1
Message Acceptance Procedure If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value. If accepted, the message ID is copied to the CAN_MIDx register.
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Figure 37-3. Message Acceptance Procedure
CAN_MIDx CAN_MAMx Message Received
&
&
==
Yes Message Accepted
No
Message Refused
CAN_MFIDx
If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register (CAN_MFIDx). For example, if the following message IDs are handled by the same mailbox:
ID0 101000100100010010000100 0 11 00b ID1 101000100100010010000100 0 11 01b ID2 101000100100010010000100 0 11 10b ID3 101000100100010010000100 0 11 11b ID4 101000100100010010000100 1 11 00b ID5 101000100100010010000100 1 11 01b ID6 101000100100010010000100 1 11 10b ID7 101000100100010010000100 1 11 11b
The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values:
CAN_MIDx = 001 101000100100010010000100 x 11 xxb CAN_MAMx = 001 111111111111111111111111 0 11 00b
If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set:
CAN_MIDx = 001 101000100100010010000100 1 11 10b CAN_MFIDx = 00000000000000000000000000000110b
If the application associates a handler for each message ID, it may define an array of pointers to functions:
void (*pHandler[8])(void);
When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits:
unsigned int MFID0_register; MFID0_register = Get_CAN_MFID0_Register(); // Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register]();
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37.6.2.2
Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers. Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (Receive only), or, if new messages with the same ID are received, then they overwrite the previous ones (Receive with overwrite). It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers. Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow.
Mailbox Object Type Receive
Description The first message received is stored in mailbox data registers. Data remain available until the next transfer request. The last message received is stored in mailbox data register. The next message always overwrites the previous one. The application has to check whether a new message has not overwritten the current one while reading the data registers. A remote frame is sent by the mailbox. The answer received is stored in mailbox data register. This extends Receive mailbox features. Data remain available until the next transfer request.
Receive with overwrite
Consumer
37.6.2.3
Transmit Mailbox When transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier. For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in CAN_MMRx register). It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame is received, the mailbox data are sent automatically. By enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer.
Mailbox Object Type Transmit
Description The message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the Time Management Unit configuration (see Section 37.6.3). The application is notified that the message has been sent or aborted. The message prepared in the mailbox data registers will be sent after receiving the next remote frame. This extends transmit mailbox features.
Producer
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37.6.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register). It is automatically cleared in the following cases: * after a reset * when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in the CAN_SR) * after a reset of the CAN controller (CANEN bit in the CAN_MR register) * in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the CAN_MSRlast_mailbox_number register). The application can also reset the internal timer by setting TIMRST in the CAN_TCR register. The current value of the internal timer is always accessible by reading the CAN_TIM register. When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated while TOVF is set. In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is enabled by setting TIMFRZ in the CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered. To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR register is set, the value is captured at each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR register. The time management unit can operate in one of the two following modes: * Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame * Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered Mode is enabled by setting TTM field in the CAN_MR register.
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37.6.4 37.6.4.1
CAN 2.0 Standard Features CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments:
Figure 37-4. Partition of the CAN Bit Time
NOMINAL BIT TIME
SYNC_SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
TIME QUANTUM: The TIME QUANTUM (TQ) is a fixed unit of time derived from the MCK period. The total number of TIME QUANTA in a bit time is programmable from 8 to 25. SYNC SEG: SYNChronization Segment. This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. It is 1 TQ long. PROP SEG: PROPagation Segment. This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal's propagation time on the bus line, the input comparator delay, and the output driver delay. It is programmable to be 1,2,..., 8 TQ long. This parameter is defined in the PROPAG field of the "CAN Baudrate Register". PHASE SEG1, PHASE SEG2: PHASE Segment 1 and 2. The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments can be lengthened (PHASE SEG1) or shortened (PHASE SEG2) by resynchronization. Phase Segment 1 is programmable to be 1,2,..., 8 TQ long. Phase Segment 2 length has to be at least as long as the Information Processing Time (IPT) and may not be more than the length of Phase Segment 1. These parameters are defined in the PHASE1 and PHASE2 fields of the "CAN Baudrate Register". INFORMATION PROCESSING TIME: The Information Processing Time (IPT) is the time required for the logic to determine the bit level of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PHASE SEG2 shall not be less than the IPT. SAMPLE POINT:
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The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1. SJW: ReSynchronization Jump Width. The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening of the Phase Segments. SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ. If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point. In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2). t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) MCK Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. t PRS = t CSC x ( PROPAG + 1 ) t PHS1 = t CSC x ( PHASE1 + 1 ) t PHS2 = t CSC x ( PHASE2 + 1 ) To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any relevant signal edge of the current transmission. The resynchronization shortens or lengthens the bit time so that the position of the sample point is shifted with regard to the detected edge. The resynchronization jump width (SJW) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization. t SJW = t CSC x ( SJW + 1 ) Figure 37-5. CAN Bit Timing
MCK
CAN Clock tCSC tPRS tPHS1 tPHS2
NOMINAL BIT TIME
SYNC_ SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
Sample Point
Transmission Point
Example of bit timing determination for CAN baudrate of 500 Kbit/s:
MCK = 48MHz
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CAN baudrate= 500kbit/s => bit time= 2us Delay of the bus driver: 50 ns Delay of the receiver: 30ns Delay of the bus line (20m): 110ns The total number of time quanta in a bit time must be comprised between 8 and 25. If we fix the bit time to 16 time quanta: Tcsc = 1 time quanta = bit time / 16 = 125 ns => BRP = (Tcsc x MCK) - 1 = 5 The propagation segment time is equal to twice the sum of the signal's propagation time on the bus line, the receiver delay and the output driver delay: Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc => PROPAG = Tprs/Tcsc - 1 = 2 The remaining time for the two phase segments is: Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc Tphs1 + Tphs2 = 12 Tcsc Because this number is even, we choose Tphs2 = Tphs1 (else we would choose Tphs2 = Tphs1 + Tcsc) Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc => PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5 The resynchronization jump width must be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1. We choose its maximum value: Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc => SJW = Tsjw/Tcsc - 1 = 3 Finally: CAN_BR = 0x00053255
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CAN Bus Synchronization Two types of synchronization are distinguished: "hard synchronization" at the start of a frame and "resynchronization" inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (tSJW). When the magnitude of the phase error is larger than the resynchronization jump width and * the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width. * the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width. Figure 37-6. CAN Resynchronization
THE PHASE ERROR IS POSITIVE (the transmitter is slower than the receiver) Received data bit Nominal Sample point Sample point after resynchronization
Nominal bit time (before resynchronization)
SYNC_ SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_ SEG
Phase error Bit time with resynchronization
Phase error (max Tsjw)
SYNC_ SEG
PROP_SEG
PHASE_SEG1
PHASE_SEG2
SYNC_ SEG
THE PHASE ERROR IS NEGATIVE (the transmitter is faster than the receiver) Received data bit
Sample point after resynchronization
Nominal Sample point
Nominal bit time (before resynchronization)
PHASE_SEG2
SYNC_ SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_ SEG
Phase error
Bit time with resynchronization
PHASE_ SYNC_ SEG2 SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
SYNC_ SEG
Phase error (max Tsjw)
Autobaud Mode The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are
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frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR register. 37.6.4.2 Error Detection There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence): * CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame. * Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with the next bit-time. * Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time. * Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated. * Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission. Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The counters are incremented upon detected errors and respectively are decremented upon correct transmissions or receptions. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off.
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Figure 37-7. Line Error Mode
Init
TEC > 127 or REC > 127
ERROR ACTIVE
128 occurences of 11 consecutive recessive bits or CAN controller reset
ERROR PASSIVE
TEC < 127 and REC < 127
BUS OFF
TEC > 255
An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the CAN controller is in Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus-off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR register. When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register. Refer to the Bosch CAN specification v2.0 for details on fault confinement. 37.6.4.3 Overload The overload frame is provided to request a delay of the next data or remote frame by the receiver node ("Request overload frame") or to signal certain error conditions ("Reactive overload frame") related to the intermission field respectively. Reactive overload frames are transmitted after detection of the following error conditions: * Detection of a dominant bit during the first two bits of the intermission field * Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.
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Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment. 37.6.5 Low-power Mode In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive. In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Lowpower Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection of 11 consecutive recessive bits on the bus. 37.6.5.1 Enabling Low-power Mode A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The WAKEUP signal is automatically cleared once SLEEP is set. Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode. Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip's Power Management Controller (PMC). The CAN controller drains only the static current. Error counters are disabled while the SLEEP signal is set to one. Thus, to enter Low-power Mode, the software application must: - Set LPM field in the CAN_MR register - Wait for SLEEP signal rising Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC).
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Figure 37-8. Enabling Low-power Mode
Arbitration lost
CAN BUS LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3) CAN_TIM
Mailbox 1
Mailbox 3
0x0
37.6.5.2
Disabling Low-power Mode The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller. To disable Low-power Mode, the software application must: - Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC). - Clear the LPM field in the CAN_MR register The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive "recessive" bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set. If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling Low-power Mode. If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see Figure 37-9).
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Figure 37-9. Disabling Low-power Mode
Bus Activity Detected Message x Interframe synchronization
CAN BUS LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR)
Message lost
MRDY (CAN_MSRx)
37.7
37.7.1
Functional Description
CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC). The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the CAN_MR register. The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0. Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset). The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register.
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Figure 37-10. Possible Initialization Procedure
Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (AIC)
Configure a Mailbox in Reception Mode
Change CAN_BR value (ABM == 1 and CANEN == 1)
Errors ? (CAN_SR or CAN_MSRx)
Yes
No ABM = 0 and CANEN = 0
CANEN = 1 (ABM == 0)
End of Initialization
37.7.2
CAN Controller Interrupt Handling There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register. They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR register. The CAN_SR register gives all interrupt source states. The following events may initiate one of the two interrupts: * Message object interrupt - Data registers in the mailbox object are available to the application. In Receive Mode, a new message was received. In Transmit Mode, a message was transmitted successfully. - A sent transmission was aborted. * System interrupts - Bus-off interrupt: The CAN module enters the bus-off state. - Error-passive interrupt: The CAN module enters Error Passive Mode. - Error-active Mode: The CAN module is neither in Error Passive Mode nor in Busoff mode.
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- Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96. - Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization. - Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent. - Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. - Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register.
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37.7.3 37.7.3.1 CAN Controller Message Handling Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox.
Simple Receive Mailbox A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal. The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx register. See Figure 37-11. Figure 37-11. Receive Mailbox
Message ID = CAN_MIDx
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx)
Message 1
Message 2 lost
Message 3
(CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx)
Message 1
Message 3
Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx
Note:
In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction.
Receive with Overwrite Mailbox
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A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register. If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx register. The CAN controller may store a new message in the CAN data registers while the application reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the CAN_MSRx register before and after reading CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 37-12). Figure 37-12. Receive with Overwrite Mailbox
Message ID = CAN_MIDx
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) (CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx)
Message 1
Message 2
Message 3
Message 4
Message 1
Message 2
Message 3
Message 4
Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx
Chaining Mailboxes Several mailboxes may be used to receive a buffer split into several messages with the same ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive with overwrite modes, the field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced.
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If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see Figure 37-13). Figure 37-13. Chaining Three Mailboxes to Receive a Buffer Split into Three Messages
Buffer split in 3 messages
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz)
Message s1
Message s2
Message s3
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR
If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see Figure 37-14).
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Figure 37-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages
Buffer split in 4 messages
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz)
Message s1
Message s2
Message s3
Message s4
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR
37.7.3.2
Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx register. The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section "Remote Frame Handling" on page 657. Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first. Several transfer request commands can be generated at the same time by setting MBx bits in the CAN_TCR register. The priority is set in the PRIOR field of the CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox
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0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR register. When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx register until the next transfer command. Figure 37-15 shows three MBx message attempts being made (MRDY of MBx set to 0). The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the CAN transceiver. Figure 37-15. Transmitting Messages
CAN BUS MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx Abort MBx message Try to Abort MBx message MBx message MBx message
37.7.3.3
Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages.
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Figure 37-16. Producer / Consumer Model
Producer
Request
PUSH MODEL
CAN Data Frame
Consumer
Indication(s)
PULL MODEL
Producer
Indications CAN Remote Frame
Consumer
Request(s)
Response
CAN Data Frame Confirmation(s)
In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to send remote frames, and at least one in Receive Mode to capture the producer's answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer. Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With 16 mailboxes, the CAN controller can handle 16 independent producers/consumers. Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration. The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. If a remote frame is received while no data are ready to be sent (signal MRDY set in the CAN_MSRx register), then the MMI signal is set in the CAN_MSRx register. This bit is cleared by reading the CAN_MSRx register. The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using Receive and Receive with Overwrite modes.
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After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting the MACR bit in the CAN_MCR register. Please refer to the section "Transmission Handling" on page 656. Figure 37-17. Producer Handling
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Reading CAN_MSRx Remote Frame Message 1 Remote Frame Remote Frame Message 2
(CAN_MDLx CAN_MDHx)
Message 1
Message 2
Consumer Configuration A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global CAN_TCR register. The application is notified of the answer by the MRDY flag set in the CAN_MSRx register. The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. The MRTR bit in the CAN_MCRx register has no effect. This field is used only when using Transmit Mode. After a remote frame has been sent, the consumer mailbox functions as a reception mailbox. The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read operation automatically clears the MMI flag. If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register.
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Figure 37-18. Consumer Handling
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Remote Frame Message x Remote Frame Message y
(CAN_MDLx CAN_MDHx)
Message x
Message y
37.7.4
CAN Controller Timing Modes Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes: * Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame. * Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR register.
37.7.4.1
Timestamping Mode Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox.
Figure 37-19. Mailbox Timestamp
Start of Frame End of Frame
CAN BUS CAN_TIM
Message 1
Message 2
TEOF (CAN_MR) TIMESTAMP (CAN_TSTP) MTIMESTAMP (CAN_MSRx) MTIMESTAMP (CAN_MSRy) Timestamp 1 Timestamp 2
Timestamp 1 Timestamp 2
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37.7.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window.
Figure 37-20. Time Triggered Principle
Time Cycle Reference Message Reference Message
Time Windows for Messages Global Time
Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0. Synchronization by a Reference Message In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. Transmitting within a Time Window A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox. In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx register. If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR register. Freezing the Internal Timer Counter The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter
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is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set. Figure 37-21. Time Triggered Operations
End of Frame Message x Arbitration Lost Message y Arbitration Win
CAN BUS
Reference Message
Message y Internal Counter Reset
CAN_TIM Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) MTIMEMARKy == CAN_TIM MTIMEMARKx == CAN_TIM
Timer Event y MRDY (CAN_MSRy)
Time Window Basic Cycle
End of Frame
Message x Arbitration Win Message x
CAN BUS CAN_TIM
Reference Message
Internal Counter Reset
Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) Time Window Basic Cycle MTIMEMARKx == CAN_TIM
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37.8 Controller Area Network (CAN) User Interface
CAN Memory Map
Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Baudrate Register Timer Register Timestamp Register Error Counter Register Transfer Command Register Abort Command Register Reserved Mailbox 0 Mode Register Mailbox 0 Acceptance Mask Register Mailbox 0 ID Register Mailbox 0 Family ID Register Mailbox 0 Status Register Mailbox 0 Data Low Register Mailbox 0 Data High Register Mailbox 0 Control Register Mailbox 1 Mode Register Mailbox 1 Acceptance Mask Register Mailbox 1 ID register Mailbox 1 Family ID Register Mailbox 1 Status Register Mailbox 1 Data Low Register Mailbox 1 Data High Register Mailbox 1 Control Register ... Name CAN_MR CAN_IER CAN_IDR CAN_IMR CAN_SR CAN_BR CAN_TIM CAN_TIMESTP CAN_ECR CAN_TCR CAN_ACR - CAN_MMR0 CAN_MAM0 CAN_MID0 CAN_MFID0 CAN_MSR0 CAN_MDL0 CAN_MDH0 CAN_MCR0 CAN_MMR1 CAN_MAM1 CAN_MID1 CAN_MFID1 CAN_MSR1 CAN_MDL1 CAN_MDH1 CAN_MCR1 ... Access Read-Write Write-only Write-only Read-only Read-only Read/Write Read-only Read-only Read-only Write-only Write-only - Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Write-only Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Write-only ... Reset State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -
Table 37-2.
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028
0x0100 - 0x01FC 0x0200 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 0x021C 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C ...
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37.8.1 Name:
CAN Mode Register CAN_MR Read/Write
30 - 22 - 14 - 6 TIMFRZ 29 - 21 - 13 - 5 TTM 28 - 20 - 12 - 4 TEOF 27 - 19 - 11 - 3 OVL 26 25 24
Access Type:
31 - 23 - 15 - 7 DRPT
18 - 10 - 2 ABM
17 - 9 - 1 LPM
16 - 8 - 0 CANEN
* CANEN: CAN Controller Enable 0 = The CAN Controller is disabled. 1 = The CAN Controller is enabled. * LPM: Disable/Enable Low Power Mode 0 = Disable Low Power Mode. 1 = Enable Low Power Mode. CAN controller enters Low Power Mode once all pending messages have been transmitted. * ABM: Disable/Enable Autobaud/Listen mode 0 = Disable Autobaud/listen mode. 1 = Enable Autobaud/listen mode. * OVL: Disable/Enable Overload Frame 0 = No overload frame is generated. 1 = An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer. * TEOF: Timestamp messages at each end of Frame 0 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame. 1 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame. * TTM: Disable/Enable Time Triggered Mode 0 = Time Triggered Mode is disabled. 1 = Time Triggered Mode is enabled. * TIMFRZ: Enable Timer Freeze 0 = The internal timer continues to be incremented after it reached 0xFFFF. 1 = The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See "Freezing the Internal Timer Counter" on page 661. * DRPT: Disable Repeat 0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
664
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6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
37.8.2 Name: Access Type:
31 - 23 TSTP 15 MB15 7 MB7
CAN Interrupt Enable Register CAN_IER Write-only
30 - 22 TOVF 14 MB14 6 MB6 29 - 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
* MBx: Mailbox x Interrupt Enable 0 = No effect. 1 = Enable Mailbox x interrupt. * ERRA: Error Active mode Interrupt Enable 0 = No effect. 1 = Enable ERRA interrupt. * WARN: Warning Limit Interrupt Enable 0 = No effect. 1 = Enable WARN interrupt. * ERRP: Error Passive mode Interrupt Enable 0 = No effect. 1 = Enable ERRP interrupt. * BOFF: Bus-off mode Interrupt Enable 0 = No effect. 1 = Enable BOFF interrupt. * SLEEP: Sleep Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. * WAKEUP: Wakeup Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. * TOVF: Timer Overflow Interrupt Enable 0 = No effect. 1 = Enable TOVF interrupt. * TSTP: TimeStamp Interrupt Enable 0 = No effect. 1 = Enable TSTP interrupt. * CERR: CRC Error Interrupt Enable 0 = No effect. 1 = Enable CRC Error interrupt. 665
6249B-ATARM-14-Dec-06
* SERR: Stuffing Error Interrupt Enable 0 = No effect. 1 = Enable Stuffing Error interrupt. * AERR: Acknowledgment Error Interrupt Enable 0 = No effect. 1 = Enable Acknowledgment Error interrupt. * FERR: Form Error Interrupt Enable 0 = No effect. 1 = Enable Form Error interrupt. * BERR: Bit Error Interrupt Enable 0 = No effect. 1 = Enable Bit Error interrupt.
666
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6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
37.8.3 Name: Access Type:
31 - 23 TSTP 15 MB15 7 MB7
CAN Interrupt Disable Register CAN_IDR Write-only
30 - 22 TOVF 14 MB14 6 MB6 29 - 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
* MBx: Mailbox x Interrupt Disable 0 = No effect. 1 = Disable Mailbox x interrupt. * ERRA: Error Active Mode Interrupt Disable 0 = No effect. 1 = Disable ERRA interrupt. * WARN: Warning Limit Interrupt Disable 0 = No effect. 1 = Disable WARN interrupt. * ERRP: Error Passive mode Interrupt Disable 0 = No effect. 1 = Disable ERRP interrupt. * BOFF: Bus-off mode Interrupt Disable 0 = No effect. 1 = Disable BOFF interrupt. * SLEEP: Sleep Interrupt Disable 0 = No effect. 1 = Disable SLEEP interrupt. * WAKEUP: Wakeup Interrupt Disable 0 = No effect. 1 = Disable WAKEUP interrupt. * TOVF: Timer Overflow Interrupt 0 = No effect. 1 = Disable TOVF interrupt. * TSTP: TimeStamp Interrupt Disable 0 = No effect. 1 = Disable TSTP interrupt. * CERR: CRC Error Interrupt Disable 0 = No effect. 1 = Disable CRC Error interrupt. 667
6249B-ATARM-14-Dec-06
* SERR: Stuffing Error Interrupt Disable 0 = No effect. 1 = Disable Stuffing Error interrupt. * AERR: Acknowledgment Error Interrupt Disable 0 = No effect. 1 = Disable Acknowledgment Error interrupt. * FERR: Form Error Interrupt Disable 0 = No effect. 1 = Disable Form Error interrupt. * BERR: Bit Error Interrupt Disable 0 = No effect. 1 = Disable Bit Error interrupt.
668
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
37.8.4 Name: Access Type:
31 - 23 TSTP 15 MB15 7 MB7
CAN Interrupt Mask Register CAN_IMR Read-only
30 - 22 TOVF 14 MB14 6 MB6 29 - 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
* MBx: Mailbox x Interrupt Mask 0 = Mailbox x interrupt is disabled. 1 = Mailbox x interrupt is enabled. * ERRA: Error Active mode Interrupt Mask 0 = ERRA interrupt is disabled. 1 = ERRA interrupt is enabled. * WARN: Warning Limit Interrupt Mask 0 = Warning Limit interrupt is disabled. 1 = Warning Limit interrupt is enabled. * ERRP: Error Passive Mode Interrupt Mask 0 = ERRP interrupt is disabled. 1 = ERRP interrupt is enabled. * BOFF: Bus-off Mode Interrupt Mask 0 = BOFF interrupt is disabled. 1 = BOFF interrupt is enabled. * SLEEP: Sleep Interrupt Mask 0 = SLEEP interrupt is disabled. 1 = SLEEP interrupt is enabled. * WAKEUP: Wakeup Interrupt Mask 0 = WAKEUP interrupt is disabled. 1 = WAKEUP interrupt is enabled. * TOVF: Timer Overflow Interrupt Mask 0 = TOVF interrupt is disabled. 1 = TOVF interrupt is enabled. * TSTP: Timestamp Interrupt Mask 0 = TSTP interrupt is disabled. 1 = TSTP interrupt is enabled. * CERR: CRC Error Interrupt Mask 0 = CRC Error interrupt is disabled. 1 = CRC Error interrupt is enabled. 669
6249B-ATARM-14-Dec-06
* SERR: Stuffing Error Interrupt Mask 0 = Bit Stuffing Error interrupt is disabled. 1 = Bit Stuffing Error interrupt is enabled. * AERR: Acknowledgment Error Interrupt Mask 0 = Acknowledgment Error interrupt is disabled. 1 = Acknowledgment Error interrupt is enabled. * FERR: Form Error Interrupt Mask 0 = Form Error interrupt is disabled. 1 = Form Error interrupt is enabled. * BERR: Bit Error Interrupt Mask 0 = Bit Error interrupt is disabled. 1 = Bit Error interrupt is enabled.
670
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6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
37.8.5 Name: Access Type:
31 OVLSY 23 TSTP 15 MB15 7 MB7
CAN Status Register CAN_SR Read-only
30 TBSY 22 TOVF 14 MB14 6 MB6 29 RBSY 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
* MBx: Mailbox x Event 0 = No event occurred on Mailbox x. 1 = An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx register. * ERRA: Error Active mode 0 = CAN controller is not in error active mode 1 = CAN controller is in error active mode This flag is set depending on TEC and REC counter values. It is set when node is neither in error passive mode nor in bus off mode. This flag is automatically reset when above condition is not satisfied. * WARN: Warning Limit 0 = CAN controller Warning Limit is not reached. 1 = CAN controller Warning Limit is reached. This flag is set depending on TEC and REC counters values. It is set when at least one of the counters values exceeds 96. This flag is automatically reset when above condition is not satisfied. * ERRP: Error Passive mode 0 = CAN controller is not in error passive mode 1 = CAN controller is in error passive mode This flag is set depending on TEC and REC counters values. A node is error passive when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal) and less than 256. This flag is automatically reset when above condition is not satisfied. * BOFF: Bus Off mode 0 = CAN controller is not in bus-off mode 1 = CAN controller is in bus-off mode This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal). This flag is automatically reset when above condition is not satisfied. * SLEEP: CAN controller in Low power Mode 0 = CAN controller is not in low power mode. 1 = CAN controller is in low power mode.
671
6249B-ATARM-14-Dec-06
This flag is automatically reset when Low power mode is disabled * WAKEUP: CAN controller is not in Low power Mode 0 = CAN controller is in low power mode. 1 = CAN controller is not in low power mode. When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode. * TOVF: Timer Overflow 0 = The timer has not rolled-over FFFFh to 0000h. 1 = The timer rolls-over FFFFh to 0000h. This flag is automatically cleared by reading CAN_SR register. * TSTP Timestamp 0 = No bus activity has been detected. 1 = A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register). This flag is automatically cleared by reading the CAN_SR register. * CERR: Mailbox CRC Error 0 = No CRC error occurred during a previous transfer. 1 = A CRC error occurred during a previous transfer. A CRC error has been detected during last reception. This flag is automatically cleared by reading CAN_SR register. * SERR: Mailbox Stuffing Error 0 = No stuffing error occurred during a previous transfer. 1 = A stuffing error occurred during a previous transfer. A form error results from the detection of more than five consecutive bit with the same polarity. This flag is automatically cleared by reading CAN_SR register. * AERR: Acknowledgment Error 0 = No acknowledgment error occurred during a previous transfer. 1 = An acknowledgment error occurred during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared by reading CAN_SR register. * FERR: Form Error 0 = No form error occurred during a previous transfer 1 = A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields: - CRC delimiter - ACK delimiter - End of frame - Error delimiter - Overload delimiter This flag is automatically cleared by reading CAN_SR register. * BERR: Bit Error 0 = No bit error occurred during a previous transfer. 1 = A bit error occurred during a previous transfer.
672
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AT91SAM9263 Preliminary
A bit error is set when the bit value monitored on the line is different from the bit value sent. This flag is automatically cleared by reading CAN_SR register. * RBSY: Receiver busy 0 = CAN receiver is not receiving a frame. 1 = CAN receiver is receiving a frame. Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving. * TBSY: Transmitter busy 0 = CAN transmitter is not transmitting a frame. 1 = CAN transmitter is transmitting a frame. Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting. * OVLSY: Overload busy 0 = CAN transmitter is not transmitting an overload frame. 1 = CAN transmitter is transmitting a overload frame. It is automatically reset when the bus is not transmitting an overload frame.
673
6249B-ATARM-14-Dec-06
37.8.6 Name:
CAN Baudrate Register CAN_BR Read/Write
30 - 22 29 - 21 28 - 20 27 - 19 BRP 11 - 3 - 26 - 18 25 - 17 24 SMP 16
Access Type:
31 - 23 - 15 - 7 -
14 - 6
13 SJW 5 PHASE1
12
10
9 PROPAG 1 PHASE2
8
4
2
0
Any modification on one of the fields of the CANBR register must be done while CAN module is disabled. To compute the different Bit Timings, please refer to the Section 37.6.4.1 "CAN Bit Timing Configuration" on page 642. * PHASE2: Phase 2 segment This phase is used to compensate the edge phase error. t PHS2 = t CSC x ( PHASE2 + 1 ) Warning: PHASE2 value must be different from 0. * PHASE1: Phase 1 segment This phase is used to compensate for edge phase error. t PHS1 = t CSC x ( PHASE1 + 1 ) * PROPAG: Programming time segment This part of the bit time is used to compensate for the physical delay times within the network. t PRS = t CSC x ( PROPAG + 1 ) * SJW: Re-synchronization jump width To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization. t SJW = t CSC x ( SJW + 1 ) * BRP: Baudrate Prescaler. This field allows user to program the period of the CAN system clock to determine the individual bit timing. t CSC = ( BRP + 1 ) MCK The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. * SMP: Sampling Mode 0 = The incoming bit stream is sampled once at sample point. 1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. SMP Sampling Mode is automatically disabled if BRP = 0.
674
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6249B-ATARM-14-Dec-06
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37.8.7 Name: Access Type:
31 - 23 - 15 TIMER15 7 TIMER7
CAN Timer Register CAN_TIM Read-only
30 - 22 - 14 TIMER14 6 TIMER6 29 - 21 - 13 TIMER13 5 TIMER5 28 - 20 - 12 TIMER12 4 TIMER4 27 - 19 - 11 TIMER11 3 TIMER3 26 - 18 - 10 TIMER10 2 TIMER2 25 - 17 - 9 TIMER9 1 TIMER1 24 - 16 - 8 TIMER8 0 TIMER0
* TIMERx: Timer This field represents the internal CAN controller 16-bit timer value.
675
6249B-ATARM-14-Dec-06
37.8.8 Name:
CAN Timestamp Register CAN_TIMESTP Read-only
30 - 22 - 14
MTIMESTAMP 14
Access Type:
31 - 23 - 15
MTIMESTAMP 15
29 - 21 - 13
MTIMESTAMP 13
28 - 20 - 12
MTIMESTAMP 12
27 - 19 - 11
MTIMESTAMP 11
26 - 18 - 10
MTIMESTAMP 10
25 - 17 - 9
MTIMESTAMP 9
24 - 16 - 8
MTIMESTAMP 8
7
MTIMESTAMP 7
6
MTIMESTAMP 6
5
MTIMESTAMP 5
4
MTIMESTAMP 4
3
MTIMESTAMP 3
2
MTIMESTAMP 2
1
MTIMESTAMP 1
0
MTIMESTAMP 0
* MTIMESTAMPx: Timestamp This field represents the internal CAN controller 16-bit timer value. If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in the CAN_SR register. This flag is cleared by reading the CAN_SR register.
Note: The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR.
676
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6249B-ATARM-14-Dec-06
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37.8.9 Name: Access Type:
31 - 23
CAN Error Counter Register CAN_ECR Read-only
30 - 22 29 - 21 28 - 20 TEC 15 - 7 14 - 6 13 - 5 12 - 4 REC 11 - 3 10 - 2 9 - 1 8 - 0 27 - 19 26 - 18 25 - 17 24 - 16
* REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG. When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8. When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8. After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. * TEC: Transmit Error Counter When a transmitter sends an ERROR FLAG, TEC is increased by 8 except when - the transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG. - the transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant. When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8. After a successful transmission the TEC is decreased by 1 unless it was already 0.
677
6249B-ATARM-14-Dec-06
37.8.10 Name:
CAN Transfer Command Register CAN_TCR Write-only
30 - 22 - 14 MB14 6 MB6 29 - 21 - 13 MB13 5 MB5 28 - 20 - 12 MB12 4 MB4 27 - 19 - 11 MB11 3 MB3 26 - 18 - 10 MB10 2 MB2 25 - 17 - 9 MB9 1 MB1 24 - 16 - 8 MB8 0 MB0
Access Type:
31 TIMRST 23 - 15 MB15 7 MB7
This register initializes several transfer requests at the same time. * MBx: Transfer Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description It receives the next message. This triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote frame. Sends data prepared in the mailbox after receiving a remote frame from a consumer.
This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transferred before MB1). * TIMRST: Timer Reset Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode.
678
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37.8.11 Name: Access Type:
31 - 23 - 15 MB15 7 MB7
CAN Abort Command Register CAN_ACR Write-only
30 - 22 - 14 MB14 6 MB6 29 - 21 - 13 MB13 5 MB5 28 - 20 - 12 MB12 4 MB4 27 - 19 - 11 MB11 3 MB3 26 - 18 - 10 MB10 2 MB2 25 - 17 - 9 MB9 1 MB1 24 - 16 - 8 MB8 0 MB0
This register initializes several abort requests at the same time. * MBx: Abort Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame is not serviced.
It is possible to set MACR field (in the CAN_MCRx register) for each mailbox.
679
6249B-ATARM-14-Dec-06
37.8.12 Name:
CAN Message Mode Register CAN_MMRx Read/Write
30 - 22 - 14
MTIMEMARK1 4
Access Type:
31 - 23 - 15
MTIMEMARK1 5
29 - 21 - 13
MTIMEMARK1 3
28 - 20 - 12
MTIMEMARK1 2
27 - 19
26
25 MOT
24
18 PRIOR
17
16
11
MTIMEMARK1 1
10
MTIMEMARK1 0
9
MTIMEMARK9
8
MTIMEMARK8
7
MTIMEMARK7
6
MTIMEMARK6
5
MTIMEMARK5
4
MTIMEMARK4
3
MTIMEMARK3
2
MTIMEMARK2
1
MTIMEMARK1
0
MTIMEMARK0
* MTIMEMARK: Mailbox Timemark This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the Mailbox Timemark. See "Transmitting within a Time Window" on page 661. In Timestamp Mode, MTIMEMARK is set to 0. * PRIOR: Mailbox Priority This field has no effect in receive and receive with overwrite modes. In these modes, the mailbox with the lowest number is serviced first. When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before MBx 15 if they have the same priority). * MOT: Mailbox Object Type This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox:
MOT 0 0 0 0 0 1 Mailbox Object Type Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. Transmit mailbox. Mailbox is configured for transmission. Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. Reserved
0 0 1
1 1 0
0 1 0
1 1
0 1
1 X
680
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37.8.13 Name: Access Type:
31 - 23
CAN Message Acceptance Mask Register CAN_MAMx Read/Write
30 - 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24
20
19
17 MIDvB
16
15
14
13
12 MIDvB
11
10
9
8
7
6
5
4 MIDvB
3
2
1
0
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers. * MIDvB: Complementary bits for identifier in extended frame mode Acceptance mask for corresponding field of the message IDvB register of the mailbox. * MIDvA: Identifier for standard frame mode Acceptance mask for corresponding field of the message IDvA register of the mailbox. * MIDE: Identifier Version 0= Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register. 1= Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register.
681
6249B-ATARM-14-Dec-06
37.8.14 Name:
CAN Message ID Register CAN_MIDx Read/Write
30 - 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24
Access Type:
31 - 23
20
19
17 MIDvB
16
15
14
13
12 MIDvB
11
10
9
8
7
6
5
4 MIDvB
3
2
1
0
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. * MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0. * MIDE: Identifier Version This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages. * MIDvA: Identifier for standard frame mode
682
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6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
37.8.15 Name: Access Type:
31 - 23
CAN Message Family ID Register CAN_MFIDx Read-only
30 - 22 29 - 21 28 27 26 MFID 18 25 24
20 MFID
19
17
16
15
14
13
12 MFID
11
10
9
8
7
6
5
4 MFID
3
2
1
0
* MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below. As an example:
CAN_MIDx = 0x305A4321 CAN_MAMx = 0x3FF0F0FF CAN_MFIDx = 0x000000A3
683
6249B-ATARM-14-Dec-06
37.8.16 Name:
CAN Message Status Register CAN_MSRx Read only
30 - 22 MABT 14
MTIMESTAMP 14
Access Type:
31 - 23 MRDY 15
MTIMESTAMP 15
29 - 21 - 13
MTIMESTAMP 13
28 - 20 MRTR 12
MTIMESTAMP 12
27 - 19
26 - 18 MDLC
25 - 17
24 MMI 16
11
MTIMESTAMP 11
10
MTIMESTAMP 10
9
MTIMESTAMP 9
8
MTIMESTAMP 8
7
MTIMESTAMP 7
6
MTIMESTAMP 6
5
MTIMESTAMP 5
4
MTIMESTAMP 4
3
MTIMESTAMP 3
2
MTIMESTAMP 2
1
MTIMESTAMP 1
0
MTIMESTAMP 0
These register fields are updated each time a message transfer is received or aborted. MMI is cleared by reading the CAN_MSRx register. MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx register. Warning: MRTR and MDLC state depends partly on the mailbox object type. * MTIMESTAMP: Timer value This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR register). If the TEOF field in the CAN_MR register is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR register is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox. In Time Triggered Mode, MTIMESTAMP is set to 0. * MDLC: Mailbox Data Length Code
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Length of the first mailbox message received Length of the last mailbox message received No action Length of the mailbox message received Length of the mailbox message to be sent after the remote frame reception
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* MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description The first frame received has the RTR bit set. The last frame received has the RTR bit set. Reserved Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1. Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0.
* MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0 = Previous transfer is not aborted. 1 = Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx register
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Reserved Reserved Previous transfer has been aborted The remote frame transfer request has been aborted. The response to the remote frame transfer has been aborted.
685
6249B-ATARM-14-Dec-06
* MRDY: Mailbox Ready An interrupt is triggered when MRDY is set. 0 = Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx. 1 = Mailbox data registers can be read/written by the software application. This flag is cleared by writing to CAN_MCRx register.
Mailbox Object Type Receive Description At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. A remote frame has been received, mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1.
Receive with overwrite
Transmit
Consumer
Producer
* MMI: Mailbox Message Ignored 0 = No message has been ignored during the previous transfer 1 = At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx register.
Mailbox Object Type Receive Description Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message. Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost. Reserved A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message. A remote frame has been received, but no data are available to be sent.
Receive with overwrite Transmit Consumer Producer
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37.8.17 Name: Access Type:
31
CAN Message Data Low Register CAN_MDLx Read/Write
30 29 28 MDL 27 26 25 24
23
22
21
20 MDL
19
18
17
16
15
14
13
12 MDL
11
10
9
8
7
6
5
4 MDL
3
2
1
0
* MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDL value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set. Bytes are received/sent on the bus in the following order: 1. CAN_MDL[7:0] 2. CAN_MDL[15:8] 3. CAN_MDL[23:16] 4. CAN_MDL[31:24] 5. CAN_MDH[7:0] 6. CAN_MDH[15:8] 7. CAN_MDH[23:16] 8. CAN_MDH[31:24]
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37.8.18 Name:
CAN Message Data High Register CAN_MDHx Read/Write
30 29 28 MDH 27 26 25 24
Access Type:
31
23
22
21
20 MDH
19
18
17
16
15
14
13
12 MDH
11
10
9
8
7
6
5
4 MDH
3
2
1
0
* MDH: Message Data High Value When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set. Bytes are received/sent on the bus in the following order: 1. CAN_MDL[7:0] 2. CAN_MDL[15:8] 3. CAN_MDL[23:16] 4. CAN_MDL[31:24] 5. CAN_MDH[7:0] 6. CAN_MDH[15:8] 7. CAN_MDH[23:16] 8. CAN_MDH[31:24]
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37.8.19 Name: Access Type:
31 - 23 MTCR 15 - 7 -
CAN Message Control Register CAN_MCRx Write-only
30 - 22 MACR 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 MRTR 12 - 4 - 27 - 19 26 - 18 MDLC 11 - 3 - 10 - 2 - 9 - 1 - 8 - 0 - 25 - 17 24 - 16
* MDLC: Mailbox Data Length Code
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action. No action. Length of the mailbox message. No action. Length of the mailbox message to be sent after the remote frame reception.
* MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Set the RTR bit in the sent frame No action, the RTR bit in the sent frame is set automatically No action
Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox. It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time.
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6249B-ATARM-14-Dec-06
* MACR: Abort Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame will not be serviced.
It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register. * MTCR: Mailbox Transfer Command
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Allows the reception of the next message. Triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote transmission frame. Sends data prepared in the mailbox after receiving a remote frame from a Consumer.
This flag clears the MRDY and MABT flags in the CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 will be serviced before MBx 15 if they have the same priority). It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register.
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38. Pulse Width Modulation (PWM) Controller
38.1 Description
The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
38.2
Block Diagram
Figure 38-1. Pulse Width Modulation Controller Block Diagram
PWM Controller
PWMx Channel
Period Update Duty Cycle Comparator
PWMx PWMx
Clock Selector
Counter
PIO
PWM0 Channel
Period Update Duty Cycle Comparator
PWM0 PWM0
Clock Selector
MCK
Counter
PMC
Clock Generator
APB Interface
Interrupt Generator
AIC
APB
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38.3
I/O Lines Description
Each channel outputs one waveform on one external I/O line. Table 38-1.
Name PWMx
I/O Line Description
Description PWM Waveform Output for channel x Type Output
38.4
38.4.1
Product Dependencies
I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs.
38.4.2
Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled.
38.4.3
Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode.
38.5
Functional Description
The PWM macrocell is primarily composed of a clock generator module and X channels. - Clocked by the system clock, MCK, the clock generator module provides 13 clocks. - Each channel can independently choose one of the clock generator outputs. - Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers.
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38.5.1 PWM Clock Generator Figure 38-2. Functional View of the Clock Generator Block Diagram
MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024
Divider A
clkA
PREA
DIVA
PWM_MR
Divider B
clkB
PREB
DIVB
PWM_MR
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: - a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 - two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR).
693
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After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock "clk". This situation is also true when the PWM master clock is turned off through the Power Management Controller. 38.5.2 38.5.2.1 PWM Channel Block Diagram
Figure 38-3. Functional View of the Channel Block Diagram
inputs from clock generator
Channel
Clock Selector Internal Counter
Comparator
PWMx output waveform
inputs from APB bus
Each of the X channels is composed of three blocks: * A clock selector which selects one of the clocks provided by the clock generator described in Section 38.5.1 "PWM Clock Generator" on page 693. * An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is Y bits. * A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration. 38.5.2.2 Waveform Properties The different properties of output waveforms are: * the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. * the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. - If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
( X x CPRD ) ------------------------------MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
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( CRPD x DIVA ) ------------------------------------------ or ( CRPD x DIVAB ) ---------------------------------------------MCK MCK
If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
( 2 x X x CPRD ) -----------------------------------------MCK
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( 2 x CPRD x DIVA ) ----------------------------------------------------- or ( 2 x CPRD x DIVB ) ----------------------------------------------------MCK MCK
* the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: duty cycle = ( period - 1 fchannel_x_clock x CDTY ) ----------------------------------------------------------------------------------------------------------period If the waveform is center aligned, then: duty cycle = ( ( period 2 ) - 1 fchannel_x_clock x CDTY ) ) ----------------------------------------------------------------------------------------------------------------------------( period 2 ) * the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level. * the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. Figure 38-4. Non Overlapped Center Aligned Waveforms
No overlap
PWM0
PWM1
Period
Note:
1. See Figure 38-5 on page 697 for a detailed description of center aligned waveforms.
When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period.
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When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when:
* CDTY = CPRD and CPOL = 0 * CDTY = 0 and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
* CDTY = 0 and CPOL = 0 * CDTY = CPRD and CPOL = 1
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled.
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Figure 38-5. Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1
PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx)
Period Output Waveform PWMx CPOL(PWM_CMRx) = 0
Output Waveform PWMx CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx)
Left Aligned CALG(PWM_CMRx) = 0
Period Output Waveform PWMx CPOL(PWM_CMRx) = 0
Output Waveform PWMx CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
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38.5.3 38.5.3.1
PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: * Configuration of the clock generator if DIVA and DIVB are required * Selection of the clock for each channel (CPRE field in the PWM_CMRx register) * Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) * Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below. * Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below. * Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) * Enable Interrupts (Writing CHIDx in the PWM_IER register) * Enable the PWM channel (Writing CHIDx in the PWM_ENA register) It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register. * In such a situation, all channels may have the same clock selector configuration and the same period specified.
38.5.3.2
Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period.
38.5.3.3
Changing the Duty Cycle or the Period It is possible to modulate the output waveform duty cycle or period. To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle.
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Figure 38-6. Synchronized Period or Duty Cycle Update
User's Writing
PWM_CUPDx Value
1
0
PWM_CMRx. CPD
PWM_CPRDx
PWM_CDTYx
End of Cycle
To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See Figure 38-7. The second method uses an Interrupt Service Routine associated with the PWM channel.
Note: Reading the PWM_ISR register automatically clears CHIDx flags.
Figure 38-7. Polling Method
PWM_ISR Read Acknowledgement and clear previous register state
Writing in CPD field Update of the Period or Duty Cycle
CHIDx = 1
YES Writing in PWM_CUPDx The last write has been taken into account
Note:
Polarity and alignment can be modified only when the channel is disabled.
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38.5.3.4
Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register.
38.6
Pulse Width Modulation (PWM) Controller User Interface
PWM Controller Registers
Register PWM Mode Register PWM Enable Register PWM Disable Register PWM Status Register PWM Interrupt Enable Register PWM Interrupt Disable Register PWM Interrupt Mask Register PWM Interrupt Status Register Reserved Reserved Channel 0 Mode Register Channel 0 Duty Cycle Register Channel 0 Period Register Channel 0 Counter Register Channel 0 Update Register Reserved Channel 1 Mode Register Channel 1 Duty Cycle Register Channel 1 Period Register Channel 1 Counter Register Channel 1 Update Register ... PWM_CMR1 PWM_CDTY1 PWM_CPRD1 PWM_CCNT1 PWM_CUPD1 ... Read/Write Read/Write Read/Write Read-only Write-only ... 0x0 0x0 0x0 0x0 ... PWM_CMR0 PWM_CDTY0 PWM_CPRD0 PWM_CCNT0 PWM_CUPD0 Read/Write Read/Write Read/Write Read-only Write-only 0x0 0x0 0x0 0x0 Name PWM_MR PWM_ENA PWM_DIS PWM_SR PWM_IER PWM_IDR PWM_IMR PWM_ISR - Access Read/Write Write-only Write-only Read-only Write-only Write-only Read-only Read-only - Peripheral Reset Value 0 0 0 0 -
Table 38-2.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x4C - 0xFC
0x100 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 ... 0x220 0x224 0x228 0x22C 0x230 ...
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38.6.1 PWM Mode Register PWM_MR Read/Write
30 - 22 29 - 21 28 - 20 DIVB 15 - 7 14 - 6 13 - 5 12 - 4 DIVA 11 10 PREA 3 2 1 0 9 8 27 26 PREB 19 18 17 16 25 24
Register Name: Access Type:
31 - 23
* DIVA, DIVB: CLKA, CLKB Divide Factor
DIVA, DIVB 0 1 2-255
CLKA, CLKB CLKA, CLKB clock is turned off CLKA, CLKB clock is clock selected by PREA, PREB CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
* PREA, PREB Table 38-3.
PREA, PREB 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK. MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Reserved Divider Input Clock
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38.6.2
PWM Enable Register PWM_ENA Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
38.6.3
PWM Disable Register PWM_DIS Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
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38.6.4 PWM Status Register PWM_SR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
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6249B-ATARM-14-Dec-06
38.6.5
PWM Interrupt Enable Register PWM_IER Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x. 38.6.6 PWM Interrupt Disable Register PWM_IDR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
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38.6.7 PWM Interrupt Mask Register PWM_IMR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. 38.6.8 PWM Interrupt Status Register PWM_ISR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 CHID3 26 - 18 - 10 - 2 CHID2 25 - 17 - 9 - 1 CHID1 24 - 16 - 8 - 0 CHID0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register. Note: Reading PWM_ISR automatically clears CHIDx flags.
705
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38.6.9
PWM Channel Mode Register PWM_CMRx Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 26 - 18 - 10 CPD 2 CPRE 25 - 17 - 9 CPOL 1 24 - 16 - 8 CALG 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* CPRE: Channel Pre-scaler Table 38-4.
CPRE
0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Other 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 CLKA CLKB Reserved
Channel Pre-scaler
* CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. * CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. * CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
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38.6.10 PWM Channel Duty Cycle Register PWM_CDTYx Read/Write
30 29 28 CDTY 23 22 21 20 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
Only the first Y bits (internal channel counter size) are significant. * CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
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38.6.11
PWM Channel Period Register PWM_CPRDx Read/Write
30 29 28 CPRD 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 CPRD
19
18
17
16
15
14
13
12 CPRD
11
10
9
8
7
6
5
4 CPRD
3
2
1
0
Only the first Y bits (internal channel counter size) are significant. * CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: - By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
( X x CPRD ) ------------------------------MCK
- By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( CRPD x DIVA ) ------------------------------------------ or ( CRPD x DIVAB ) ---------------------------------------------MCK MCK
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: - By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
( 2 x X x CPRD ) -----------------------------------------MCK
- By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
( 2 x CPRD x DIVA ) ) ----------------------------------------------------- or ( 2 x CPRD x DIVB ----------------------------------------------------MCK MCK
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38.6.12 PWM Channel Counter Register PWM_CCNTx Read-only
30 29 28 CNT 23 22 21 20 CNT 15 14 13 12 CNT 7 6 5 4 CNT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* CNT: Channel Counter Register Internal counter value. This register is reset when: * the channel is enabled (writing CHIDx in the PWM_ENA register). * the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 38.6.13 PWM Channel Update Register PWM_CUPDx Write-only
30 29 28 CUPD 23 22 21 20 CUPD 15 14 13 12 CUPD 7 6 5 4 CUPD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first Y bits (internal channel counter size) are significant. Table 38-5.
CPD (PWM_CMRx Register) 0 1 The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the beginning of the next period. The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning of the next period.
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39. MultiMedia Card Interface (MCI)
39.1 Description
The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology.
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39.2
Block Diagram
Figure 39-1. Block Diagram
APB Bridge
PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1)
MCI Interrupt
Note:
1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy.
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39.3 Application Block Diagram
Figure 39-2. Application Block Diagram
Application Layer ex: File System, Audio, Security, etc.
Physical Layer MCI Interface
1 2 3 4 5 6 78 1234567 MMC 9
SDCard
39.4
Pin Name List
I/O Lines Description
Pin Description Command/response Clock Data 0..3 of Slot A Data 0..3 of Slot B Type(1) I/O/PP/OD I/O I/O/PP I/O/PP Comments CMD of an MMC or SDCard/SDIO CLK of an MMC or SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO
Table 39-1.
Pin Name(2)
MCCDA/MCCDB MCCK MCDA0 - MCDA3 MCDB0 - MCDB3 Notes:
1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy.
39.5
39.5.1
Product Dependencies
I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins.
39.5.2
Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock.
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39.5.3
Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI.
39.6
Bus Topology
Figure 39-3. Multimedia Memory Card Bus Topology
1234567 MMC
The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 39-2.
Pin Number 1 2 3 4 5 6 7 Notes:
Bus Topology
Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type(1) NC I/O/PP/OD S S I/O S I/O/PP Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCDz VSS VDD MCCK VSS MCDz0
1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy.
Figure 39-4. MMC Bus Connections (One Slot)
MCI
MCDA0
MCCDA
MCCK
1234567 MMC1
1234567 MMC2
1234567 MMC3
Note:
When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy.
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Figure 39-5. SD Memory Card Bus Topology
1 2 3 4 5 6 78 9
SD CARD
The SD Memory Card bus includes the signals listed in Table 39-3. Table 39-3.
Pin Number 1 2 3 4 5 6 7 8 9 Notes:
SD Memory Card Bus Signals
Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type
(1)
Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2
MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS MCDz0 MCDz1 MCDz2
I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP
1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy.
Figure 39-6. SD Card Bus Connections with One Slot
MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78
SD CARD
Note:
When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy.
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Figure 39-7. SD Card Bus Connections with Two Slots
MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1234567 MMC1 1 2 3 4 5 6 78
SD CARD 1
MCDB0 - MCDB3
MCCDB
Note:
When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy.
Figure 39-8. Mixing MultiMedia and SD Memory Cards with Two Slots
MCDA0 MCCDA MCCK
1234567 MMC2
9
9
SD CARD 2
1234567 MMC3
MCDB0 - MCDB3
SD CARD
MCCDB
Note:
When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy.
When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs.
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39.7 MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: * Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. * Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. * Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 39-4 on page 718. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: * Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. * Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See "Data Transfer Operation" on page 719.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 39.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2 PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This guarantees data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock.
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All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command:
Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z
The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 39-4 and Table 39-5. Table 39-4.
CMD Index
ALL_SEND_CID Command Description
Type Argument Resp Abbreviation Command Description Asks all cards to send their CID numbers on the CMD line
CMD2
bcr
[31:0] stuff bits
R2
ALL_SEND_CID
Note:
bcr means broadcast command with response.
Table 39-5.
Field
Fields and Values for MCI_CMDR Command Register
Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command)
CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command)
The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: * Fill the argument register (MCI_ARGR) with the command argument. * Set the command register (MCI_CMDR) (see Table 39-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer.
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The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. Figure 39-9. Command/Response Functional Flow Diagram
Set the command argument MCI_ARGR = Argument(1)
Set the command MCI_CMDR = Command
Read MCI_SR
Wait for command ready status flag
0 CMDRDY
1
Check error bits in the status register (1)
Yes Status error flags?
Read response if required (1) RETURN ERROR RETURN OK
Note:
1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification).
39.7.2
Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block.
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Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): * Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card continuously transfers (or programs) data blocks until a stop transmission command is received. * Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card transfers (or programs) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card starts an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 39.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 39-10), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read.
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Figure 39-10. Read Functional Flow Diagram
Send SELECT/DESELECT_CARD (1) command to select the card
Send SET_BLOCKLEN command(1)
No Read with PDC
Yes
Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0)
Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLength << 16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0)
Send READ_SINGLE_BLOCK command(1)
Configure the PDC channel MCI_RPR = Data Buffer Address MCI_RCR = BlockLength/4 MCI_PTCR = RXTEN
Number of words to read = BlockLength/4 Send READ_SINGLE_BLOCK command(1)
Yes Number of words to read = 0 ? Read status register MCI_SR No Read status register MCI_SR Poll the bit ENDRX = 0? Yes
Poll the bit RXRDY = 0?
Yes No
No Read data = MCI_RDR Number of words to read = Number of words to read -1
RETURN
RETURN
Note:
1. It is assumed that this command has been correctly sent (see Figure 39-9). 2. This field is also accessible in the MCI Block Register (MCI_BLKR).
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39.7.4
Write Operation In write operation, the MCI Mode Register (MCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart shows how to write a single block with or without use of PDC facilities (see Figure 39-11). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR).
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Figure 39-11. Write Functional Flow Diagram
Send SELECT/DESELECT_CARD command(1) to select the card
Send SET_BLOCKLEN command(1)
No Write using PDC
Yes
Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0)
Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLength << 16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0)
Send WRITE_SINGLE_BLOCK command(1)
Configure the PDC channel MCI_TPR = Data Buffer Address to write MCI_TCR = BlockLength/4
Number of words to write = BlockLength/4
Send WRITE_SINGLE_BLOCK command(1)
MCI_PTCR = TXTEN Yes Number of words to write = 0 ? Read status register MCI_SR No Read status register MCI_SR Poll the bit NOTBUSY= 0? Poll the bit TXRDY = 0? Yes No Yes
No MCI_TDR = Data to write Number of words to write = Number of words to write -1 RETURN
RETURN
Note:
1. It is assumed that this command has been correctly sent (see Figure 39-9). 2. This field is also accessible in the MCI Block Register (MCI_BLKR).
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The following flowchart shows how to manage a multiple write block transfer with the PDC (see Figure 39-12). Polling or interrupt method can be used to wait for the end of write according to the contents of the Interrupt Mask Register (MCI_IMR).
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Figure 39-12. Multiple Write Functional Flow Diagram
Send SELECT/DESELECT_CARD command(1) to select the card
Send SET_BLOCKLEN command
(1)
Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLength << 16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0)
Configure the PDC channel MCI_TPR = Data Buffer Address to write MCI_TCR = BlockLength/4
Send WRITE_MULTIPLE_BLOCK command(1)
MCI_PTCR = TXTEN
Read status register MCI_SR
Poll the bit BLKE = 0?
Yes
No Send STOP_TRANSMISSION command(1)
Poll the bit NOTBUSY = 0?
Yes
No RETURN
Note:
1. It is assumed that this command has been correctly sent (see Figure 39-9). 2. This field is also accessible in the MCI Block Register (MCI_BLKR).
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39.8
SD/SDIO Card Operations
The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features. The physical form factor, pin assignment and data transfer protocol are forward-compatible with the MultiMedia Card with some additions. SD slots can actually be used for more than flash memory cards. Devices that support SDIO can use small devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters, modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras and more. SD/SDIO is covered by numerous patents and trademarks, and licensing is only available through the Secure Digital Card Association. The SD/SDIO Card communication is based on a 9-pin interface (Clock, Command, 4 x Data and 3 x Power lines). The communication protocol is defined as a part of this specification. The main difference between the SD/SDIO Card and the MultiMedia Card is the initialization process. The SD/SDIO Card Register (MCI_SDCR) allows selection of the Card Slot and the data bus width. The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power up, by default, the SD/SDIO Card uses only DAT0 for data transfer. After initialization, the host can change the bus width (number of active data lines).
39.8.1
SDIO Data Transfer Type SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format (1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The TRTYP field in the MCI Command Register (MCI_CMDR) allows to choose between SDIO Byte or SDIO Block transfer. The number of bytes/blocks to transfer is set through the BCNT field in the MCI Block Register (MCI_BLKR). In SDIO Block mode, the field BLKLEN must be set to the data block size while this field is not used in SDIO Byte mode. An SDIO Card can have multiple I/O or combined I/O and memory (called Combo Card). Within a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share access to the SD bus. In order to allow the sharing of access to the host among multiple devices, SDIO and combo cards can implement the optional concept of suspend/resume (Refer to the SDIO Specification for more details). To send a suspend or a resume command, the host must set the SDIO Special Command field (IOSPCMD) in the MCI Command Register.
39.8.2
SDIO Interrupts Each function within an SDIO or Combo card may implement interrupts (Refer to the SDIO Specification for more details). In order to allow the SDIO card to interrupt the host, an interrupt function is added to a pin on the DAT[1] line to signal the card's interrupt to the host. An SDIO interrupt on each slot can be enabled through the MCI Interrupt Enable Register. The SDIO interrupt is sampled regardless of the currently selected slot.
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39.9 MultiMedia Card Interface (MCI) User Interface
Register Mapping
Register Control Register Mode Register Data Timeout Register SD/SDIO Card Register Argument Register Command Register Block Register Reserved Response Register
(1) (1) (1)
Table 39-6.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34
Register Name MCI_CR MCI_MR MCI_DTOR MCI_SDCR MCI_ARGR MCI_CMDR MCI_BLKR - MCI_RSPR MCI_RSPR MCI_RSPR MCI_RSPR MCI_RDR MCI_TDR - MCI_SR MCI_IER MCI_IDR MCI_IMR - -
Read/Write Write Read/write Read/write Read/write Read/write Write Read/write - Read Read Read Read Read Write - Read Write Write Read - -
Reset - 0x0 0x0 0x0 0x0 - 0x0 - 0x0 0x0 0x0 0x0 0x0 - - 0xC0E5 - - 0x0 - -
Response Register Response Register
Response Register(1) Receive Data Register Transmit Data Register Reserved Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for the PDC
0x38 - 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100-0x124 Note:
1. The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
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39.9.1 Name:
MCI Control Register MCI_CR Write-only
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
SWRST
-
-
-
PWSDIS
PWSEN
MCIDIS
MCIEN
* MCIEN: Multi-Media Interface Enable 0 = No effect. 1 = Enables the Multi-Media Interface if MCDIS is 0. * MCIDIS: Multi-Media Interface Disable 0 = No effect. 1 = Disables the Multi-Media Interface. * PWSEN: Power Save Mode Enable 0 = No effect. 1 = Enables the Power Saving Mode if PWSDIS is 0. Warning: Before enabling this mode, the user must set a value different from 0 in the PWSDIV field (Mode Register MCI_MR). * PWSDIS: Power Save Mode Disable 0 = No effect. 1 = Disables the Power Saving Mode. * SWRST: Software Reset 0 = No effect. 1 = Resets the MCI. A software triggered hardware reset of the MCI interface is performed.
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39.9.2 Name: Access Type:
31
MCI Mode Register MCI_MR Read/write
30 29 28 27 26 25 24
BLKLEN
23 22 21 20 19 18 17 16
BLKLEN
15 14 13 12 11 10 9 8
PDCMODE
7
PDCPADV
6
PDCFBYTE
5
WRPROOF
4
RDPROOF
3 2
PWSDIV
1 0
CLKDIV
* CLKDIV: Clock Divider Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)). * PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode. Warning: This value must be different from 0 before enabling the Power Save Mode in the MCI_CR (MCI_PWSEN bit). * RDPROOF Read Proof Enable Enabling Read Proof allows to stop the MCI Clock during read access if the internal FIFO is full. This guarantees data integrity, not bandwidth. 0 = Disables Read Proof. 1 = Enables Read Proof. * WRPROOF Write Proof Enable Enabling Write Proof allows to stop the MCI Clock during write access if the internal FIFO is full. This guarantees data integrity, not bandwidth. 0 = Disables Write Proof. 1 = Enables Write Proof. * PDCFBYTE: PDC Force Byte Transfer Enabling PDC Force Byte Transfer allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. Warning: BLKLEN value depends on PDCFBYTE. 0 = Disables PDC Force Byte Transfer. PDC type of transfer are in words. 1 = Enables PDC Force Byte Transfer. PDC type of transfer are in bytes. * PDCPADV: PDC Padding Value 0 = 0x00 value is used when padding data in write transfer (not only PDC transfer). 1 = 0xFF value is used when padding data in write transfer (not only PDC transfer). * PDCMODE: PDC-oriented Mode 0 = Disables PDC transfer 1 = Enables PDC transfer. In this case, UNRE and OVRE flags in the MCI Mode Register (MCI_SR) are deactivated after the PDC transfer has been completed. * BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MCI Block Register (MCI_BLKR).
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6249B-ATARM-14-Dec-06
Bits 16 and 17 must be set to 0 if PDCFBYTE is disabled.
Note: In SDIO Byte mode, BLKLEN field is not used.
39.9.3 Name:
MCI Data Timeout Register MCI_DTOR Read/write
30 29 28 27 26 25 24
Access Type:
31
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
-
DTOMUL
DTOCYC
* DTOCYC: Data Timeout Cycle Number * DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the MCI waits between two data block transfers. It equals (DTOCYC x Multiplier). Multiplier is defined by DTOMUL as shown in the following table:
DTOMUL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Multiplier 1 16 128 256 1024 4096 65536 1048576
If the data time-out set by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error flag (DTOE) in the MCI Status Register (MCI_SR) raises.
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39.9.4 Name: Access Type:
31
MCI SDCard/SDIO Register MCI_SDCR Read/write
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
SDCBUS
-
-
-
-
-
SDCSEL
* SDCSEL: SDCard/SDIO Slot
SDCSEL 0 0 1 1 0 1 0 1 SDCard/SDIO Slot
Slot A is selected.
Slot B selected Reserved Reserved
* SDCBUS: SDCard/SDIO Bus Width 0 = 1-bit data bus 1 = 4-bit data bus
731
6249B-ATARM-14-Dec-06
39.9.5 Name:
MCI Argument Register MCI_ARGR Read/write
30 29 28 27 26 25 24
Access Type:
31
ARG
23 22 21 20 19 18 17 16
ARG
15
14
13
12
11
10
9
8
ARG
7 6 5 4 3 2 1 0
ARG
* ARG: Command Argument
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39.9.6 Name: Access Type:
31
MCI Command Register MCI_CMDR Write-only
30 29 28 27 26 25 24
-
23
-
22
-
21
-
20
-
19
-
18 17
IOSPCMD
16
-
15
-
14 13
TRTYP
12 11
TRDIR
10 9
TRCMD
8
-
7
-
6
-
5
MAXLAT
4
OPDCMD
3 2
SPCMD
1 0
RSPTYP
CMDNB
This register is write-protected while CMDRDY is 0 in MCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD). This means that the current command execution cannot be interrupted or modified. * CMDNB: Command Number * RSPTYP: Response Type
RSP 0 0 1 1 0 1 0 1 Response Type No response. 48-bit response. 136-bit response. Reserved.
* SPCMD: Special Command
SPCMD 0 0 0 0 0 1 Command Not a special CMD. Initialization CMD: 74 clock cycles for initialization sequence. Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. Reserved. Interrupt command: Corresponds to the Interrupt Mode (CMD40). Interrupt response: Corresponds to the Interrupt Mode (CMD40).
0 0 1 1
1 1 0 0
0 1 0 1
* OPDCMD: Open Drain Command 0 = Push pull command 1 = Open drain command
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6249B-ATARM-14-Dec-06
* MAXLAT: Max Latency for Command to Response 0 = 5-cycle max latency 1 = 64-cycle max latency * TRCMD: Transfer Command
TRCMD 0 0 1 1 0 1 0 1 Transfer Type No data transfer Start data transfer Stop data transfer Reserved
* TRDIR: Transfer Direction 0 = Write 1 = Read * TRTYP: Transfer Type
TRTYP 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Transfer Type MMC/SDCard Single Block MMC/SDCard Multiple Block MMC Stream Reserved SDIO Byte SDIO Block Reserved Reserved
* IOSPCMD: SDIO Special Command
IOSPCMD 0 0 1 1 0 1 0 1 SDIO Special Command Type Not a SDIO Special Command SDIO Suspend Command SDIO Resume Command Reserved
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39.9.7 Name: Access Type:
31
MCI Block Register MCI_BLKR Read/write
30 29 28 27 26 25 24
BLKLEN
23 22 21 20 19 18 17 16
BLKLEN
15 14 13 12 11 10 9 8
BCNT
7 6 5 4 3 2 1 0
BCNT
* BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer. The transfer data type and the authorized values for BCNT field are determined by the TRTYP field in the MCI Command Register (MCI_CMDR):
TRTYP 0 1 1 0 0 0 Other values 1 0 1 Type of Transfer MMC/SDCard Multiple Block SDIO Byte SDIO Block BCNT Authorized Values From 1 to 65536: Value 0 corresponds to an infinite block transfer. From 1 to 512 bytes: value 0 corresponds to a 512-byte transfer. Values from 0x200 to 0xFFFF are forbidden. From 1 to 511 blocks: value 0 corresponds to an infinite block transfer. Values from 0x200 to 0xFFFF are forbidden. Reserved.
Warning: In SDIO Byte and Block modes, writing to the 7 last bits of BCNT field, is forbidden and may lead to unpredictable results. * BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MCI Mode Register (MCI_MR). Bits 16 and 17 must be set to 0 if PDCFBYTE is disabled.
Note: In SDIO Byte mode, BLKLEN field is not used.
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6249B-ATARM-14-Dec-06
39.9.8 Name:
MCI Response Register MCI_RSPR Read-only
30 29 28 27 26 25 24
Access Type:
31
RSP
23 22 21 20 19 18 17 16
RSP
15 14 13 12 11 10 9 8
RSP
7 6 5 4 3 2 1 0
RSP
* RSP: Response
Note: 1. The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response.
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39.9.9 Name: Access Type:
31
MCI Receive Data Register MCI_RDR Read-only
30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
7 6 5 4 3 2 1 0
DATA
* DATA: Data to Read 39.9.10 Name: Access Type:
31
MCI Transmit Data Register MCI_TDR Write-only
30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
7 6 5 4 3 2 1 0
DATA
* DATA: Data to Write
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6249B-ATARM-14-Dec-06
39.9.11 Name:
MCI Status Register MCI_SR Read-only
30 29 28 27 26 25 24
Access Type:
31
UNRE
23
OVRE
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
DTOE
14
DCRCE
13
RTOE
12
RENDE
11
RCRCE
10
RDIRE
9
RINDE
8
TXBUFE
7
RXBUFF
6
-
5
-
4
-
3
-
2
SDIOIRQB
1
SDIOIRQA
0
ENDTX
ENDRX
NOTBUSY
DTIP
BLKE
TXRDY
RXRDY
CMDRDY
* CMDRDY: Command Ready 0 = A command is in progress. 1 = The last command has been sent. Cleared when writing in the MCI_CMDR. * RXRDY: Receiver Ready 0 = Data has not yet been received since the last read of MCI_RDR. 1 = Data has been received since the last read of MCI_RDR. * TXRDY: Transmit Ready 0= The last data written in MCI_TDR has not yet been transferred in the Shift Register. 1= The last data written in MCI_TDR has been transferred in the Shift Register. * BLKE: Data Block Ended This flag must be used only for Write Operations. 0 = A data block transfer is not yet finished. Cleared when reading the MCI_SR. 1 = A data block transfer has ended, including the CRC16 Status transmission. In PDC mode (PDCMODE=1), the flag is set when the CRC Status of the last block has been transmitted (TXBUFE already set). Otherwise (PDCMODE=0), the flag is set for each transmitted CRC Status. Refer to the MMC or SD Specification for more details concerning the CRC Status. * DTIP: Data Transfer in Progress 0 = No data transfer in progress. 1 = The current data transfer is still in progress, including CRC16 calculation. Cleared at the end of the CRC16 calculation. * NOTBUSY: MCI Not Busy This flag must be used only for Write Operations. A block write operation uses a simple busy signalling of the write operation duration on the data (DAT0) line: during a data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer for the defined data transfer block length becomes free. The NOTBUSY flag allows to deal with these different states. 0 = The MCI is not ready for new data transfer. Cleared at the end of the card response. 1 = The MCI is ready for new data transfer. Set when the busy state on the data line has ended. This corresponds to a free internal data receive buffer of the card. Refer to the MMC or SD Specification for more details concerning the busy behavior. * ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in MCI_RCR or MCI_RNCR. 738
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1 = The Receive Counter Register has reached 0 since the last write in MCI_RCR or MCI_RNCR. * ENDTX: End of TX Buffer 0 = The Transmit Counter Register has not reached 0 since the last write in MCI_TCR or MCI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in MCI_TCR or MCI_TNCR.
Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller.
* RXBUFF: RX Buffer Full 0 = MCI_RCR or MCI_RNCR has a value other than 0. 1 = Both MCI_RCR and MCI_RNCR have a value of 0. * TXBUFE: TX Buffer Empty 0 = MCI_TCR or MCI_TNCR has a value other than 0. 1 = Both MCI_TCR and MCI_TNCR have a value of 0.
Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller.
* RINDE: Response Index Error 0 = No error. 1 = A mismatch is detected between the command index sent and the response index received. Cleared when writing in the MCI_CMDR. * RDIRE: Response Direction Error 0 = No error. 1 = The direction bit from card to host in the response has not been detected. * RCRCE: Response CRC Error 0 = No error. 1 = A CRC7 error has been detected in the response. Cleared when writing in the MCI_CMDR. * RENDE: Response End Bit Error 0 = No error. 1 = The end bit of the response has not been detected. Cleared when writing in the MCI_CMDR. * RTOE: Response Time-out Error 0 = No error. 1 = The response time-out set by MAXLAT in the MCI_CMDR has been exceeded. Cleared when writing in the MCI_CMDR. * DCRCE: Data CRC Error 0 = No error. 1 = A CRC16 error has been detected in the last data block. Reset by reading in the MCI_SR register. * DTOE: Data Time-out Error 0 = No error. 1 = The data time-out set by DTOCYC and DTOMUL in MCI_DTOR has been exceeded. Reset by reading in the MCI_SR register. * OVRE: Overrun 0 = No error. 1 = At least one 8-bit received data has been lost (not read). Cleared when sending a new data transfer command. * UNRE: Underrun 0 = No error. 1 = At least one 8-bit data has been sent without valid information (not written). Cleared when sending a new data transfer command. 739
6249B-ATARM-14-Dec-06
* SDIOIRQA: SDIO Interrupt for Slot A 0 = No interrupt detected on SDIO Slot A. 1 = A SDIO Interrupt on Slot A has reached. Cleared when reading the MCI_SR. * SDIOIRQB: SDIO Interrupt for Slot B 0 = No interrupt detected on SDIO Slot B. 1 = A SDIO Interrupt on Slot B has reached. Cleared when reading the MCI_SR. * RXBUFF: RX Buffer Full 0 = MCI_RCR or MCI_RNCR has a value other than 0. 1 = Both MCI_RCR and MCI_RNCR have a value of 0. * TXBUFE: TX Buffer Empty 0 = MCI_TCR or MCI_TNCR has a value other than 0. 1 = Both MCI_TCR and MCI_TNCR have a value of 0.
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39.9.12 Name: Access Type:
31
MCI Interrupt Enable Register MCI_IER Write-only
30 29 28 27 26 25 24
UNRE
23
OVRE
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
DTOE
14
DCRCE
13
RTOE
12
RENDE
11
RCRCE
10
RDIRE
9
RINDE
8
TXBUFE
7
RXBUFF
6
-
5
-
4
-
3
-
2
SDIOIRQB
1
SDIOIRQA
0
ENDTX
ENDRX
NOTBUSY
DTIP
BLKE
TXRDY
RXRDY
CMDRDY
* CMDRDY: Command Ready Interrupt Enable * RXRDY: Receiver Ready Interrupt Enable * TXRDY: Transmit Ready Interrupt Enable * BLKE: Data Block Ended Interrupt Enable * DTIP: Data Transfer in Progress Interrupt Enable * NOTBUSY: Data Not Busy Interrupt Enable * ENDRX: End of Receive Buffer Interrupt Enable * ENDTX: End of Transmit Buffer Interrupt Enable * SDIOIRQA: SDIO Interrupt for Slot A Interrupt Enable * SDIOIRQB: SDIO Interrupt for Slot B Interrupt Enable * RXBUFF: Receive Buffer Full Interrupt Enable * TXBUFE: Transmit Buffer Empty Interrupt Enable * RINDE: Response Index Error Interrupt Enable * RDIRE: Response Direction Error Interrupt Enable * RCRCE: Response CRC Error Interrupt Enable * RENDE: Response End Bit Error Interrupt Enable * RTOE: Response Time-out Error Interrupt Enable * DCRCE: Data CRC Error Interrupt Enable * DTOE: Data Time-out Error Interrupt Enable * OVRE: Overrun Interrupt Enable * UNRE: UnderRun Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
741
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39.9.13 Name:
MCI Interrupt Disable Register MCI_IDR Write-only
30 29 28 27 26 25 24
Access Type:
31
UNRE
23
OVRE
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
DTOE
14
DCRCE
13
RTOE
12
RENDE
11
RCRCE
10
RDIRE
9
RINDE
8
TXBUFE
7
RXBUFF
6
-
5
-
4
-
3
-
2
SDIOIRQB
1
SDIOIRQA
0
ENDTX
ENDRX
NOTBUSY
DTIP
BLKE
TXRDY
RXRDY
CMDRDY
* CMDRDY: Command Ready Interrupt Disable * RXRDY: Receiver Ready Interrupt Disable * TXRDY: Transmit Ready Interrupt Disable * BLKE: Data Block Ended Interrupt Disable * DTIP: Data Transfer in Progress Interrupt Disable * NOTBUSY: Data Not Busy Interrupt Disable * ENDRX: End of Receive Buffer Interrupt Disable * ENDTX: End of Transmit Buffer Interrupt Disable * SDIOIRQA: SDIO Interrupt for Slot A Interrupt Disable * SDIOIRQB: SDIO Interrupt for Slot B Interrupt Disable * RXBUFF: Receive Buffer Full Interrupt Disable * TXBUFE: Transmit Buffer Empty Interrupt Disable * RINDE: Response Index Error Interrupt Disable * RDIRE: Response Direction Error Interrupt Disable * RCRCE: Response CRC Error Interrupt Disable * RENDE: Response End Bit Error Interrupt Disable * RTOE: Response Time-out Error Interrupt Disable * DCRCE: Data CRC Error Interrupt Disable * DTOE: Data Time-out Error Interrupt Disable * OVRE: Overrun Interrupt Disable * UNRE: UnderRun Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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39.9.14 Name: Access Type:
31
MCI Interrupt Mask Register MCI_IMR Read-only
30 29 28 27 26 25 24
UNRE
23
OVRE
22
-
21
-
20
-
19
-
18
-
17
-
16
-
15
DTOE
14
DCRCE
13
RTOE
12
RENDE
11
RCRCE
10
RDIRE
9
RINDE
8
TXBUFE
7
RXBUFF
6
-
5
-
4
-
3
-
2
SDIOIRQB
1
SDIOIRQA
0
ENDTX
ENDRX
NOTBUSY
DTIP
BLKE
TXRDY
RXRDY
CMDRDY
* CMDRDY: Command Ready Interrupt Mask * RXRDY: Receiver Ready Interrupt Mask * TXRDY: Transmit Ready Interrupt Mask * BLKE: Data Block Ended Interrupt Mask * DTIP: Data Transfer in Progress Interrupt Mask * NOTBUSY: Data Not Busy Interrupt Mask * ENDRX: End of Receive Buffer Interrupt Mask * ENDTX: End of Transmit Buffer Interrupt Mask * SDIOIRQA: SDIO Interrupt for Slot A Interrupt Mask * SDIOIRQB: SDIO Interrupt for Slot B Interrupt Mask * RXBUFF: Receive Buffer Full Interrupt Mask * TXBUFE: Transmit Buffer Empty Interrupt Mask * RINDE: Response Index Error Interrupt Mask * RDIRE: Response Direction Error Interrupt Mask * RCRCE: Response CRC Error Interrupt Mask * RENDE: Response End Bit Error Interrupt Mask * RTOE: Response Time-out Error Interrupt Mask * DCRCE: Data CRC Error Interrupt Mask * DTOE: Data Time-out Error Interrupt Mask * OVRE: Overrun Interrupt Mask * UNRE: UnderRun Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
743
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40. Ethernet MAC 10/100 (EMACB)
40.1 Description
The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external address match signal. The statistics register block contains registers for counting various types of event associated with transmit and receive operations. These registers, along with the status words stored in the receive buffer list, enable software to generate network management statistics compatible with IEEE 802.3.
40.2
Block Diagram
Figure 40-1. EMAC Block Diagram
Address Checker
APB Slave
Register Interface
Statistics Registers
MDIO
Control Registers
DMA Interface
RX FIFO TX FIFO
Ethernet Receive
AHB Master MII/RMII
Ethernet Transmit
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6249B-ATARM-14-Dec-06
40.3
Functional Description
Figure 40-1 illustrates the different blocks of the EMAC module. The control registers drive the MDIO interface, setup up DMA activity, start frame transmission and select modes of operation such as full- or half-duplex. The receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the address checking block and DMA interface.
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The transmit block takes data from the DMA interface, adds preamble and, if necessary, pad and FCS, and transmits data according to the CSMA/CD (carrier sense multiple access with collision detect) protocol. The start of transmission is deferred if CRS (carrier sense) is active. If COL (collision) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random back off. CRS and COL have no effect in full duplex mode. The DMA block connects to external memory through its AHB bus interface. It contains receive and transmit FIFOs for buffering frame data. It loads the transmit FIFO and empties the receive FIFO using AHB bus master operations. Receive data is not sent to memory until the address checking logic has determined that the frame should be copied. Receive or transmit frames are stored in one or more buffers. Receive buffers have a fixed length of 128 bytes. Transmit buffers range in length between 0 and 2047 bytes, and up to 128 buffers are permitted per frame. The DMA block manages the transmit and receive framebuffer queues. These queues can hold multiple frames.
40.3.1
Memory Interface Frame data is transferred to and from the EMAC through the DMA interface. All transfers are 32-bit words and may be single accesses or bursts of 2, 3 or 4 words. Burst accesses do not cross sixteen-byte boundaries. Bursts of 4 words are the default data transfer; single accesses or bursts of less than four words may be used to transfer data at the beginning or the end of a buffer. The DMA controller performs six types of operation on the bus. In order of priority, these are: 1. Receive buffer manager write 2. Receive buffer manager read 3. Transmit data DMA read 4. Receive data DMA write 5. Transmit buffer manager read 6. Transmit buffer manager write
40.3.1.1
FIFO The FIFO depths are Transmit_FIFO_size bytes and Receive_FIFO_size bytes and area function of the system clock speed, memory latency and network speed. Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when the FIFO contains four words and has space for three more. For transmit, a bus request is generated when there is space for four words, or when there is space for two words if the next transfer is to be only one or two words. Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (12 bytes) of data. At 100 Mbit/s, it takes 960 ns to transmit or receive 12 bytes of data. In addition, six master clock cycles should be allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 60 MHz master clock this takes 100 ns, making the bus latency requirement 860 ns.
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6249B-ATARM-14-Dec-06
40.3.1.2
Receive Buffers Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address. For the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14 and 15 of the network configuration register. If the start location of the buffer is offset the available length of the first buffer of a frame is reduced by the corresponding number of bytes. Each list entry consists of two words, the first being the address of the receive buffer and the second being the receive status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes except for the "start of frame" bit and the offset bits, if appropriate. Bit zero of the address field is written to one to show the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with receive frame data. The final buffer descriptor status word contains the complete frame status. Refer to Table 40-1 for details of the receive buffer descriptor list.
Table 40-1.
Bit
Receive Buffer Descriptor Entry
Function Word 0
31:2 1 0
Address of beginning of buffer Wrap - marks last descriptor in receive buffer descriptor list. Ownership - needs to be zero for the EMAC to write data to the receive buffer. The EMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again. Word 1
31 30 29 28 27 26 25 24 23 22 21 20 19:17 16 15
Global all ones broadcast address detected Multicast hash match Unicast hash match External address match Reserved for future use Specific address register 1 match Specific address register 2 match Specific address register 3 match Specific address register 4 match Type ID match VLAN tag detected (i.e., type id of 0x8100) Priority tag detected (i.e., type id of 0x8100 and null VLAN identifier) VLAN priority (only valid if bit 21 is set) Concatenation format indicator (CFI) bit (only valid if bit 21 is set) End of frame - when set the buffer contains the end of a frame. If end of frame is not set, then the only other valid status are bits 12, 13 and 14.
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Table 40-1.
Bit 14
Receive Buffer Descriptor Entry (Continued)
Function Start of frame - when set the buffer contains the start of a frame. If both bits 15 and 14 are set, then the buffer contains a whole frame. Receive buffer offset - indicates the number of bytes by which the data in the first buffer is offset from the word address. Updated with the current values of the network configuration register. If jumbo frame mode is enabled through bit 3 of the network configuration register, then bits 13:12 of the receive buffer descriptor entry are used to indicate bits 13:12 of the frame length. Length of frame including FCS (if selected). Bits 13:12 are also used if jumbo frame mode is selected.
13:12
11:0
To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the wrap bit and indicates the last entry in the list. The start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive. As soon as the receive block starts writing received frame data to the receive FIFO, the receive buffer manager reads the first receive buffer location pointed to by the receive buffer queue pointer register. If the filter block then indicates that the frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the current buffer pointer has its wrap bit set or is the 1024th descriptor, the next receive buffer location is read from the beginning of the receive descriptor list. Otherwise, the next receive buffer location is read from the next word in memory. There is an 11-bit counter to count out the 2048 word locations of a maximum length, receive buffer descriptor list. This is added with the value originally written to the receive buffer queue pointer register to produce a pointer into the list. A read of the receive buffer queue pointer register returns the pointer value, which is the queue entry currently being accessed. The counter is reset after receive status is written to a descriptor that has its wrap bit set or rolls over to zero after 1024 descriptors have been accessed. The value written to the receive buffer pointer register may be any word-aligned address, provided that there are at least 2048 word locations available between the pointer and the top of the memory. Section 3.6 of the AMBA 2.0 specification states that bursts should not cross 1K boundaries. As receive buffer manager writes are bursts of two words, to ensure that this does not occur, it is best to write the pointer register with the least three significant bits set to zero. As receive buffers are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate used. If a receive error is detected the receive buffer currently being written is recovered. Previous buffers are not recovered. Software should search through the used bits in the buffer descriptors to find out how many frames have been received. It should be checking the start-of-frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue pointer register which changes continuously as more buffers are used. For CRC errored frames, excessive length frames or length field mismatched frames, all of which are counted in the statistics registers, it is possible that a frame fragment might be stored in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a buffer following a buffer with no end of frame bit set.
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For a properly working Ethernet system, there should be no excessively long frames or frames greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long. Therefore, it is a rare occurrence to find a frame fragment in a receive buffer. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the receive status register and triggers an interrupt. If bit zero is set when the receive buffer manager reads the location of the receive buffer and a frame is being received, the frame is discarded and the receive resource error statistics register is incremented. A receive overrun condition occurs when bus was not granted in time or because HRESP was not OK (bus error). In a receive overrun condition, the receive overrun interrupt is asserted and the buffer currently being written is recovered. The next frame received with an address that is recognized reuses the buffer. If bit 17 of the network configuration register is set, the FCS of received frames shall not be copied to memory. The frame length indicated in the receive status field shall be reduced by four bytes in this case. 40.3.1.3 Transmit Buffer Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number of buffers permitted for each transmit frame is 128. The start location for each transmit buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer register. Each list entry consists of two words, the first being the byte address of the transmit buffer and the second containing the transmit control and status. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad is also automatically generated to take frames to a minimum length of 64 bytes. Table 40-2 on page 751 defines an entry in the transmit buffer descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits 31 to 0 in the first word of each list entry. The second transmit buffer descriptor is initialized with control information that indicates the length of the buffer, whether or not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame. After transmission, the control bits are written back to the second word of the first buffer along with the "used" bit and other status information. Bit 31 is the "used" bit which must be zero when the control word is read if transmission is to happen. It is written to one when a frame has been transmitted. Bits 27, 28 and 29 indicate various transmit error conditions. Bit 30 is the "wrap" bit which can be set for any buffer within a frame. If no wrap bit is encountered after 1024 descriptors, the queue pointer rolls over to the start in a similar fashion to the receive queue. The transmit buffer queue pointer register must not be written while transmit is active. If a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the trans-
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mit queue. Note that disabling receive does not have the same effect on the receive queue pointer. Once the transmit queue is initialized, transmit is activated by writing to bit 9, the Transmit Start bit of the network control register. Transmit is halted when a buffer descriptor with its used bit set is read, or if a transmit error occurs, or by writing to the transmit halt bit of the network control register. (Transmission is suspended if a pause frame is received while the pause enable bit is set in the network configuration register.) Rewriting the start bit while transmission is active is allowed. Transmission control is implemented with a Tx_go variable which is readable in the transmit status register at bit location 3. The Tx_go variable is reset when: - transmit is disabled - a buffer descriptor with its ownership bit set is read - a new value is written to the transmit buffer queue pointer register - bit 10, tx_halt, of the network control register is written - there is a transmit error such as too many retries or a transmit underrun. To set tx_go, write to bit 9, tx_start, of the network control register. Transmit halt does not take effect until any ongoing transmit finishes. If a collision occurs during transmission of a multibuffer frame, transmission automatically restarts from the first buffer of the frame. If a "used" bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, tx_er is asserted and the FCS is bad. If transmission stops due to a transmit error, the transmit queue pointer resets to point to the beginning of the transmit queue. Software needs to re-initialize the transmit queue after a transmit error. If transmission stops due to a "used" bit being read at the start of the frame, the transmission queue pointer is not reset and transmit starts from the same transmit buffer descriptor when the transmit start bit is written Table 40-2.
Bit
Transmit Buffer Descriptor Entry
Function Word 0
31:0
Byte Address of buffer Word 1 Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software has to clear this bit before the buffer can be used again. Note: This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used.
31
30 29 28 27 26:17 16
Wrap. Marks last descriptor in transmit buffer descriptor list. Retry limit exceeded, transmit error detected Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or when buffers are exhausted in mid frame. Buffers exhausted in mid frame Reserved No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame.
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Table 40-2.
Bit 15 14:11 10:0
Transmit Buffer Descriptor Entry
Function Last buffer. When set, this bit indicates the last buffer in the current frame has been reached. Reserved Length of buffer
40.3.2
Transmit Block This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, taking the frame length to a minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retry transmission after the back off time has elapsed. The back-off time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision, 1 bit is used, after the second 2, and so on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are made if 16 attempts cause collisions. If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion and the tx_er signal is asserted. For a properly configured system, this should never happen. If the back pressure bit is set in the network control register in half duplex mode, the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half-duplex mode.
40.3.3
Pause Frame Support The start of an 802.3 pause frame is as follows: Table 40-3. Start of an 802.3 Pause Frame
Source Address 6 bytes Type (Mac Control Frame) 0x8808 Pause Opcode 0x0001 Pause Time 2 bytes
Destination Address 0x0180C2000001
The network configuration register contains a receive pause enable bit (13). If a valid pause frame is received, the pause time register is updated with the frame's pause time, regardless of its current contents and regardless of the state of the configuration register bit 13. An inter-
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rupt (12) is triggered when a pause frame is received, assuming it is enabled in the interrupt mask register. If bit 13 is set in the network configuration register and the value of the pause time register is non-zero, no new frame is transmitted until the pause time register has decremented to zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the EMAC is configured for full-duplex operation. If the EMAC is configured for half-duplex, there is no transmission pause, but the pause frame received interrupt is still triggered. A valid pause frame is defined as having a destination address that matches either the address stored in specific address register 1 or matches 0x0180C2000001 and has the MAC control frame type ID of 0x8808 and the pause opcode of 0x0001. Pause frames that have FCS or other errors are treated as invalid and are discarded. Valid pause frames received increment the Pause Frame Received statistic register. The pause time register decrements every 512 bit times (i.e., 128 rx_clks in nibble mode) once transmission has stopped. For test purposes, the register decrements every rx_clk cycle once transmission has stopped if bit 12 (retry test) is set in the network configuration register. If the pause enable bit (13) is not set in the network configuration register, then the decrementing occurs regardless of whether transmission has stopped or not. An interrupt (13) is asserted whenever the pause time register decrements to zero (assuming it is enabled in the interrupt mask register). 40.3.4 Receive Block The receive block checks for valid preamble, FCS, alignment and length, presents received frames to the DMA block and stores the frames destination address for use by the address checking block. If, during frame reception, the frame is found to be too long or rx_er is asserted, a bad frame indication is sent to the DMA block. The DMA block then ceases sending data to memory. At the end of frame reception, the receive block indicates to the DMA block whether the frame is good or bad. The DMA block recovers the current receive buffer if the frame was bad. The receive block signals the register block to increment the alignment error, the CRC (FCS) error, the short frame, long frame, jabber error, the receive symbol error statistics and the length field mismatch statistics. The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to 10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 40.3.5 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory. Whether a frame is copied depends on what is enabled in the network configuration register, the state of the external match pin, the contents of the specific address and hash registers and the frame's destination address. In this implementation of the EMAC, the frame's source address is not checked. Provided that bit 18 of the Network Configuration register is not set, a frame is not copied to memory if the EMAC is transmitting in half duplex mode at the time a destination address is received. If bit 18 of the Network Configuration register is set, frames can be received while transmitting in half-duplex mode. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, the LSB of the first byte of the frame, is the group/individual bit: this is One for multi-
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cast addresses and Zero for unicast. The All Ones address is the broadcast address, and a special case of multicast. The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific address register bottom and specific address register top. Specific address register bottom stores the first four bytes of the destination address and specific address register top contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the specific address registers once they have been activated. The addresses are deactivated at reset or when their corresponding specific address register bottom is written. They are activated when specific address register top is written. If a receive frame address matches an active address, the frame is copied to memory. The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB. Preamble 55 SFD D5 DA (Octet0 - LSB) 21 DA(Octet 1) 43 DA(Octet 2) 65 DA(Octet 3) 87 DA(Octet 4) A9 DA (Octet5 - MSB) CB SA (LSB) 00 SA 00 SA 00 SA 00 SA 00 SA (MSB) 43 SA (LSB) 21 The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: * Base address + 0x98 0x87654321 (Bottom) * Base address + 0x9C 0x0000CBA9 (Top) And for a successful match to the Type ID register, the following should be set up: * Base address + 0xB8 0x00004321
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40.3.6 Broadcast Address The broadcast address of 0xFFFFFFFFFFFF is recognized if the `no broadcast' bit in the network configuration register is zero. Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function. The hash function is an exclusive or of every sixth bit of the destination address.
40.3.7
hash_index[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47] hash_index[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46] hash_index[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45] hash_index[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44] hash_index[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43] hash_index[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the hash register, then the frame is matched according to whether the frame is multicast or unicast. A multicast match is signalled if the multicast hash enable bit is set. da[0] is 1 and the hash index points to a bit set in the hash register. A unicast match is signalled if the unicast hash enable bit is set. da[0] is 0 and the hash index points to a bit set in the hash register. To receive all multicast frames, the hash register should be set with all ones and the multicast hash enable bit should be set in the network configuration register. 40.3.8 Copy All Frames (or Promiscuous Mode) If the copy all frames bit is set in the network configuration register, then all non-errored frames are copied to memory. For example, frames that are too long, too short, or have FCS errors or rx_er asserted during reception are discarded and all others are received. Frames with FCS errors are copied to memory if bit 19 in the network configuration register is set. Type ID Checking The contents of the type_id register are compared against the length/type ID of received frames (i.e., bytes 13 and 14). Bit 22 in the receive buffer descriptor status is set if there is a match. The reset state of this register is zero which is unlikely to match the length/type ID of any valid Ethernet frame.
Note: A type ID match does not affect whether a frame is copied to memory.
40.3.9
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40.3.10
VLAN Support An Ethernet encoded 802.1Q VLAN tag looks like this: Table 40-4. 802.1Q VLAN Tag
TCI (Tag Control Information) 16 bits First 3 bits priority, then CFI bit, last 12 bits VID
TPID (Tag Protocol Identifier) 16 bits 0x8100
The VLAN tag is inserted at the 13th byte of the frame, adding an extra four bytes to the frame. If the VID (VLAN identifier) is null (0x000), this indicates a priority-tagged frame. The MAC can support frame lengths up to 1536 bytes, 18 bytes more than the original Ethernet maximum frame length of 1518 bytes. This is achieved by setting bit 8 in the network configuration register. The following bits in the receive buffer descriptor status word give information about VLAN tagged frames: * Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100) * Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is set bit 21 is set also.) * Bit 19, 18 and 17 set to priority if bit 21 is set * Bit 16 set to CFI if bit 21 is set 40.3.11 PHY Maintenance The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set to zero, and bit eleven is set to one in the network configuration register). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration register in the "Network Control Register" on page 763. 40.3.12 Media Independent Interface The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface is selected.
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The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in Table 40-5. Table 40-5.
Pin Name ETXCK_EREFCK ECRS ECOL ERXDV ERX0 - ERX3 ERXER ERXCK ETXEN ETX0-ETX3 ETXER
Pin Configuration
MII ETXCK: Transmit Clock ECRS: Carrier Sense ECOL: Collision Detect ERXDV: Data Valid ERX0 - ERX3: 4-bit Receive Data ERXER: Receive Error ERXCK: Receive Clock ETXEN: Transmit Enable ETX0 - ETX3: 4-bit Transmit Data ETXER: Transmit Error ETXEN: Transmit Enable ETX0 - ETX1: 2-bit Transmit Data ECRSDV: Carrier Sense/Data Valid ERX0 - ERX1: 2-bit Receive Data ERXER: Receive Error RMII EREFCK: Reference Clock
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100Mb/s data rate. 40.3.12.1 RMII Transmit and Receive Operation The same signals are used internally for both the RMII and the MII operations. The RMII maps these signals in a more pin-efficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense and data valid signals are combined into the ECRSDV signal. This signal contains information on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision detect (ECOL) are not used in RMII mode.
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40.4
40.4.1
Programming Interface
Initialization Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. Write to network control register to disable transmit and receive circuits. 2. Write to network control register to change loop-back mode. 3. Write to network control register to re-enable transmit or receive circuits.
Note: These writes to network control register cannot be combined in any way.
40.4.1.1
40.4.1.2
Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in "Receive Buffer Descriptor Entry" on page 748. It points to this data structure.
Figure 40-2. Receive Buffer List
Receive Buffer 0 Receive Buffer Queue Pointer (MAC Register) Receive Buffer 1
Receive Buffer N Receive Buffer Descriptor List (In memory) (In memory)
To create the list of buffers: 1. Allocate a number (n) of buffers of 128 bytes in system memory. 2. Allocate an area 2n words for the receive buffer descriptor entry in system memory and create n entries in this list. Mark all entries in this list as owned by EMAC, i.e., bit 0 of word 0 set to 0. 3. If less than 1024 buffers are defined, the last descriptor must be marked with the wrap bit (bit 1 in word 0 set to 1). 4. Write address of receive buffer descriptor entry to EMAC register receive_buffer queue pointer. 5. The receive circuits can then be enabled by writing to the address recognition registers and then to the network control register. 758
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40.4.1.3 Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries (as defined in Table 40-2 on page 751) that points to this data structure. To create this list of buffers: 1. Allocate a number (n) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. 2. Allocate an area 2n words for the transmit buffer descriptor entry in system memory and create N entries in this list. Mark all entries in this list as owned by EMAC, i.e. bit 31 of word 1 set to 0. 3. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit -- bit 30 in word 1 set to 1. 4. Write address of transmit buffer descriptor entry to EMAC register transmit_buffer queue pointer. 5. The transmit circuits can then be enabled by writing to the network control register. 40.4.1.4 Address Matching The EMAC register-pair hash address and the four specific address register-pairs must be written with the required values. Each register-pair comprises a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register-pair after the bottom-register has been written and re-enabled when the top register is written. See "Address Checking Block" on page 753. for details of address matching. Each register-pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. Interrupts There are 14 interrupt conditions that are detected within the EMAC. These are ORed to make a single interrupt. Depending on the overall system design, this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler (Refer to the AIC programmer datasheet). To ascertain which interrupt has been generated, read the interrupt status register. Note that this register clears itself when read. At reset, all interrupts are disabled. To enable an interrupt, write to interrupt enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to interrupt disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read interrupt mask register: if the bit is set to 1, the interrupt is disabled. 40.4.1.6 Transmitting Frames To set up a frame for transmission: 1. Enable transmit in the network control register. 2. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used as long as they conclude on byte borders. 3. Set-up the transmit buffer list. 4. Set the network control register to enable transmission and enable interrupts. 5. Write data for transmission into these buffers. 6. Write the address to transmit buffer descriptor queue pointer. 7. Write control and length to word one of the transmit buffer descriptor entry.
40.4.1.5
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8. Write to the transmit start bit in the network control register. 40.4.1.7 Receiving Frames When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following cases, the frame is written to system memory: * if it matches one of the four specific address registers. * if it matches the hash address function. * if it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. * if the EMAC is configured to copy all frames. The register receive buffer queue pointer points to the next entry (see Table 40-1 on page 748) and the EMAC uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, the EMAC then updates the receive buffer descriptor entry with the reason for the address match and marks the area as being owned by software. Once this is complete an interrupt receive complete is set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership bit back to 0. If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available is set. If the frame is not successfully received, a statistic register is incremented and the frame is discarded without informing software.
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40.5 Ethernet MAC 10/100 (EMAC) User Interface
Ethernet MAC 10/100 (EMAC) Register Mapping
Register Network Control Register Network Configuration Register Network Status Register Reserved Reserved Transmit Status Register Receive Buffer Queue Pointer Register Transmit Buffer Queue Pointer Register Receive Status Register Interrupt Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Phy Maintenance Register Pause Time Register Pause Frames Received Register Frames Transmitted Ok Register Single Collision Frames Register Multiple Collision Frames Register Frames Received Ok Register Frame Check Sequence Errors Register Alignment Errors Register Deferred Transmission Frames Register Late Collisions Register Excessive Collisions Register Transmit Underrun Errors Register Carrier Sense Errors Register Receive Resource Errors Register Receive Overrun Errors Register Receive Symbol Errors Register Excessive Length Errors Register Receive Jabbers Register Undersize Frames Register SQE Test Errors Register Received Length Field Mismatch Register EMAC_TSR EMAC_RBQP EMAC_TBQP EMAC_RSR EMAC_ISR EMAC_IER EMAC_IDR EMAC_IMR EMAC_MAN EMAC_PTR EMAC_PFR EMAC_FTO EMAC_SCF EMAC_MCF EMAC_FRO EMAC_FCSE EMAC_ALE EMAC_DTF EMAC_LCOL EMAC_ECOL EMAC_TUND EMAC_CSE EMAC_RRE EMAC_ROV EMAC_RSE EMAC_ELE EMAC_RJA EMAC_USF EMAC_STE EMAC_RLE Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_3FFF 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Name EMAC_NCR EMAC_NCFG EMAC_NSR Access Read/Write Read/Write Read-only Reset Value 0 0x800 -
Table 40-6.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 0x88
761
6249B-ATARM-14-Dec-06
Table 40-6.
Offset 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xC0 0xC8-0xF8 0xC8 - 0xFC
Ethernet MAC 10/100 (EMAC) Register Mapping (Continued)
Register Hash Register Bottom [31:0] Register Hash Register Top [63:32] Register Specific Address 1 Bottom Register Specific Address 1 Top Register Specific Address 2 Bottom Register Specific Address 2 Top Register Specific Address 3 Bottom Register Specific Address 3 Top Register Specific Address 4 Bottom Register Specific Address 4 Top Register Type ID Checking Register User Input/output Register Reserved Reserved Name EMAC_HRB EMAC_HRT EMAC_SA1B EMAC_SA1T EMAC_SA2B EMAC_SA2T EMAC_SA3B EMAC_SA3T EMAC_SA4B EMAC_SA4T EMAC_TID EMAC_USRIO - - Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write - - Reset Value 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 - -
762
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.1 Network Control Register EMAC_NCR Read/Write
30 - 22 - 14 - 6 INCSTAT 29 - 21 - 13 - 5 CLRSTAT 28 - 20 - 12 27 - 19 - 11 26 - 18 - 10 THALT 2 RE 25 - 17 - 9 TSTART 1 LLB 24 - 16 - 8 BP 0 LB
Register Name: Access Type:
31 - 23 - 15 - 7 WESTAT
4 MPE
3 TE
* LB: LoopBack Asserts the loopback signal to the PHY. * LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4. rx_clk and tx_clk may glitch as the EMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. * RE: Receive enable When set, enables the EMAC to receive data. When reset, frame reception stops immediately and the receive FIFO is cleared. The receive queue pointer register is unaffected. * TE: Transmit enable When set, enables the Ethernet transmitter to send data. When reset transmission, stops immediately, the transmit FIFO and control registers are cleared and the transmit queue pointer register resets to point to the start of the transmit descriptor list. * MPE: Management port enable Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low. * CLRSTAT: Clear statistics registers This bit is write only. Writing a one clears the statistics registers. * INCSTAT: Increment statistics registers This bit is write only. Writing a one increments all the statistics registers by one for test purposes. * WESTAT: Write enable for statistics registers Setting this bit to one makes the statistics registers writable for functional test purposes. * BP: Back pressure If set in half duplex mode, forces collisions on all received frames.
763
6249B-ATARM-14-Dec-06
* TSTART: Start transmission Writing one to this bit starts transmission. * THALT: Transmit halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.
40.5.2
Network Configuration Register EMAC_NCFGR
Register Name:
764
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
Access Type:
31 - 23 - 15 RBOF 7 UNI 6 MTI
Read/Write
30 - 22 - 14 29 - 21 - 13 PAE 5 NBC 28 - 20 - 12 RTY 4 CAF 27 - 19 IRXFCS 11 CLK 3 JFRAME 2 - 1 FD 26 - 18 EFRHD 10 25 - 17 DRFCS 9 24 - 16 RLCE 8 BIG 0 SPD
* SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin. * FD: Full Duplex If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. Also controls the half_duplex pin. * CAF: Copy All Frames When set to 1, all valid frames are received. * JFRAME: Jumbo Frames Set to one to enable jumbo frames of up to 10240 bytes to be accepted. * NBC: No Broadcast When set to 1, frames addressed to the broadcast address of all ones are not received. * MTI: Multicast Hash Enable When set, multicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. * UNI: Unicast Hash Enable When set, unicast frames are received when the 6-bit hash function of the destination address points to a bit that is set in the hash register. * BIG: Receive 1536 bytes frames Setting this bit means the EMAC receives frames up to 1536 bytes in length. Normally, the EMAC would reject any frame above 1518 bytes. * CLK: MDC clock divider Set according to system clock speed. This determines by what number system clock is divided to generate MDC. For conformance with 802.3, MDC must not exceed 2.5MHz (MDC is only active during MDIO read and write operations).
CLK 00 01 10 11 MDC MCK divided by 8 (MCK up to 20 MHz) MCK divided by 16 (MCK up to 40 MHz) MCK divided by 32 (MCK up to 80 MHz) MCK divided by 64 (MCK up to 160 MHz)
* RTY: Retry test
765
6249B-ATARM-14-Dec-06
Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. * PAE: Pause Enable When set, transmission pauses when a valid pause frame is received. * RBOF: Receive Buffer Offset Indicates the number of bytes by which the received data is offset from the start of the first receive buffer.
RBOF 00 01 10 11 Offset No offset from start of receive buffer One-byte offset from start of receive buffer Two-byte offset from start of receive buffer Three-byte offset from start of receive buffer
* RLCE: Receive Length field Checking Enable When set, frames with measured lengths shorter than their length fields are discarded. Frames containing a type ID in bytes 13 and 14 -- length/type ID = 0600 -- are not be counted as length errors. * DRFCS: Discard Receive FCS When set, the FCS field of received frames are not be copied to memory. * EFRHD: Enable Frames to be received in half-duplex mode while transmitting. * IRXFCS: Ignore RX FCS When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.
766
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.3 Network Status Register EMAC_NSR Read-only
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 IDLE 25 - 17 - 9 - 1 MDIO 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. * IDLE 0 = The PHY management logic is idle (i.e., has completed). 1 = The PHY logic is running.
767
6249B-ATARM-14-Dec-06
40.5.4
Transmit Status Register EMAC_TSR Read/Write
30 - 22 - 14 - 6 UND 29 - 21 - 13 - 5 COMP 28 - 20 - 12 - 4 BEX 27 - 19 - 11 - 3 TGO 26 - 18 - 10 - 2 RLE 25 - 17 - 9 - 1 COL 24 - 16 - 8 - 0 UBR
Register Name: Access Type:
31 - 23 - 15 - 7 -
This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. * UBR: Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit. * COL: Collision Occurred Set by the assertion of collision. Cleared by writing a one to this bit. * RLE: Retry Limit exceeded Cleared by writing a one to this bit. * TGO: Transmit Go If high transmit is active. * BEX: Buffers exhausted mid frame If the buffers run out during transmission of a frame, then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit. * COMP: Transmit Complete Set when a frame has been transmitted. Cleared by writing a one to this bit. * UND: Transmit Underrun Set when transmit DMA was not able to read data from memory, either because the bus was not granted in time, because a not OK hresp(bus error) was returned or because a used bit was read midway through frame transmission. If this occurs, the transmitter forces bad CRC. Cleared by writing a one to this bit.
768
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.5 Receive Buffer Queue Pointer Register EMAC_RBQP Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 ADDR 4 3 2 1 - 0 - 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the used bits. Receive buffer writes also comprise bursts of two words and, as with transmit buffer reads, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification. * ADDR: Receive buffer queue pointer address Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used.
769
6249B-ATARM-14-Dec-06
40.5.6
Transmit Buffer Queue Pointer Register EMAC_TBQP Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 ADDR 4 3 2 1 - 0 - 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list. The lower order bits increment as buffers are used up and wrap to their original values after either 1024 buffers or when the wrap bit of the entry is set. This register can only be written when bit 3 in the transmit status register is low. As transmit buffer reads consist of bursts of two words, it is recommended that bit 2 is always written with zero to prevent a burst crossing a 1K boundary, in violation of section 3.6 of the AMBA specification. * ADDR: Transmit buffer queue pointer address Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.
770
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.7 Receive Status Register EMAC_RSR Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 OVR 25 - 17 - 9 - 1 REC 24 - 16 - 8 - 0 BNA
Register Name: Access Type:
31 - 23 - 15 - 7 -
This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register. * BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit. * REC: Frame Received One or more frames have been received and placed in memory. Cleared by writing a one to this bit. * OVR: Receive Overrun The DMA block was unable to store the receive frame to memory, either because the bus was not granted in time or because a not OK hresp(bus error) was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit.
771
6249B-ATARM-14-Dec-06
40.5.8
Interrupt Status Register EMAC_ISR Read/Write
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. * RCOMP: Receive Complete A frame has been stored in memory. Cleared on read. * RXUBR: Receive Used Bit Read Set when a receive buffer descriptor is read with its used bit set. Cleared on read. * TXUBR: Transmit Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. * TUND: Ethernet Transmit Buffer Underrun The transmit DMA did not fetch frame data in time for it to be transmitted or hresp returned not OK. Also set if a used bit is read mid-frame or when a new transmit queue pointer is written. Cleared on read. * RLE: Retry Limit Exceeded Cleared on read. * TXERR: Transmit Error Transmit buffers exhausted in mid-frame - transmit error. Cleared on read. * TCOMP: Transmit Complete Set when a frame has been transmitted. Cleared on read. * ROVR: Receive Overrun Set when the receive overrun status bit gets set. Cleared on read. * HRESP: Hresp not OK Set when the DMA block sees a bus error. Cleared on read. * PFR: Pause Frame Received Indicates a valid pause has been received. Cleared on a read. * PTZ: Pause Time Zero Set when the pause time register, 0x38 decrements to zero. Cleared on a read.
772
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.9 Interrupt Enable Register EMAC_IER Write-only
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame sent Enable management done interrupt. * RCOMP: Receive Complete Enable receive complete interrupt. * RXUBR: Receive Used Bit Read Enable receive used bit read interrupt. * TXUBR: Transmit Used Bit Read Enable transmit used bit read interrupt. * TUND: Ethernet Transmit Buffer Underrun Enable transmit underrun interrupt. * RLE: Retry Limit Exceeded Enable retry limit exceeded interrupt. * TXERR Enable transmit buffers exhausted in mid-frame interrupt. * TCOMP: Transmit Complete Enable transmit complete interrupt. * ROVR: Receive Overrun Enable receive overrun interrupt. * HRESP: Hresp not OK Enable Hresp not OK interrupt. * PFR: Pause Frame Received Enable pause frame received interrupt. * PTZ: Pause Time Zero Enable pause time zero interrupt.
773
6249B-ATARM-14-Dec-06
40.5.10
Interrupt Disable Register EMAC_IDR Write-only
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame sent Disable management done interrupt. * RCOMP: Receive Complete Disable receive complete interrupt. * RXUBR: Receive Used Bit Read Disable receive used bit read interrupt. * TXUBR: Transmit Used Bit Read Disable transmit used bit read interrupt. * TUND: Ethernet Transmit Buffer Underrun Disable transmit underrun interrupt. * RLE: Retry Limit Exceeded Disable retry limit exceeded interrupt. * TXERR Disable transmit buffers exhausted in mid-frame interrupt. * TCOMP: Transmit Complete Disable transmit complete interrupt. * ROVR: Receive Overrun Disable receive overrun interrupt. * HRESP: Hresp not OK Disable Hresp not OK interrupt. * PFR: Pause Frame Received Disable pause frame received interrupt. * PTZ: Pause Time Zero Disable pause time zero interrupt.
774
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.11 Interrupt Mask Register EMAC_IMR Read-only
30 - 22 - 14 - 6 TXERR 29 - 21 - 13 PTZ 5 RLE 28 - 20 - 12 PFR 4 TUND 27 - 19 - 11 HRESP 3 TXUBR 26 - 18 - 10 ROVR 2 RXUBR 25 - 17 - 9 24 - 16 - 8 - 0 MFD
Register Name: Access Type:
31 - 23 - 15 - 7 TCOMP
1 RCOMP
* MFD: Management Frame sent Management done interrupt masked. * RCOMP: Receive Complete Receive complete interrupt masked. * RXUBR: Receive Used Bit Read Receive used bit read interrupt masked. * TXUBR: Transmit Used Bit Read Transmit used bit read interrupt masked. * TUND: Ethernet Transmit Buffer Underrun Transmit underrun interrupt masked. * RLE: Retry Limit Exceeded Retry limit exceeded interrupt masked. * TXERR Transmit buffers exhausted in mid-frame interrupt masked. * TCOMP: Transmit Complete Transmit complete interrupt masked. * ROVR: Receive Overrun Receive overrun interrupt masked. * HRESP: Hresp not OK Hresp not OK interrupt masked. * PFR: Pause Frame Received Pause frame received interrupt masked. * PTZ: Pause Time Zero Pause time zero interrupt masked.
775
6249B-ATARM-14-Dec-06
40.5.12
PHY Maintenance Register EMAC_MAN Read/Write
30 SOF 29 RW 22 21 20 REGA 12 DATA 19 18 28 27 26 PHYA 17 CODE 11 10 9 8 16 25 24
Register Name: Access Type:
31
23 PHYA 15
14
13
7
6
5
4 DATA
3
2
1
0
* DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. * CODE: Must be written to 10. Reads as written. * REGA: Register Address Specifies the register in the PHY to access. * PHYA: PHY Address * RW: Read/Write 10 is read; 01 is write. Any other value is an invalid PHY management frame * SOF: Start of frame Must be written 01 for a valid frame.
776
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.13 Pause Time Register EMAC_PTR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 PTIME 7 6 5 4 PTIME 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times.
777
6249B-ATARM-14-Dec-06
40.5.14
Hash Register Bottom EMAC_HRB Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR: Bits 31:0 of the hash address register. See "Hash Addressing" on page 755. 40.5.15 Hash Register Top EMAC_HRT Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ADDR: Bits 63:32 of the hash address register. See "Hash Addressing" on page 755.
778
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.16 Specific Address 1 Bottom Register EMAC_SA1B Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 40.5.17 Specific Address 1 Top Register EMAC_SA1T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 7 6 5 4 ADDR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
779
6249B-ATARM-14-Dec-06
40.5.18
Specific Address 2 Bottom Register EMAC_SA2B Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 40.5.19 Specific Address 2 Top Register EMAC_SA2T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 7 6 5 4 ADDR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
780
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.20 Specific Address 3 Bottom Register EMAC_SA3B Read/Write
30 29 28 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
Register Name: Access Type:
31
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 40.5.21 Specific Address 3 Top Register EMAC_SA3T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 7 6 5 4 ADDR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
781
6249B-ATARM-14-Dec-06
40.5.22
Specific Address 4 Bottom Register EMAC_SA4B Read/Write
30 29 28 ADDR 27 26 25 24
Register Name: Access Type:
31
23
22
21
20 ADDR
19
18
17
16
15
14
13
12 ADDR
11
10
9
8
7
6
5
4 ADDR
3
2
1
0
* ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. 40.5.23 Specific Address 4 Top Register EMAC_SA4T Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 ADDR 7 6 5 4 ADDR 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* ADDR The most significant bits of the destination address, that is bits 47 to 32.
782
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.24 Type ID Checking Register EMAC_TID Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 TID 7 6 5 4 TID 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* TID: Type ID checking For use in comparisons with received frames TypeID/Length field.
783
6249B-ATARM-14-Dec-06
40.5.25
User Input/Output Register EMAC_USRIO Read/Write
30 - 22 - 29 - 21 - 28 - 20 - 27 - 19 - 26 - 18 - 25 - 17 - 24 - 16 -
Register Name: Access Type:
31 - 23 -
784
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
15 - 7 - 14 - 6 - 13 - 5 - 12 - 4 - 11 - 3 - 10 - 2 - 9 - 1 CLKEN 8 - 0 RMII
* RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. * CLKEN When set, this bit enables the transceiver input clock. Setting this bit to 0 reduces power consumption when the treasurer is not used.
785
6249B-ATARM-14-Dec-06
786
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 40.5.26.1 Pause Frames Received Register EMAC_PFR Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 FROK 7 6 5 4 FROK 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* FROK: Pause Frames received OK A 16-bit register counting the number of good pause frames received. A good frame has a length of 64 to 1518 (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors. 40.5.26.2 Frames Transmitted OK Register EMAC_FTO Read/Write
30 - 22 29 - 21 28 - 20 FTOK 15 14 13 12 FTOK 7 6 5 4 FTOK 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type:
31 - 23
* FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries.
787
6249B-ATARM-14-Dec-06
40.5.26.3
Single Collision Frames Register EMAC_SCF Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 SCF 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
7
6
5
4 SCF
3
2
1
0
* SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. 40.5.26.4 Multicollision Frames Register EMAC_MCF Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 MCF 7 6 5 4 MCF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.
788
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
40.5.26.5 Frames Received OK Register EMAC_FRO Read/Write
30 - 22 29 - 21 28 - 20 FROK 15 14 13 12 FROK 7 6 5 4 FROK 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16
Register Name: Access Type:
31 - 23
* FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory. A good frame is of length 64 to 1518 bytes (1536 if bit 8 set in network configuration register) and has no FCS, alignment or receive symbol errors. 40.5.26.6 Frames Check Sequence Errors Register EMAC_FCSE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FCSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes.
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40.5.26.7
Alignment Errors Register EMAC_ALE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 ALE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* ALE: Alignment Errors An 8-bit register counting frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. 40.5.26.8 Deferred Transmission Frames Register EMAC_DTF Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 DTF 7 6 5 4 DTF 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit underrun.
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40.5.26.9 Late Collisions Register EMAC_LCOL Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 LCOL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision. 40.5.26.10 Excessive Collisions Register EMAC_EXCOL Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXCOL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions.
791
6249B-ATARM-14-Dec-06
40.5.26.11
Transmit Underrun Errors Register EMAC_TUND Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 TUND 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented. 40.5.26.12 Carrier Sense Errors Register EMAC_CSE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* CSE: Carrier Sense Errors An 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun). Only incremented in half-duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.
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40.5.26.13 Receive Resource Errors Register EMAC_RRE Read/Write
30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 RRE 7 6 5 4 RRE 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
Register Name: Access Type:
31 - 23 - 15
* RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. 40.5.26.14 Receive Overrun Errors Register EMAC_ROVR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 ROVR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun.
793
6249B-ATARM-14-Dec-06
40.5.26.15
Receive Symbol Errors Register EMAC_RSE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RSE 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception. Receive symbol errors are also counted as an FCS or alignment error if the frame is between 64 and 1518 bytes in length (1536 if bit 8 is set in the network configuration register). If the frame is larger, it is recorded as a jabber error. 40.5.26.16 Excessive Length Errors Register EMAC_ELE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* EXL: Excessive Length Errors An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error.
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40.5.26.17 Receive Jabbers Register EMAC_RJA Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RJB 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error. 40.5.26.18 Undersize Frames Register EMAC_USF Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 USF 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* USF: Undersize frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error.
795
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40.5.26.19
SQE Test Errors Register EMAC_STE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 SQER 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. 40.5.26.20 Received Length Field Mismatch Register EMAC_RLE Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 RLFM 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. Checking is enabled through bit 16 of the network configuration register. Frames containing a type ID in bytes 13 and 14 (i.e., length/type ID 0x0600) are not counted as length field errors, neither are excessive length frames.
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6249B-ATARM-14-Dec-06
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41. USB Host Port (UHP)
41.1 Description
The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB "tiered star" topology. The USB Host Port controller is fully compliant with the OpenHCI specification. The standard OHCI USB stack driver can be easily ported to ATMEL's architecture in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses.
41.2
Block Diagram
Figure 41-1. Block Diagram
AHB
HCI Slave Block OHCI Registers Control
List Processor Block ED & TD Regsisters
OHCI Root Hub Registers
Embedded USB v2.0 Full-speed Transceiver USB transceiver USB transceiver DP DM DP DM
Slave
Root Hub and Host SIE
PORT S/M PORT S/M
AHB HCI Master Block Master Data FIFO 64 x 8
uhp_int MCK UHPCK
Access to the USB host operational registers is achieved through the AHB bus slave interface. The OpenHCI host controller initializes master DMA transfers through the ASB bus master interface as follows: * Fetches endpoint descriptors and transfer descriptors * Access to endpoint data from system memory * Access to the HC communication area * Write status and retire transfer Descriptor
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Memory access errors (abort, misalignment) lead to an "UnrecoverableError" indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub's operational registers. Device connection is automatically detected by the USB host port logic. Warning: A pull-down must be connected to DP on the board. Otherwise The USB host will permanently detect a device connection on this port. USB physical transceivers are integrated in the product and driven by the root hub's ports. Over current protection on ports can be activated by the USB host controller. Atmel's standard product does not dedicate pads to external over current protection.
41.3
41.3.1
Product Dependencies
I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller.
41.3.2
Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain).
41.3.3
Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP.
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41.4 Functional Description
Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 41.4.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second communication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. Figure 41-2. USB Host Communication Channels
Device Enumeration Open HCI
Operational Registers Mode HCCA Status Event Frame Int Ratio Control Bulk
Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 ... Interrupt 31 ...
... Done Device Register in Memory Space
Shared RAM
= Transfer Descriptor
= Endpoint Descriptor
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41.4.2
Host Controller Driver
Figure 41-3. USB Host Drivers
User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver
HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware
USB Handling is done through several layers as follows: * Host controller hardware and serial engine: Transmits and receives USB data on the bus. * Host controller driver: Drives the Host controller hardware and handles the USB protocol. * USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface. * Mini driver: Handles device specific commands. * Class driver: Handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver.
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41.5 Typical Connection
Figure 41-4. Board Schematic to Interface UHP Device Controller
5V 0.20A
Type A Connector
10F HDMA or HDMB HDPA or HDPB
100nF
10nF
REXT
REXT 15k 15k
As device connection is automatically detected by the USB host port logic, a pull-down must be connected on DP and DM on the board. Otherwise the USB host permanently detects a device connection on this port. A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT).
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42. USB Device Port (UDP)
42.1 Overview
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Table 42-1. USB Endpoint Description
Mnemonic EP0 EP1 EP2 EP3 EP4 EP5 Dual-Bank No Yes Yes No Yes Yes Max. Endpoint Size 64 64 64 64 256 256 Endpoint Type Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt
Endpoint Number 0 1 2 3 4 5
Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake up to the USB host controller.
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42.2
Block Diagram
Figure 42-1. Block Diagram
Atmel Bridge APB to MCU Bus
USB Device
txoen
MCK UDPCK
U s e r I n t e r f a c e
W r a p p e r
Dual Port RAM FIFO
W r a p p e r
eopn
Serial Interface Engine
12 MHz
txd rxdm rxd rxdp
Embedded USB Transceiver
DP DM
SIE
udp_int
Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain
external_resume
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a 48 MHz clock used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration.
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42.3 Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Properties document. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. One I/O line may be used by the application to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the pullup on DP must be disabled in order to prevent feeding current to the host. The application should disconnect the transceiver, then remove the pullup. 42.3.1 I/O Lines DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral. To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input PIO mode. 42.3.2 Power Management The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain). WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. 42.3.3 Interrupt The USB device interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the USB device interrupt requires programming the AIC before configuring the UDP.
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42.4
Typical Connection
Figure 42-2. Board Schematic to Interface Device Peripheral
PIO 5V Bus Monitoring 27 K
47 K
REXT DDM DDP REXT 330 K 330 K
2
1
3
Type B 4 Connector
42.4.1
USB Device Transceiver The USB device transceiver is embedded in the product. A few discrete components are required as follows: * the application detects all device states as defined in chapter 9 of the USB specification; - VBUS monitoring * to reduce power consumption the host is disconnected * for line termination.
42.4.2
VBUS Monitoring VBUS monitoring is required to detect host connection. VBUS monitoring is done using a standard PIO with internal pullup disabled. When the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pullup resistor. When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to over consumption. A solution is to connect 330 K pulldowns on DP and DM. These pulldowns do not alter DDP and DDM signal integrity.
A termination serial resistor must be connected to DP and DM. The resistor value is defined in the electrical specification of the product (REXT).
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42.5
42.5.1
Functional Description
USB V2.0 Full-speed Introduction The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with a USB device through a set of communication flows.
Figure 42-3. Example of USB V2.0 Full-speed Communication Control
USB Host V2.0 Software Client 1 Software Client 2
Data Flow: Control Transfer Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer
EP0 USB Device 2.0 EP1 Block 1 EP2
Data Flow: Control Transfer Data Flow: Bulk In Transfer Data Flow: Bulk Out Transfer
EP0 USB Device 2.0 EP4 Block 2 EP5
USB Device endpoint configuration requires that in the first instance Control Transfer must be EP0.
Figure 42-4. Example of USB V2.0 Full-speed Communication Control
USB Host V2.0 Software Client
Data Flow: Control Transfer Data Flow: Isochronous or Bulk In Transfer Data Flow: Isochronous or Bulk Out Transfer
EP0 EP1 USB Device 2.0 EP2
USB Device endpoint configuration requires that in the first instance Control Transfer must be EP0.
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The Control Transfer endpoint EP0 is always used when a USB device is first configured (USB v. 2.0 specifications). 42.5.1.1 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device. Table 42-2.
Transfer Control Isochronous Interrupt Bulk
USB Communication Flow
Direction Bidirectional Unidirectional Unidirectional Unidirectional Bandwidth Not guaranteed Guaranteed Not guaranteed Not guaranteed Supported Endpoint Size 8, 16, 32, 64 256 8, 16, 32, 64 8, 16, 32, 64 Error Detection Yes Yes Yes Yes Retrying Automatic No Yes Yes
42.5.1.2
USB Bus Transactions Each transfer results in one or more transactions over the USB bus. There are three kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction
42.5.1.3
USB Transfer Event Definitions As indicated below, transfers are sequential events carried out on the USB bus. Table 42-3. USB Transfer Events * Setup transaction > Data IN transactions > Status OUT transaction
Control Transfers(1) (3)
* Setup transaction > Data OUT transactions > Status IN transaction * Setup transaction > Status IN transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction * Data IN transaction > Data IN transaction * Data OUT transaction > Data OUT transaction
Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes:
1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake.
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A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. Figure 42-5. Control Read and Write Sequences
Setup Stage Data Stage Status Stage
Control Read
Setup TX
Data OUT TX
Data OUT TX
Status IN TX
Setup Stage
Data Stage
Status Stage
Control Write
Setup TX
Data IN TX
Data IN TX
Status OUT TX
Setup Stage
Status Stage
No Data Control
Notes:
Setup TX
Status IN TX
1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data).
42.5.2 42.5.2.1
Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: * The USB device automatically acknowledges the setup packet * RXSETUP is set in the UDP_ CSRx register * An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint.
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Thus, firmware must detect the RXSETUP polling the UDP_ CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. Figure 42-6. Setup Transaction Followed by a Data OUT Transaction
Setup Received Setup Handled by Firmware Data Out Received
USB Bus Packets
Setup PID
Data Setup
ACK PID
Data OUT PID
Data OUT
NAK PID
Data OUT PID
Data OUT
ACK PID
RXSETUP Flag
Interrupt Pending
Set by USB Device
Cleared by Firmware Set by USB Device Peripheral
RX_Data_BKO (UDP_CSRx)
FIFO (DPR) Content
XX
Data Setup
XX
Data OUT
42.5.2.2
Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes.
42.5.2.3
Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint's UDP_ CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint's FIFO, writing zero or more byte values in the endpoint's UDP_ FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint's UDP_ CSRx register. 4. The application is notified that the endpoint's FIFO has been released by the USB device when TXCOMP in the endpoint's UDP_ CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint's FIFO, writing zero or more byte values in the endpoint's UDP_ FDRx register, 6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint's UDP_ CSRx register. 7. The application clears the TXCOMP in the endpoint's UDP_ CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set.
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Warning: TX_COMP must be cleared after TX_PKTRDY has been set.
Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer.
Figure 42-7. Data IN Transfer for Non Ping-pong Endpoint
Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus
USB Bus Packets
Data IN PID
Data IN 1
ACK PID
Data IN PID
NAK PID
Data IN PID
Data IN 2
ACK PID
TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Set by the firmware Cleared by Hw Interrupt Pending Payload in FIFO Cleared by Firmware DPR access by the firmware FIFO (DPR) Content Data IN 1 Load In Progress DPR access by the hardware Data IN 2 Cleared by Firmware
Interrupt Pending TXCOMP Flag (UDP_CSRx)
42.5.2.4
Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 42-8. Bank Swapping Data IN Transfer for Ping-pong Endpoints
Microcontroller Write Bank 0 Endpoint 1 USB Device Read USB Bus
1st Data Payload
Read and Write at the Same Time
2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1
Data IN Packet 1st Data Payload
Data IN Packet 2nd Data Payload
Bank 0 Endpoint 1
Data IN Packet 3rd Data Payload
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When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint's UDP_ CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint's UDP_ FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint's UDP_ CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint's UDP_ FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint's UDP_ CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint's UDP_ CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 42-9. Data IN Transfer for Ping-pong Endpoint
Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1
USB Bus Packets
Data IN PID
Data IN
ACK PID
Data IN PID
Data IN
ACK PID
TXPKTRDY Flag (UDP_MCSRx)
Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx)
Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device
Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device
Interrupt Cleared by Firmware
FIFO (DPR) Written by Microcontroller Bank 0
Read by USB Device
Written by Microcontroller
FIFO (DPR) Bank 1
Written by Microcontroller
Read by USB Device
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth.
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Warning: TX_COMP must be cleared after TX_PKTRDY has been set. 42.5.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 42.5.2.6 Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint's UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's UDP_ CSRx register. 5. The microcontroller carries out data received from the endpoint's memory to its memory. Data received is available by reading the endpoint's UDP_ FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's UDP_ CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 42-10. Data OUT Transfer for Non Ping-pong Endpoints
Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload
USB Bus Packets
Data OUT PID
Data OUT 1
ACK PID
Data OUT2 PID
Data OUT2
NAK PID
Data OUT PID
Data OUT2
ACK PID
RX_DATA_BK0 (UDP_CSRx)
Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device
FIFO (DPR) Content
Data OUT 1 Written by USB Device
Data OUT 1 Microcontroller Read
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.
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42.5.2.7
Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 42-11. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus
Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1
Bank 1 Endpoint 1
Data IN Packet nd Data Payload 2
Bank 0 Endpoint 1
Data IN Packet 3rd Data Payload
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint's FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint's UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint's UDP_ CSRx register. 6. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is made available by reading the endpoint's UDP_ FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint's UDP_ CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint's UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set.
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10. The microcontroller transfers out data received from the endpoint's memory to the microcontroller's memory. Data received is available by reading the endpoint's UDP_ FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint's UDP_ CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 42-12. Data OUT Transfer for Ping-pong Endpoint
Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload
USB Bus Packets
Data OUT PID
Data OUT 1
ACK PID
Data OUT PID
Data OUT 2
ACK PID
Data OUT PID
Data OUT 3
A P
RX_DATA_BK0 Flag (UDP_CSRx)
Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0
Cleared by Firmware
RX_DATA_BK1 Flag (UDP_CSRx)
Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1
Cleared by Firmware Interrupt Pending
FIFO (DPR) Bank 0
Data OUT1 Write by USB Device
Data OUT 1 Read By Microcontroller
Data OUT 3 Write In Progress
FIFO (DPR) Bank 1
Data OUT 2 Write by USB Device
Data OUT 2 Read By Microcontroller
Note:
An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 42.5.2.8 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) * A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) * To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet:
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1. The microcontroller sets the FORCESTALL flag in the UDP_ CSRx endpoint's register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 42-13. Stall Handshake (Data IN Transfer)
USB Bus Packets Data IN PID Stall PID
Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device
Figure 42-14. Stall Handshake (Data OUT Transfer)
USB Bus Packets Data OUT PID Data OUT Stall PID
FORCESTALL
Set by Firmware Interrupt Pending
STALLSENT Set by USB Device
Cleared by Firmware
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42.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 42-15. USB Device State Diagram
Attached
Hub Reset or Deconfigured
Hub Configured
Bus Inactive
Powered
Bus Activity Power Interruption
Suspended
Reset
Bus Inactive
Default
Reset Address Assigned Bus Inactive Bus Activity
Suspended
Address
Bus Activity Device Deconfigured Device Configured Bus Inactive
Suspended
Configured
Bus Activity
Suspended
Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 A on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host.
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42.5.3.1
Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 K resistors.
42.5.3.2
Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 K pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 K pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 K resistor to 3.3V and DM is pulled down by the 15 K resistor of the host. To enable integrated pullup, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pullup connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled.
42.5.3.3
From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must: * Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. * Configure the interrupt mask register which has been reset by the USB reset detection * Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset.
42.5.3.4
From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register.
42.5.3.5
From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the
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EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 42.5.3.6 Entering in Suspend State When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 42.5.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register. 42.5.3.8 Sending a Device Remote Wakeup In Suspend state it is possible to wake up the host sending an external resume. * The device must wait at least 5 ms after being entered in suspend before sending an external resume. * The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host. * The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DM at 3.3V and DP tied to GND), it is possible to use a transistor to connect a pullup on DM. The K state is obtained by disabling the pullup on DP and enabling the pullup on DM. This should be under the control of the application.
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Figure 42-16. Board Schematic to Drive a K State
3V3
PIO 0: Force Wake UP (K State) 1: Normal Mode 1.5 K
DM
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42.6 USB Device Port (UDP) User Interface
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. Table 42-4.
Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 . . . See Note: (1) 0x050 . . . See Note: (2) 0x070 0x074 0x078 - 0xFC Notes:
UDP Memory Map
Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint 0 Control and Status Register . . . Endpoint 5 Control and Status Register Endpoint 0 FIFO Data Register . . . Endpoint 5 FIFO Data Register Reserved Transceiver Control Register Reserved UDP_ FDR5 - UDP_ TXVC -
(3)
Name UDP_ FRM_NUM UDP_ GLB_STAT UDP_ FADDR - UDP_ IER UDP_ IDR UDP_ IMR UDP_ ISR UDP_ ICR - UDP_ RST_EP - UDP_CSR0
Access Read Read/Write Read/Write - Write Write Read Read Write - Read/Write - Read/Write
Reset State 0x0000_0000 0x0000_0000 0x0000_0100 -
0x0000_1200 0x0000_XX00
-
- 0x0000_0000
UDP_CSR5 UDP_ FDR0
Read/Write Read/Write
0x0000_0000 0x0000_0000
Read/Write - Read/Write -
0x0000_0000 - 0x0000_0000 -
1. The addresses of the UDP_ CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1). 2. The addresses of the UDP_ FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1). 3. See Warning above the "UDP Memory Map" on this page.
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42.6.1
UDP Frame Number Register UDP_ FRM_NUM Read-only
30 --22 - 14 - 6 29 --21 - 13 - 5 28 --20 - 12 - 4 FRM_NUM 27 --19 - 11 - 3 26 --18 - 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8
Register Name: Access Type:
31 --23 - 15 - 7
2
0
* FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). * FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. * FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP.
Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.
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42.6.2 UDP Global State Register UDP_ GLB_STAT Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 CONFG 24 - 16 - 8 - 0 FADDEN
Register Name: Access Type:
31 - 23 - 15 - 7 -
This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. * FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_ FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. * CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details.
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42.6.3
UDP Function Address Register UDP_ FADDR Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 FADD 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 FEN 0
Register Name: Access Type:
31 - 23 - 15 - 7 -
* FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. * FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host.
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42.6.4 UDP Interrupt Enable Register UDP_ IER Write-only
30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 - 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7
* EP0INT: Enable Endpoint 0 Interrupt * EP1INT: Enable Endpoint 1 Interrupt * EP2INT: Enable Endpoint 2Interrupt * EP3INT: Enable Endpoint 3 Interrupt * EP4INT: Enable Endpoint 4 Interrupt * EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. * RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. * RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt. * SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. * WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt.
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42.6.5
UDP Interrupt Disable Register UDP_ IDR Write-only
30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 - 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7
* EP0INT: Disable Endpoint 0 Interrupt * EP1INT: Disable Endpoint 1 Interrupt * EP2INT: Disable Endpoint 2 Interrupt * EP3INT: Disable Endpoint 3 Interrupt * EP4INT: Disable Endpoint 4 Interrupt * EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. * RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. * RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. * SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt * WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt.
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42.6.6 UDP Interrupt Mask Register UDP_ IMR Read-only
30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12(1) - 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 - 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7
Note:
1. Bit 12 of UDP_IMR cannot be masked and is always read at 1.
* EP0INT: Mask Endpoint 0 Interrupt * EP1INT: Mask Endpoint 1 Interrupt * EP2INT: Mask Endpoint 2 Interrupt * EP3INT: Mask Endpoint 3 Interrupt * EP4INT: Mask Endpoint 4 Interrupt * EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. * RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. * RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. * SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. * WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled.
Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_ IMR is enabled.
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42.6.7
UDP Interrupt Status Register UDP_ ISR Read-only
30 - 22 - 14 - 6 29 - 21 - 13 WAKEUP 5 EP5INT 28 - 20 - 12 ENDBUSRES 4 EP4INT 27 - 19 - 11 SOFINT 3 EP3INT 26 - 18 - 10 - 2 EP2INT 25 - 17 - 9 RXRSM 1 EP1INT 24 - 16 - 8 RXSUSP 0 EP0INT
Register Name: Access Type:
31 - 23 - 15 - 7
* EP0INT: Endpoint 0 Interrupt Status * EP1INT: Endpoint 1 Interrupt Status * EP2INT: Endpoint 2 Interrupt Status * EP3INT: Endpoint 3 Interrupt Status * EP4INT: Endpoint 4 Interrupt Status * EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_ CSR0 bit. * RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. * RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ ICR register. * SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints.
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* ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. * WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ ICR register.
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42.6.8
UDP Interrupt Clear Register UDP_ ICR Write-only
30 - 22 - 14 - 6 - 29 - 21 - 13 WAKEUP 5 - 28 - 20 - 12 ENDBUSRES 4 - 27 - 19 - 11 SOFINT 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 RXRSM 1 - 24 - 16 - 8 RXSUSP 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
* RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. * RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. * SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. * ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. * WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt.
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42.6.9 UDP Reset Endpoint Register UDP_ RST_EP Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 EP5 28 - 20 - 12 - 4 EP4 27 - 19 - 11 - 3 EP3 26 - 18 - 10 - 2 EP2 25 - 17 - 9 - 1 EP1 24 - 16 - 8 - 0 EP0
Register Name: Access Type:
31 - 23 - 15 - 7
* EP0: Reset Endpoint 0 * EP1: Reset Endpoint 1 * EP2: Reset Endpoint 2 * EP3: Reset Endpoint 3 * EP4: Reset Endpoint 4 * EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_ CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_ CSRx register.
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42.6.10
UDP Endpoint Control and Status Register UDP_ CSRx [x = 0..5] Read/Write
30 - 22 29 - 21 28 - 20 RXBYTECNT 27 - 19 26 25 RXBYTECNT 17 24
Register Name: Access Type:
31 - 23
18
16
15 EPEDS 7 DIR
14 - 6 RX_DATA_ BK1
13 - 5 FORCE STALL
12 - 4 TXPKTRDY
11 DTGLE 3 STALLSENT ISOERROR
10
9 EPTYPE 1 RX_DATA_ BK0
8
2 RXSETUP
0 TXCOMP
WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared.
//! Clear flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_clr_flag(pInterface, endpoint, flags) { \ while (pInterface->UDP_CSR[endpoint] & (flags)) \ pInterface->UDP_CSR[endpoint] &= ~(flags); \ } //! Set flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_set_flag(pInterface, endpoint, flags) { \ while ( (pInterface->UDP_CSR[endpoint] & (flags)) != (flags) ) \ pInterface->UDP_CSR[endpoint] |= (flags); \ }
* TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. * RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0.
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When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. * RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_ FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. * STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints) / ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. * TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Can be set to one to send the FIFO data. 1 = The data is waiting to be sent upon reception of token IN. Write: 0 = No effect.
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1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_ FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. * FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. * RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO's Bank 1. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. * DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_ CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. * EPTYPE[2:0]: Endpoint Type Read/Write
000 001 101 010 Control Isochronous OUT Isochronous IN Bulk OUT
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Read/Write
110 011 111 Bulk IN Interrupt OUT Interrupt IN
* DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. * EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. * RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_ FDRx register.
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42.6.11
UDP FIFO Data Register UDP_ FDRx [x = 0..5] Read/Write
30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FIFO_DATA 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
Register Name: Access Type:
31 - 23 - 15 - 7
* FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_ CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information.
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42.6.12 UDP Transceiver Control Register UDP_ TXVC Read/Write
30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 PUON 1 - 24 - 16 - 8 TXVDIS 0 -
Register Name: Access Type:
31 - 23 - 15 - 7 -
WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. * TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. NOTE: If the USB pullup is not connected on DP, the user should not write in any UDP register other than the UDP_ TXVC register. This is because if DP and DM are floating at 0, or pulled down, then SE0 is received by the device with the consequence of a USB Reset. * PUON: Pullup On 0: The 1.5K integrated pullup on DP is disconnected. 1: The 1.5 K integrated pullup on DP is connected.
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43. LCD Controller (LCDC)
43.1 Description
The LCD Controller consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN displays to generate up to 4096 colors. The LCD Controller has a display input buffer (FIFO) to allow a flexible connection of the external AHB master interface, and a lookup table to allow palletized display configurations. The LCD Controller is programmable in order to support many different requirements such as resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing. The LCD Controller is connected to the ARM Advanced High Performance Bus (AHB) as a master for reading pixel data. However, the LCD Controller interfaces with the AHB as a slave in order to configure its registers.
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43.2
Block Diagram
Figure 43-1. LCD Macrocell Block Diagram
AHB MASTER
AHB SLAVE
DMA Controller
SPLIT
AHB IF CFG
AHB SLAVE DMA Data Dvalid Dvalid
CH-U
Upper Push
CH-L
Lower Push
CTRL
Input Interface
LCD Controller Core
FIFO
Configuration IF
CFG
AHB SLAVE
SERIALIZER
DATAPATH
LUT Mem Interface
PALETTE
LUT Mem Interface FIFO Mem Interface
DITHERING
Control Interface
FIFO MEM OUTPUT SHIFTER
LUT MEM
Timegen
LCDD
DISPLAY IF Control signals
Display
PWM
DISPLAY IF
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43.3 I/O Lines Description
I/O Lines Description
Description Contrast control signal Line synchronous signal (STN) or Horizontal synchronous signal (TFT) LCD clock signal (STN/TFT) Frame synchronous signal (STN) or Vertical synchronization signal (TFT) STN AC bias signal for the driver or Data enable signal (TFT) LCD Data Bus output Type Output Output Output Output Output Output
Table 43-1.
Name LCDCC LCDHSYNC LCDDOTCK LCDVSYNC LCDDEN LCDD[23:0]
43.4
43.4.1
Product Dependencies
I/O Lines The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCD Controller are not used by the application, they can be used for other purposes by the PIO Controller.
43.4.2
Power Management The LCD Controller is not continuously clocked. The user must first enable the LCD Controller clock in the Power Management Controller before using it (PMC_PCER). Interrupt Sources The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC.
43.4.3
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43.5
Functional Description
The LCD Controller consists of two main blocks (Figure 43-1 on page 842), the DMA controller and the LCD controller core (LCDC core). The DMA controller reads the display data from an external memory through a AHB master interface. The LCD controller core formats the display data. The LCD controller core continuously pumps the pixel data into the LCD module via the LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK, LCDDEN, LCDHSYNC, and LCDVSYNC signals.
43.5.1 43.5.1.1
DMA Controller Configuration Block The configuration block is a set of programmable registers that are used to configure the DMA controller operation. These registers are written via the AHB slave interface. Only word access is allowed. For details on the configuration registers, see "LCD Controller (LCDC) User Interface" on page 869.
43.5.1.2
AHB Interface This block generates the AHB transactions. It generates undefined-length incrementing bursts as well as 4- ,8- or 16-beat incrementing bursts. The size of the transfer can be configured in the BRSTLN field of the DMAFRMCFG register. For details on this register, see "DMA Frame Configuration Register" on page 874. Channel-U This block stores the base address and the number of words transferred for this channel (frame in single scan mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame signal. It has two pointers, the base address and the number of words to transfer. When the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. When the module receives the new_frame signal, it also reloads the base address with the base address programmed by the host. The size of the frame/panel can be programmed in the FRMSIZE field of the DMAFRMCFG Register. This size is calculated as follows: X_size*Y_size Frame_size = ------------------------------------32 X_size = ((LINESIZE+1)*Bpp+PIXELOFF)/32 Y_size = (LINEVAL+1)
43.5.1.3
* LINESIZE is the horizontal size of the display in pixels, minus 1, as programmed in the LINESIZE field of the LCDFRMCFG register of the LCD Controller. * Bpp is the number of bits per pixel configured. * PIXELOFF is the pixel offset for 2D addressing, as programmed in the DMA2DCFG register. Applicable only if 2D addressing is being used.
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* LINEVAL is the vertical size of the display in pixels, minus 1, as programmed in the LINEVAL field of the LCDFRMCFG register of the LCD Controller.
Note: X_size is calculated as an up-rounding of a division by 32. (This can also be done adding 31 to the dividend before using an integer division by 32). When using the 2D-addressing mode (see "2D Memory Addressing" on page 866), it is important to note that the above calculation must be executed and the FRMSIZE field programmed with every movement of the displaying window, since a change in the PIXELOFF field can change the resulting FRMSIZE value.
43.5.1.4
Channel-L This block has the same functionality as Channel-U, but for the Lower Panel in dual scan mode only.
43.5.1.5
Control This block receives the request signals from the LCDC core and generates the requests for the channels.
43.5.2 43.5.2.1
LCD Controller Core Configuration Block The configuration block is a set of programmable registers that are used to configure the LCDC core operation. These registers are written via the AHB slave interface. Only word access is allowed. The description of the configuration registers can be found in "LCD Controller (LCDC) User Interface" on page 869.
43.5.2.2
Datapath The datapath block contains five submodules: FIFO, Serializer, Palette, Dithering and Shifter. The structure of the datapath is shown in Figure 43-2.
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Figure 43-2. Datapath Structure
Input Interface
FIFO
Serializer Configuration IF
Palette
Control Interface Dithering
Output Shifter
Output Interface
This module transforms the data read from the memory into a format according to the LCD module used. It has four different interfaces: the input interface, the output interface, the configuration interface and the control interface. * The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus and two push lines that are used by the DMA controller to fill the FIFOs. * The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface). * The configuration interface connects the datapath with the configuration block. It is used to select between the different datapath configurations. * The control interface connects the datapath with the timing generation block. The main control signal is the data-request signal, used by the timing generation module to request new data from the datapath. The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data is available at the output of the datapath. The parameter cycles_per_data is the minimum number of LCDC Core clock cycles between two consecutive data at the output interface.
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These parameters are different for the different configurations of the LCD Controller and are shown in Table 43-2. Table 43-2. Datapath Parameters
Configuration DISTYPE TFT STN Mono STN Mono STN Mono STN Mono STN Color STN Color STN Color STN Color Single Single Dual Dual Single Single Dual Dual 4 8 8 16 4 8 8 16 SCAN IFWIDTH initial_latency 9 13 17 17 25 11 12 14 15 cycles_per_data 1 4 8 8 16 2 3 4 6
FIFO The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to be used in Dual Scan configuration that are configured as a single FIFO when used in single scan configuration. The size of the FIFOs allows a wide range of architectures to be supported. The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO register. The LCDC core will request a DMA transfer when the number of words in each FIFO is less than FIFOTH words. To avoid overwriting in the FIFO and to maximize the FIFO utilization, the FIFOTH should be programmed with: FIFOTH = 2048 - (2 x DMA_BURST_LENGTH + 3) where: * 2048 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode. * DMA_burst_length is the burst length of the transfers made by the DMA Serializer This block serializes the data read from memory. It reads words from the FIFO and outputs pixels (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both bigendian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register. The organization of the pixel data in the memory depends on the configuration and is shown in Table 43-3 and Table 43-4.
Note: For a color depth of 24 bits per pixel there are two different formats supported: packed and unpacked. The packed format needs less memory but has some limitations when working in 2D addressing mode (See "2D Memory Addressing" on page 866.).
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Table 43-3.
Mem Addr
Little Endian Memory Organization
0x3 0x2 0x1 8 8 4 2 1 0 0 2 3 5 4 1 2 7 7 3 1 0 6 6 5 5 2 4 4 0x0 3 3 1 0 2 2 1 1 0 0 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 1bpp Pixel 2bpp Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp Pixel 24bpp Pixel 24bpp Pixel 24bpp 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 15 7 3 1 14 13 6 12 11 5 2 10 9 4 8 7 3 6 5
Table 43-4.
Mem Addr
Big Endian Memory Organization
0x3 0x2 0x1 8 7 6 5 4 0x0 3 2 1 0
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 1bpp Pixel 2bpp Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp unpacked not used 0 4 2 3 1 0 0 0 0 0 1 2 1 3 4 2 1 5 6 3 7 8 4 2 1 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 5 6 3 7 8 4 2 1 9 10 5 11 12 6 3 13 14 7 15
0
1
2
5
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Table 43-5.
Mem Addr
WindowsCE Pixel Memory Organization
0x3 0x2 0x1 8 7 6 1 0 0 0 0 5 2 1 4 3 0x0 3 4 3 1 2 5 1 6 3 0 7
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 1bpp Pixel 2bpp Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp unpacked not used 0 3 2 1 24 25 26 27 28 29 30 31 16 17 18 19 20 21 22 23 8 12 6 3 1 13 14 7 15 8 4 2 9 10 5 11 4 2 1 9
10 11 12 13 14 15 0 5 6 3 7
0
1
2
Palette This block is used to generate the pixel gray or color information in palletized configurations. The different modes with the palletized/non-palletized configuration can be found in Table 43-6. In these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. The corresponding entry in the lookup table contains the color or gray shade information for the pixel. Table 43-6. Palette Configurations
Configuration DISTYPE TFT TFT STN Mono STN Mono STN Color STN Color PIXELSIZE 1, 2, 4, 8 16, 24 1, 2 4 1, 2, 4, 8 16 Palette Palletized Non-palletized Palletized Non-palletized Palletized Non-palletized
The lookup table can be accessed by the host in R/W mode to allow the host to program and check the values stored in the palette. It is mapped in the LCD controller configuration memory map. The LUT is mapped as 16-bit half-words aligned at word boundaries, only word write access is allowed (the 16 MSB of the bus are not used). For the detailed memory map, see Table 43-13 on page 869.
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The lookup table contains 256 16-bit wide entries. The 256 entries are chosen by the programmer from the 216 possible combinations. For the structure of each LUT entry, see Table 43-7. Table 43-7.
Address 00 01 ... FE FF Intensity_bit_254 Intensity_bit_255 Blue_value_254[4:0] Blue_value_255[4:0] Green_value_254[4:0] Green_value_255[4:0] Red_value_254[4:0] Red_value_255[4:0] Intensity_bit_0 Intensity_bit_1 Blue_value_0[4:0] Blue_value_1[4:0]
Lookup Table Structure in the Memory
Data Output [15:0] Green_value_0[4:0] Green_value_1[4:0] Red_value_0[4:0] Red_value_1[4:0]
In STN Monochrome, only the four most significant bits of the red value are used (16 gray shades). In STN Color, only the four most significant bits of the blue, green and red value are used (4096 colors). In TFT mode, all the bits in the blue, green and red values are used (32768 colors). In this mode, there is also a common intensity bit that can be used to double the possible colors. This bit is the least significant bit of each color component in the LCDD interface (LCDD[18], LCDD[10], LCDD[2]). The LCDD unused bits are tied to 0 when TFT palletized configurations are used (LCDD[17:16], LCDD[9:8], LCDD[1:0]). Dithering The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Control method. The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the display an appearance of multiple shades. In order to reduce the flicker noise caused by turning on and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. This algorithm is expressed in terms of Dithering Pattern registers (DP_i) and considers not only the pixel gray level number, but also its horizontal coordinate. Table 43-8 shows the correspondences between the gray levels and the duty cycle. Table 43-8.
Gray Level 15 14 13 12 11 10 9 8 7
Dithering Duty Cycle
Duty Cycle 1 6/7 4/5 3/4 5/7 2/3 3/5 4/7 1/2 Pattern Register DP6_7 DP4_5 DP3_4 DP5_7 DP2_3 DP3_5 DP4_7 ~DP1_2
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Table 43-8.
Gray Level 6 5 4 3 2 1 0
Dithering Duty Cycle
Duty Cycle 3/7 2/5 1/3 1/4 1/5 1/7 0 Pattern Register ~DP4_7 ~DP3_5 ~DP2_3 ~DP3_4 ~DP4_5 ~DP6_7 -
The duty cycles for gray levels 0 and 15 are 0 and 1, respectively. The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The dithering pattern for the first pair member is the inversion of the one for the second. The DP_i registers contain a series of 4-bit patterns. The (3-m)th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame. The operation is shown by the examples below. Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is DP3_5 ="1010 0101 1010 0101 1111". The output sequence obtained in the data output for monochrome mode is shown in Table 43-9. Table 43-9.
Frame Number N N+1 N+2 N+3 N+4 N+5 N+6 N+7 ...
Dithering Algorithm for Monochrome Mode
Pattern 1010 0101 1010 0101 1111 1010 0101 1010 ... Pixel a ON OFF ON OFF ON ON OFF ON ... Pixel b OFF ON OFF ON ON OFF ON OFF ... Pixel c ON OFF ON OFF ON ON OFF ON ... Pixel d OFF ON OFF ON ON OFF ON OFF ...
Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be displayed sending the color components {R0, G0, B0} to the display. Pixel p1 will be displayed sending the color components {R1, G1, B1}. Suppose that the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color components of both pixels, with the dithering pattern to apply to all of them being DP2_3 = "1101 1011 0110". Table 43-10 shows the output sequence in the data output bus for single scan configurations. (In
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Dual Scan Configuration, each panel data bus acts like in the equivalent single scan configuration.) Table 43-10. Dithering Algorithm for Color Mode
Frame N N N N N N ... N+1 N+1 N+1 N+1 N+1 N+1 ... N+2 N+2 N+2 N+2 N+2 N+2 ... Note: Signal red_data_0 green_data_0 blue_data_0 red_data_1 green_data_1 blue_data_1 ... red_data_0 green_data_0 blue_data_0 red_data_1 green_data_1 blue_data_1 ... red_data_0 green_data_0 blue_data_0 red_data_1 green_data_1 blue_data_1 ... Shadow Level 1010 1010 1010 1010 1010 1010 ... 1010 1010 1010 1010 1010 1010 ... 1010 1010 1010 1010 1010 1010 ... Bit used 3 2 1 0 3 2 ... 3 2 1 0 3 2 ... 3 2 1 0 3 2 ... Dithering Pattern 1101 1101 1101 1101 1101 1101 ... 1011 1011 1011 1011 1011 1011 ... 0110 0110 0110 0110 0110 0110 ... 4-bit LCDD LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCDD[3] LCDD[2] ... LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCDD[3] LCDD[2] ... LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCDD[3] LCDD[2] ... 8-bit LCDD LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] ... LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] ... LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] ... Output R0 G0 b0 R1 G1 B1 ... R0 g0 B0 R1 G1 b1 ... r0 G0 B0 r1 g1 B1 ...
Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF. gi = green pixel component OFF. bi = blue pixel component OFF.
Shifter The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output interface. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LDCCON3 register. The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCANMODE field selects between single and dual scan modes; in TFT mode, only single scan is supported. The IFWIDTH field configures the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only). For a more detailed description of the fields, see "LCD Controller (LCDC) User Interface" on page 869. For a more detailed description of the LCD Interface, see "LCD Interface" on page 857.
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43.5.2.3 Timegen The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, used by the LCD module. This block is programmable in order to support different types of LCD modules and obtain the output clock signals, which are derived from the LCDC Core clock.
The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in Table 43-11. f LCDC_clock f LCDDOTCK = -------------------------------2 x CLKVAL The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2 register: * Always Active (used with TFT LCD Modules) * Active only when data is available (used with STN LCD Modules)
Table 43-11. Minimum LCDDOTCK Period in LCDC Core Clock Cycles
Configuration DISTYPE TFT STN Mono STN Mono STN Mono STN Mono STN Color STN Color STN Color STN Color Single Single Dual Dual Single Single Dual Dual 4 8 8 16 4 8 8 16 SCAN IFWIDTH LCDDOTCK Period 1 4 8 8 16 2 2 4 6
The LCDDEN signal indicates valid data in the LCD Interface. After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be displayed on the panel. The following timing parameters can be configured: * Vertical to Horizontal Delay (VHDLY): The delay between begin_of_line and the generation of LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to (VHDLY+1) LCDDOTCK cycles.
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* Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles. * Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles. * Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+1) LCDDOTCK cycles. There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by the initial latency of the datapath. The total delay in LCDC clock cycles must be higher than or equal to the latency column in Table 43-2 on page 847. This limitation is given by the following formula: Equation 1 ( VHDLY + HPW + HBP + 3 ) x PCLK_PERIOD DPATH_LATENCY where: * VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers * PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles * DPATH_LATENCY is the datapath latency of the configuration, given in Table 43-2 on page 847 The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at the top of the display. The timing of this signal depends on the type of LCD: STN or TFT LCD. In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode, this signal is synchronized with the first active LCDDOTCK rising edge in a line. In TFT mode, the high phase of this signal starts at the beginning of the first line. The following timing parameters can be selected: * Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register. The pulse width is equal to (VPW+1) lines. * Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in STN Mode. * Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of LCDTIM2 register. The number of inactive lines is equal to VFP. This field should be programmed with 0 in STN mode. There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the LCDFRMCFG: * HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1. * LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The minimum value of this parameter is 1. Figure 43-3, Figure 43-4 and Figure 43-5 show the timing of LCDDOTCK, LCDDEN, LCDHSYNC and LCDVSYNC signals:
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Figure 43-3. STN Panel Timing, CLKMOD 0
Frame Period LCDVSYNC
LCDHSYNC LCDDEN LCDDOTCK LCDD
Line Period VHDLY+ LCDVSYNC HPW+1 HBP+1 HOZVAL+1 HFP+1
LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK
Figure 43-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1
Frame Period
(VPW+1) Lines LCDVSYNC Vertical Back Porch = VBP Lines VHDLY+1 LCDHSYNC LCDDEN LCDDOTCK LCDD Vertical Fron t Porch = VFP Lines
Line Period VHDLY+1 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK HPW+1 HBP+1 HOZVAL+1 HFP+1
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Figure 43-5. TFT Panel Timing (Line Expanded View), CLKMOD=1
Line Period VHDLY+1 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK HPW+1 HBP+1 HOZVAL+1 HFP+1
Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation: VHDLY + HPW + HBP + HOZVAL + HFP + 5 1 --------------------------- = -------------------------------------------------------------------------------------------------------------------- ( VBP + LINEVAL + VFP + 1 ) f LCDDOTCK f LCDVSYNC where: * HOZVAL determines de number of LCDDOTCK cycles per line * LINEVAL determines the number of LCDHSYNC cycles per frame, according to the expressions shown below: In STN Mode: HOZVAL = Horizontal_display_size - 1 -------------------------------------------------------------Number_data_lines LINEVAL = Vertical_display_size - 1
In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. In color mode, Horizontal_display_size equals three times the number of horizontal pixels. In TFT Mode: HOZVAL = Horizontal_display_size - 1 LINEVAL = Vertical_display_size - 1 The frame rate equation is used first without considering the clock periods added at the end beginning or at the end of each line to determine, approximately, the LCDDOTCK rate: f lcd_pclk = ( HOZVAL + 5 ) x ( f lcd_vsync x ( LINEVAL + 1 ) )
With this value, the CLKVAL is fixed, as well as the corresponding LCDDOTCK rate. Then select VHDLY, HPW and HBP according to the type of LCD used and "Equation 1" on page 854. Finally, the frame rate is adjusted to 70 Hz - 75 Hz with the HFP value:
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1 HFP = f LCDDOTCK x -------------------------------------------------------------------------------------------------------------- - ( VHDLY + VPW + VBP + HOZVAL + 5 ) f LCDVSYNC x ( LINEVAL + VBP + VFP + 1 ) The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The LINECNT field decreases by one unit at each falling edge of LCDHSYNC. 43.5.2.4 Display This block is used to configure the polarity of the data and control signals. The polarity of all clock signals can be configured by LCDCON2[12:8] register setting. This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and off by software the LCD module.
This signal is controlled by the PWRCON register and respects the number of frames configured in the GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the write access to LCD_PWR field (PWRCON[0]) and the activation/deactivation of lcd_pwr signal. The minimum value for the GUARD_TIME field is one frame. This gives the DMA Controller enough time to fill the FIFOs before the start of data transfer to the LCD. 43.5.2.5 PWM This block generates the LCD contrast control signal (LCDCC) to make possible the control of the display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog voltage with a simple passive filter. The PWM module has a free-running counter whose value is compared against a compare register (CONSTRAST_VAL register). If the value in the counter is less than that in the register, the output brings the value of the polarity (POL) bit in the PWM control register: CONTRAST_CTR. Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated. Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles. Thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) x VDD can be obtained (for the positive polarity case, or between (1/256) x VDD and VDD for the negative polarity case). Other voltage values can be obtained by adding active external circuitry. For PWM mode, the frequency of the counter can be adjusted to four different values using field PS of CONTRAST_CTR register. 43.5.3 LCD Interface The LCD Controller interfaces with the LCD Module through the LCD Interface (Table 43-12 on page 863). The Controller supports the following interface configurations: 24-bit TFT single scan, 16-bit STN Dual Scan Mono (Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit single scan Mono (Color). A 4-bit single scan STN display uses 4 parallel data lines to shift data to successive single horizontal lines one at a time until the entire frame has been shifted and transferred. The 4 LSB pins of LCD Data Bus (LCDD [3:0]) can be directly connected to the LCD driver; the 20 MSB pins (LCDD [23:4]) are not used. An 8-bit single scan STN display uses 8 parallel data lines to shift data to successive single horizontal lines one at a time until the entire frame has been shifted and transferred. The 8 LSB pins 857
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of LCD Data Bus (LCDD [7:0]) can be directly connected to the LCD driver; the 16 MSB pins (LCDD [23:8]) are not used. An 8-bit Dual Scan STN display uses two sets of 4 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[3:0] is connected to the upper panel data lines and the bus LCDD[7:4] is connected to the lower panel data lines. The rest of the LCD Data Bus lines (LCDD[23:8]) are not used. A 16-bit Dual Scan STN display uses two sets of 8 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[7:0] is connected to the upper panel data lines and the bus LCDD[15:8] is connected to the lower panel data lines. The rest of the LCD Data Bus lines (LCDD[23:16]) are not used. STN Mono displays require one bit of image data per pixel. STN Color displays require three bits (Red, Green and Blue) of image data per pixel, resulting in a horizontal shift register of length three times the number of pixels per horizontal line. This RGB or Monochrome data is shifted to the LCD driver as consecutive bits via the parallel data lines. A TFT single scan display uses up to 24 parallel data lines to shift data to successive horizontal lines one at a time until the entire frame has been shifted and transferred. The 24 data lines are divided in three bytes that define the color shade of each color component of each pixel. The LCDD bus is split as LCDD[23:16] for the blue component, LCDD[15:8] for the green component and LCDD[7:0] for the red component. If the LCD Module has lower color resolution (fewer bits per color component), only the most significant bits of each component are used. All these interfaces are shown in Figure 43-6 to Figure 43-10. Figure 43-6 on page 858 shows the 24-bit single scan TFT display timing; Figure 43-7 on page 859 shows the 4-bit single scan STN display timing for monochrome and color modes; Figure 43-8 on page 860 shows the 8-bit single scan STN display timing for monochrome and color modes; Figure 43-9 on page 861 shows the 8-bit Dual Scan STN display timing for monochrome and color modes; Figure 43-10 on page 862 shows the 16-bit Dual Scan STN display timing for monochrome and color modes. Figure 43-6. TFT Timing (First Line Expanded View)
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [24:16] LCDD [15:8] LCDD [7:0]
B0 G0 R0
B1 G1 R1
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Figure 43-7. Single Scan Monochrome and Color 4-bit Panel Timing (First Line Expanded View)
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] LCDD [2] LCDD [1] LCDD [0] P0 P1 P2 P3 P4 P5 P6 P7
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] LCDD [2] LCDD [1] LCDD [0] R0 G0 B0 R1 G1 B1 R2 G2
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Figure 43-8. Single Scan Monochrome and Color 8-bit Panel Timing (First Line Expanded View)
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5
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Figure 43-9. Dual Scan Monochrome and Color 8-bit Panel Timing (First Line Expanded View)
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK
Lower Pane
LCDD [7] LCDD [6] LCDD [5] LCDD [4]
Upper Pane
LP0 LP1 L2 L3
LP4 LP5 LP6 LP7
LCDD [3] LCDD [2] LCDD [1] LCDD [0]
UP0 UP4 UP1 UP5 UP2 UP6 UP3 UP7
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK
Lower Pane
LCDD [7] LCDD [6] LCDD [5] LCDD [4]
Upper Pane
LR0 LG0 LB0 LR1
LG1 LB1 LR2 LG2
LCDD [3] LCDD [2] LCDD [1] LCDD [0]
UR0 UG1 UG0 UB1 UB0 UR2 UR1 UG2
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Figure 43-10. Dual Scan Monochrome and Color 16-bit Panel Timing (First Line Expanded View)
LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK
Lower Panel
LCDD [15] LCDD [14] LCDD [13] LCDD [12] LCDD [11] LCDD [10] LCDD [9] LCDD [8]
Upper Panel
LP0 LP1
LP8 LP9
LP2 LP10 LP3 LP11 LP4 LP12 LP5 LP13 LP6 LP14 LP7 LP15 UP0 UP8 UP1 UP9 UP2 UP10 UP3 UP11 UP4 UP12 UP5 UP13 UP6 UP14 UP7 UP15
LC DD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0]
LCDVSYNC LCDDEN LC DHSYNC LCDDOTCK
Lower Panel
LCDD [15] LCDD [14] LCDD [13] LCDD [12] LCDD [11] LCDD [10] LCDD [9] LCDD [8]
Upper Panel
LR0
LB2
LG0 LR3 LB0 LR1 LG3 LB3
LG1 LR4 LB1 LR2 LG4 LB4
LG2 LR5 UR0 UB2 UG0 UR3 UB0 UG3 UR1 UB3 UG1 UR4 UB1 UG4 UR2 UB4 UG2 UR5
LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0]
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Table 43-12. LCD Signal Multiplexing
LCD Data Bus LCDD[23] LCDD[22] LCDD[21] LCDD[20] LCDD[19] LCDD[18] LCDD[17] LCDD[16] LCDD[15] LCDD[14] LCDD[13] LCDD[12] LCDD[11] LCDD[10] LCDD[9] LCDD[8] LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCD3 LCD2 LCD1 LCD0 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 LCDLP3 LCDLP2 LCDLP1 LCDLP0 LCDUP3 LCDUP2 LCDUP1 LCDUP0 LCDLP7 LCDLP6 LCDLP5 LCDLP4 LCDLP3 LCDLP2 LCDLP1 LCDLP0 LCDUP7 LCDUP6 LCDUP5 LCDUP4 LCDUP3 LCDUP2 LCDUP1 LCDUP0 4-bit STN Single Scan (mono, color) 8-bit STN Single Scan (mono, color) 8-bit STN Dual Scan (mono, color) 16-bit STN Dual Scan (mono, color)
24-bit TFT LCD_BLUE7 LCD_BLUE6 LCD_BLUE5 LCD_BLUE4 LCD_BLUE3 LCD_BLUE2 LCD_BLUE1 LCD_BLUE0 LCD_GREEN7 LCD_GREEN6 LCD_GREEN5 LCD_GREEN4 LCD_GREEN3 LCD_GREEN2 LCD_GREEN1 LCD_GREEN0 LCD_RED7 LCD_RED6 LCD_RED5 LCD_RED4 LCD_RED3 LCD_RED2 LCD_RED1 LCD_RED0
16-bit TFT LCD_BLUE4 LCD_BLUE3 LCD_BLUE2 LCD_BLUE1 LCD_BLUE0 Intensity Bit
LCD_GREEN4 LCD_GREEN3 LCD_GREEN2 LCD_GREEN1 LCD_GREEN0 Intensity Bit
LCD_RED4 LCD_RED3 LCD_RED2 LCD_RED1 LCD_RED0 Intensity Bit
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43.6
Interrupts
The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are: * DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer. * FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty. * FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is full. * DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base Address pointers. This IRQ can be used to implement a double-buffer technique. For more information, see "Double-buffer Technique" on page 865. * End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached and the DMA Controller is in inactive state. * End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of the current frame is reached and the DMA Controller is in inactive state. Each IRQ can be individually enabled, disabled or cleared, in the LCD_IER (Interrupt Enable Register), LCD_IDR (Interrupt Disable Register) and LCD_ICR (Interrupt Clear Register) registers. The LCD_IMR register contains the mask value for each IRQ source and the LDC_ISR contains the status of each IRQ source. A more detailed description of these registers can be found in "LCD Controller (LCDC) User Interface" on page 869.
43.7
Configuration Sequence
The DMA Controller starts to transfer image data when the LCDC Core is activated (Write to LCD_PWR field of PWRCON register). Thus, the user should configure the LCDC Core and configure and enable the DMA Controller prior to activation of the LCD Controller. In addition, the image data to be shows should be available when the LCDC Core is activated, regardless of the value programmed in the GUARD_TIME field of the PWRCON register. To disable the LCD Controller, the user should disable the LCDC Core and then disable the DMA Controller. The user should not enable LIP again until the LCDC Core is in IDLE state. This is checked by reading the LCD_BUSY bit in the PWRCON register. The initialization sequence that the user should follow to make the LCDC work is: * Create or copy the first image to show in the display buffer memory. * If a palletized mode is used, create and store a palette in the internal LCD Palette memory(See "Palette" on page 849. * Configure the LCD Controller Core without enabling it: - LCDCON1 register: Program the CLKVAL and BYPASS fields: these fields control the pixel clock divisor that is used to generate the pixel clock LCDDOTCK. The value to program depends on the LCD Core clock and on the type and size of the LCD Module used. There is a minimum value of the LCDDOTCK clock period that depends on the LCD Controller Configuration, this minimum value can be found in Table 43-11 on page 853. The equations that are used to calculate the value of the pixel clock divisor can be found at the end of the section "Timegen" on page 853
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- LCDCON2 register: Program its fields following their descriptions in the LCD Controller User Interface section below and considering the type of LCD module used and the desired working mode. Consider that not all combinations are possible. - LCDTIM1 and LCDTIM2 registers: Program their fields according to the datasheet of the LCD module used and with the help of the Timegen section in page 10. Note that some fields are not applicable to STN modules and must be programmed with 0 values. Note also that there is a limitation on the minimum value of VHDLY, HPW, HBP that depends on the configuration of the LCDC. - LCDFRMCFG register: program the dimensions of the LCD module used. - LCDFIFO register: To program it, use the formula in section "FIFO" on page 847 - DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules. They are loaded with recommended patterns at reset, so it is not necessary to write anything on them. They can be used to improve the image quality in the display by tuning the patterns in each application. - PWRCON Register: this register controls the power-up sequence of the LCD, so take care to use it properly. Do not enable the LCD (writing a 1 in LCD_PWR field) until the previous steps and the configuration of the DMA have been finished. - CONTRAST_CTR and CONTRAST_VAL: use this registers to adjust the contrast of the display, when the LCDCC line is used. * Configure the DMA Controller. The user should configure the base address of the display buffer memory, the size of the AHB transaction and the size of the display image in memory. When the DMA is configured the user should enable the DMA. To do so the user should configure the following registers: - DMABADDR1 and DMABADDR2 registers: In single scan mode only DMABADDR1 register must be configured with the base address of the display buffer in memory. In dual scan mode DMABADDR1 should be configured with the base address of the Upper Panel display buffer and DMABADDR2 should be configured with the base address of the Lower Panel display buffer. - DMAFRMCFG register: Program the FRMSIZE field. Note that in dual scan mode the vertical size to use in the calculation is that of each panel. Respect to the BRSTLN field, a recommended value is a 4-word burst. - DMACON register: Once both the LCD Controller Core and the DMA Controller have been configured, enable the DMA Controller by writing a "1" to the DMAEN field of this register. If using a dual scan module or the 2D addressing feature, do not forget to write the DMAUPDT bit after every change to the set of DMA configuration values. - DMA2DCFG register: Required only in 2D memory addressing mode (see "2D Memory Addressing" on page 866). * Finally, enable the LCD Controller Core by writing a "1" in the LCD_PWR field of the PWRCON register and do any other action that may be required to turn the LCD module on.
43.8
Double-buffer Technique
The double-buffer technique is used to avoid flickering while the frame being displayed is updated. Instead of using a single buffer, there are two different buffers, the backbuffer (background buffer) and the primary buffer (the buffer being displayed).
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The host updates the backbuffer while the LCD Controller is displaying the primary buffer. When the backbuffer has been updated the host updates the DMA Base Address registers. When using a Dual Panel LCD Module, both base address pointers should be updated in the same frame. There are two possibilities: * Check the DMAFRMPTx register to ensure that there is enough time to update the DMA Base Address registers before the end of frame. * Update the Frame Base Address Registers when the End Of Frame IRQ is generated. Once the host has updated the Frame Base Address Registers and the next DMA end of frame IRQ arrives, the backbuffer and the primary buffer are swapped and the host can work with the new backbuffer. When using a dual-panel LCD module, both base address pointers should be updated in the same frame. In order to achieve this, the DMAUPDT bit in DMACON register must be used to validate the new base address.
43.9
2D Memory Addressing
The LCDC can be configured to work on a frame buffer larger than the actual screen size. By changing the values in a few registers, it is easy to move the displayed area along the frame buffer width and height.
Figure 43-11. Frame Buffer Addressing
Frame Buffer Displayed Image Base word address & pixel offset
Line-to-line address increment
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In order to locate the displayed window within a larger frame buffer, the software must: * Program the DMABADDR1 (DMABADDR2) register(s) to make them point to the word containing the first pixel of the area of interest. * Program the PIXELOFF field of DMA2DCFG register to specify the offset of this first pixel within the 32-bit memory word that contains it. * Define the width of the complete frame buffer by programming in the field ADDRINC of DMA2DCFG register the address increment between the last word of a line and the first word of the next line (in number of 32-bit words). * Enable the 2D addressing mode by writing the DMA2DEN bit in DMACON register. If this bit is not activated, the values in the DMA2DCFG register are not considered and the controller assumes that the displayed area occupies a continuous portion of the memory. The above configuration can be changed frame to frame, so the displayed window can be moved rapidly. Note that the FRMSIZE field of DMAFRMCFG register must be updated with any movement of the displaying window. Note also that the software must write bit DMAUPDT in DMACON register after each configuration for it to be accepted by LCDC.
Note: In 24 bpp packed mode, the DMA base address must point to a word containing a complete pixel (possible values of PIXELOFF are 0 and 8). This means that the horizontal origin of the displaying window must be a multiple of 4 pixels or a multiple of 4 pixels minus 1 (x = 4n or x = 4n-1, valid origins are pixel 0,3,4,7,8,11,12, etc.).
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43.10 Register Configuration Guide
Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. 43.10.1 STN Mode Example STN color(R,G,B) 320*240, 8-bit single scan, 70 frames/sec, Master clock = 60 Mhz Data rate : 320*240*70*3/8 = 2.016 MHz HOZVAL= ((3*320)/8 ) - 1 LINEVAL= 240 -1 CLKVAL = (60 MHz/ (2*2.016 MHz)) - 1= 14 LCDCON1= CLKVAL << 12 LCDCON2 = LITTLEENDIAN | SINGLESCAN | STNCOLOR | DISP8BIT| PS8BPP; LCDTIM1 = 0; LCDTIM2 = 10 | (10 << 21); LCDFRMCFG = (HOZVAL << 21) | LINEVAL; DMAFRMCFG = (7 << 24) + (320 * 240 * 8) / 32; 43.10.2 TFT Mode Example This example is based on the NEC TFT color LCD module NL6448BC20-08. TFT 640*480, 16-bit single scan, 60 frames/sec, pixel clock frequency = [21MHz..29MHz] with a typical value = 25.175 MHz. The Master clock must be (2*(n + 1))*pixel clock frequency HOZVAL = 640 - 1 LINEVAL = 480 - 1 If Master clock is 50 MHz CLKVAL = (50 MHz/ (2*25.175 MHz)) - 1= 0 VFP = (12 -1), VBP = (31-1), VPW = (2-1), VHDLY= (2-1) HFP = (16-1), HBP = (48 -1), HPW= (96-1)
LCDCON1= CLKVAL << 12 LCDCON2 = LITTLEENDIAN | CLKMOD | INVERT_CLK | INVERT_LINE | INVERT_FRM | PS16BPP | SINGLESCAN | TFT LCDTIM1 = VFP | (VBP << 8) | (VPW << 16) | (VHDLY << 24) LCDTIM2 = HBP | (HPW << 8) | (HFP << 21) LCDFRMCFG = (HOZVAL << 21) | LINEVAL DMAFRMCFG = (7 << 24) + (640 * 480* 16) / 32;
868
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43.11 LCD Controller (LCDC) User Interface
Table 43-13. LCD Controller (LCDC) User Interface
Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 0x81C 0x820 0x824 0x828 0x82C 0x830 0x834 0x838 0x83C 0x840 0x844 0x848 0x84C 0x850 0x854 0x858 0x860 0x864 Register DMA Base Address Register 1 DMA Base Address Register 2 DMA Frame Pointer Register 1 DMA Frame Pointer Register 2 DMA Frame Address Register 1 DMA Frame Address Register 2 DMA Frame Configuration Register DMA Control Register DMA Control Register LCD Control Register 1 LCD Control Register 2 LCD Timing Register 1 LCD Timing Register 2 LCD Frame Configuration Register LCD FIFO Register Reserved Dithering Pattern DP1_2 Dithering Pattern DP4_7 Dithering Pattern DP3_5 Dithering Pattern DP2_3 Dithering Pattern DP5_7 Dithering Pattern DP3_4 Dithering Pattern DP4_5 Dithering Pattern DP6_7 Power Control Register Contrast Control Register Contrast Value Register LCD Interrupt Enable Register LCD Interrupt Disable Register LCD Interrupt Mask Register LCD Interrupt Status Register LCD Interrupt Clear Register LCD Interrupt Test Register LCD Interrupt Raw Status Register Register Name DMABADDR1 DMABADDR2 DMAFRMPT1 DMAFRMPT2 DMAFRMADD1 DMAFRMADD2 DMAFRMCFG DMACON DMA2DCFG LCDCON1 LCDCON2 LCDTIM1 LCDTIM2 LCDFRMCFG LCDFIFO - DP1_2 DP4_7 DP3_5 DP2_3 DP5_7 DP3_4 DP4_5 DP6_7 PWRCON CONTRAST_CTR CONTRAST_VAL LCD_IER LCD_IDR LCD_IMR LCD_ISR LCD_ICR LCD_ITR LCD_IRR Access R/W R/W Read-only Read-only Read-only Read-only R/W R/W R/W R/W R/W R/W R/W R/W R/W - R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Write-only Write-only Read-only Read-only Write-only Write-only Read-only Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00002000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - 0xA5 0x5AF0FA5 0xA5A5F 0xA5F 0xFAF5FA5 0xFAF5 0xFAF5F 0xF5FFAFF 0x0000000e 0x00000000 0x00000000 0x0 0x0 0x0 0x0 0x0 0 0
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Table 43-13. LCD Controller (LCDC) User Interface (Continued)
Offset 0xC00 0xC04 0xC08 0xC0C ... 0xFFC Palette entry 255 Register Palette entry 0 Palette entry 1 Palette entry 2 Palette entry 3 Register Name LUT ENTRY 0 LUT ENTRY 1 LUT ENTRY 2 LUT ENTRY 3 ... LUT ENTRY 255 R/W Access R/W R/W R/W R/W Reset Value
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43.11.1 DMA Base Address Register 1 Name: DMABADDR1 Access: Read/Write Reset value: 0x00000000
31 23 15 7 30 22 14 6 29 21 13 5 28 BADDR-U 20 BADDR-U 12 BADDR-U 4 BADDR-U 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* BADDR-U Base Address for the upper panel in dual scan mode. Base Address for the complete frame in single scan mode. If a dual scan configuration is selected in LCDCON2 register or bit DMA2DEN in register DMACON is set, the bit DMAUPDT in that same register must be written after writing any new value to this field in order to make the DMA controller use this new value. 43.11.2 DMA Base Address Register 2 Name: DMABADDR2 Access: Read/Write Reset value: 0x00000000
31 23 15 7 30 22 14 6 29 21 13 5 28 BADDR-L 20 BADDR-L 12 BADDR-L 4 BADDR-L 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* BADDR-L Base Address for the lower panel in dual scan mode only. If a dual scan configuration is selected in LCDCON2 register or bit DMA2DEN in register DMACON is set, the bit DMAUPDT in that same register must be written after writing any new value to this field in order to make the DMA controller use this new value.
871
6249B-ATARM-14-Dec-06
43.11.3 DMA Frame Pointer Register 1 Name: DMAFRMPT1 Access: Read-only Reset value: 0x00000000
31 - 23 - 15 7 30 - 22 14 6 29 - 21 13 5 28 - 20 12 4 27 - 19 FRMPT-U 11 FRMPT-U 3 FRMPT-U 26 - 18 10 2 25 - 17 9 1 24 - 16 8 0
* FRMPT-U Current value of frame pointer for the upper panel in dual scan mode. Current value of frame pointer for the complete frame in single scan mode. Down count from FRMSIZE to 0.
Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame). It can be used as an estimation of the number of words transferred from memory for the current frame.
43.11.4 DMA Frame Pointer Register 2 Name: DMAFRMPT2 Access: Read-only Reset value: 0x00000000
31 - 23 15 7 30 - 22 14 6 29 - 21 13 5 28 - 20 12 4 27 - 19 FRMPT-L 11 FRMPT-L 3 FRMPT-L 26 - 18 10 2 25 - 17 9 1 24 - 16 8 0
* FRMPT-L Current value of frame pointer for the Lower panel in dual scan mode only. Down count from FRMSIZE to 0.
Note: This register is read-only and contains the current value of the frame pointer (number of words to the end of the frame). It can be used as an estimation of the number of words transferred from memory for the current frame.
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43.11.5 DMA Frame Address Register 1 Name: DMAFRMADD1 Access: Read-only Reset value: 0x00000000
31 23 15 7 30 22 14 6 29 21 13 5 28 FRMADD-U 20 FRMADD-U 12 FRMADD-U 4 FRMADD-U 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* FRMADD-U Current value of frame address for the upper panel in dual scan mode. Current value of frame address for the complete frame in single scan.
Note: This register is read-only and contains the current value of the last DMA transaction in the bus for the panel/frame.
43.11.6 DMA Frame Address Register 2 Name: DMAFRMADD2 Access: Read-only Reset value: 0x00000000
31 23 15 7 30 22 14 6 29 21 13 5 28 FRMADD-L 20 FRMADD-L 12 FRMADD-L 4 FRMADD-L 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* FRMADD-L Current value of frame address for the lower panel in single scan mode only.
Note: This register is read-only and contains the current value of the last DMA transaction in the bus for the panel.
873
6249B-ATARM-14-Dec-06
43.11.7 DMA Frame Configuration Register Name: DMAFRMCFG Access: Read/Write Reset value: 0x00000000
31 - 23 - 15 7 30 22 14 6 29 21 13 5 28 27 BRSTLN 20 19 FRMSIZE 12 11 FRMSIZE 4 3 FRMSIZE 26 18 10 2 25 17 9 1 24 16 8 0
* FRMSIZE: Frame Size In single scan mode, this is the frame size in words. In dual scan mode, this is the size of each panel. If a dual scan configuration is selected in LCDCON2 register or bit DMA2DEN in register DMACON is set, the bit DMAUPDT in that same register must be written after writing any new value to this field in order to make the DMA controller use this new value. * BRSTLN: Burst Length Program with the desired burst length - 1
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43.11.8 DMA Control Register Name: DMACON Access: Read/Write Reset value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 DMA2DEN 27 - 19 - 11 - 3 DMAUPDT 26 - 18 - 10 - 2 DMABUSY 25 - 17 - 9 - 1 DMARST 24 - 16 - 8 - 0 DMAEN
* DMAEN: DMA Enable 0: DMA is disabled. 1: DMA is enabled. * DMARST: DMA Reset (Write-only) 0: No effect. 1: Reset DMA module. DMA Module should be reset only when disabled and in idle state. * DMABUSY: DMA Busy 0: DMA module is idle. 1: DMA module is busy (doing a transaction on the AHB bus). * DMAUPDT: DMA Configuration Update 0: No effect 1: Update DMA Configuration. Used for simultaneous updating of DMA parameters in dual scan mode or when using 2D addressing. The values written in the registers DMABADDR1, DMABADDR2 and DMA2DCFG, and in the field FRMSIZE of register DMAFRMCFG, are accepted by the DMA controller and are applied at the next frame. This bit is used only if a dual scan configuration is selected (bit SCANMOD of LCDCON2 register) or 2D addressing is enabled (bit DMA2DEN in this register). Otherwise, the LCD controller accepts immediately the values written in the registers referred to above. * DMA2DEN: DMA 2D Adressing Enable 0: 2D adressing is disabled (values in register DMA2DCFG are "don't care"). 1: 2D adressing is enabled.
875
6249B-ATARM-14-Dec-06
43.11.9 LCD DMA 2D Adressing Register Name: DMA2DCFG Access: Read/Write Reset value: 0x00000000
31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 - 13 5 28 20 - 12 ADDRINC 4 ADDRINC 3 2 1 0 27 19 - 11 26 PIXELOFF 18 - 10 25 17 - 9 24 16 - 8
* ADDRINC: DMA 2D Addressing Address increment When 2-D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the number of bytes that the DMA controller must jump between screen lines. Itb must be programmed as: [({address of first 32-bit word in a screen line} - {address of last 32-bit word in previous line})]. In other words, it is equal to 4*[number of 32-bit words occupied by each line in the complete frame buffer minus the number of 32-bit words occupied by each displayed line]. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA controller use this new value. * PIXELOFF: DAM2D Addressing Pixel offset When 2D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the offset of the first pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31, so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering configuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA controller use this new value.
876
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43.11.10 LCD Control Register 1 Name: LCDCON1 Access: Read/Write, except LINECNT: Read-only Reset value: 0x00002000
31 23 15 7 - 30 22 LINECNT 14 CLKVAL 6 - 29 21 13 5 - 28 LINECNT 20 12 4 - 19 11 - 3 - 18 CLKVAL 10 - 2 - 17 9 - 1 - 16 8 - 0 BYPASS 27 26 25 24
* BYPASS: Bypass LCDDOTCK divider 0: The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1: The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency. * CLKVAL: Clock divider 9-bit divider for pixel clock (LCDDOTCK) frequency. Pixel_clock = system_clock ( CLKVAL + 1 ) x 2 * LINECNT: Line Counter (Read-only) Current Value of 11-bit line counter. Down count from LINEVAL to 0.
877
6249B-ATARM-14-Dec-06
43.11.11 LCD Control Register 2 Name: LCDCON2 Access: Read/Write Reset value: 0x0000000
31 30 MEMOR 23 22 - - 15 14 CLKMOD - 7 6 PIXELSIZE 29 - 21 - 13 - 5 28 27 - - 20 19 - - 12 11 INVDVAL INVCLK 4 3 IFWIDTH 26 - 18 - 10 INVLINE 2 SCANMOD 25 24 - - 17 16 - - 9 8 INVFRAME INVVD 1 0 DISTYPE
* DISTYPE: Display Type
DISTYPE 0 0 1 1 0 1 0 1 STN Monochrome STN Color TFT Reserved
* SCANMOD: Scan Mode 0: Single Scan 1: Dual Scan * IFWIDTH: Interface width (STN)
IFWIDTH 0 0 1 1 0 1 0 1 4-bit (Only valid in single scan STN mono or color) 8-bit (Only valid in STN mono or Color) 16-bit (Only valid in dual scan STN mono or color) Reserved
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* PIXELSIZE: Bits per pixel
PIXELSIZE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 bit per pixel 2 bits per pixel 4 bits per pixel 8 bits per pixel 16 bits per pixel 24 bits per pixel (Only valid in TFT mode) Reserved Reserved
* INVVD: LCDD polarity 0: Normal 1: Inverted * INVFRAME: LCDVSYNC polarity 0: Normal (active high) 1: Inverted (active low) * INVLINE: LCDHSYNC polarity 0: Normal (active high) 1: Inverted (active low) * INVCLK: LCDDOTCK polarity 0: Normal (LCDD fetched at LCDDOTCK falling edge) 1: Inverted (LCDD fetched at LCDDOTCK rising edge) * INVDVAL: LCDDEN polarity 0: Normal (active high) 1: Inverted (active low) * CLKMOD: LCDDOTCK mode 0: LCDDOTCK only active during active display period 1: LCDDOTCK always active * MEMOR: Memory Ordering Format 00: Big Endian 10: Little Endian 11: Wince format
879
6249B-ATARM-14-Dec-06
43.11.12 LCD Timing Configuration Register 1 Name: LCDTIM1 Access: Read/Write Reset value: 0x0000000
31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 13 5 28 - 20 12 VBP 4 VFP 3 2 1 0 27 19 VPW 11 10 9 8 26 VHDLY 18 17 16 25 24
* VFP: Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0. * VBP: Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to 0. * VPW: Vertical Synchronization pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal to (VPW+1) lines. In STN mode, these bits should be set to 0. * VHDLY: Vertical to horizontal delay In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is (VHDLY+1) LCDDOTCK cycles. In STN mode, these bits should be set to 0.
880
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43.11.13 LCD Timing Configuration Register 2 Name: LCDTIM2 Access: Read/Write Reset value: 0x0000000
31 23 15 - 7 30 22 HFP 14 - 6 29 21 13 5 28 HFP 20 - 12 4 HBP 19 - 11 HPW 3 2 1 0 18 - 10 17 - 9 16 - 8 27 26 25 24
* HBP: Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is (HBP+1) LCDDOTCK cycles. * HPW: Horizontal synchronization pulse width Width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is (HPW+1) LCDDOTCK cycles. * HFP: Horizontal Front Porch Number of idle LCDDOTCK cycles at the end of the line. Idle period is (HFP+1) LCDDOTCK cycles.
881
6249B-ATARM-14-Dec-06
43.11.14 LCD Frame Configuration Register Name: LCDFRMCFG Access: Read/Write Reset value: 0x0000000
31 23 15 - 7 30 22 LINESIZE 14 - 6 29 21 13 - 5 28 LINESIZE 20 - 12 - 4 LINEVAL 19 - 11 - 3 18 - 10 2 17 - 9 LINEVAL 1 16 - 8 0 27 26 25 24
* LINEVAL: Vertical size of LCD module In single scan mode: vertical size of LCD Module, in pixels, minus 1 In dual scan mode: vertical display size of each LCD panel, in pixels, minus 1 * LINESIZE: Horizontal size of LCD module, in pixels, minus 1
882
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43.11.15 LCD FIFO Register Name: LCDFIFO Access: Read/Write Reset value: 0x0000000
31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 FIFOTH 4 FIFOTH 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* FIFOTH: FIFO Threshold Must be programmed with: FIFOTH = 2048 - (2 x DMA_BURST_LENGTH + 3) where: * 2048 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode. * DMA_burst_length is the burst length of the transfers made by the DMA. Refer to "BRSTLN: Burst Length" on page 874.
883
6249B-ATARM-14-Dec-06
43.11.16 Dithering Pattern DP1_2 Register Name: DP1_2 Access: Read/Write Reset value: 0xA5
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DP1_2 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* DP1_2: Pattern value for 1/2 duty cycle 43.11.17 Dithering Pattern DP4_7 Register Name: DP4_7 Access: Read/Write Reset value: 0x5AF0FA5
31 - 23 15 7 30 - 22 14 6 29 - 21 13 5 28 - 20 DP4_7 12 DP4_7 4 DP4_7 3 2 1 0 11 10 9 8 27 19 26 DP4_7 18 17 16 25 24
* DP4_7: Pattern value for 4/7 duty cycle 43.11.18 Dithering Pattern DP3_5 Register Name: DP3_5 Access: Read/Write Reset value: 0xA5A5F
31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 DP3_5 4 DP3_5 3 2 1 0 27 - 19 11 26 - 18 DP3_5 10 9 8 25 - 17 24 - 16
* DP3_5: Pattern value for 3/5 duty cycle
884
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43.11.19 Dithering Pattern DP2_3 Register Name: DP2_3: Dithering Pattern DP2_3 Register Access: Read/Write Reset value: 0xA5F
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DP2_3 27 - 19 - 11 3 26 - 18 - 10 DP2_3 2 1 0 25 - 17 - 9 24 - 16 - 8
* DP2_3: Pattern value for 2/3 duty cycle
43.11.20 Dithering Pattern DP5_7 Register Name: DP5_7: Access: Read/Write Reset value: 0xFAF5FA5
31 - 23 15 7 30 - 22 14 6 29 - 21 13 5 28 - 20 DP5_7 12 DP5_7 4 DP5_7 3 2 1 0 11 10 9 8 27 19 26 DP5_7 18 17 16 25 24
* DP5_7: Pattern value for 5/7 duty cycle 43.11.21 Dithering Pattern DP3_4 Register Name: DP3_4 Access: Read/Write Reset value: 0xFAF5
31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 DP3_4 4 DP3_4 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* DP3_4: Pattern value for 3/4 duty cycle
885
6249B-ATARM-14-Dec-06
43.11.22 Dithering Pattern DP4_5 Register Name: DP4_5 Access: Read/Write Reset value: 0xFAF5F
31 - 23 - 15 7 30 - 22 - 14 6 29 - 21 - 13 5 28 - 20 - 12 DP4_5 4 DP4_5 3 2 1 0 27 - 19 11 26 - 18 DP4_5 10 9 8 25 - 17 24 - 16
* DP4_5: Pattern value for 4/5 duty cycle 43.11.23 Dithering Pattern DP6_7 Register Name: DP6_7 Access: Read/Write Reset value: 0xF5FFAFF
31 - 23 15 7 30 - 22 14 6 29 - 21 13 5 28 - 20 DP6_7 12 DP6_7 4 DP6_7 3 2 1 0 11 10 9 8 27 19 26 DP6_7 18 17 16 25 24
* DP6_7: Pattern value for 6/7 duty cycle
886
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43.11.24 Power Control Register Name: PWRCON Access: Read/Write Reset value: 0x0000000e
31 LCD_BUSY 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 GUARD_TIME 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 LCD_PWR
* LCD_PWR: LCD module power control 0 = lcd_pwr pin is low, other LCD_* pins are low. 0->1 = lcd_* pins activated, lcd_pwr are set high with the delay of GUARD_TIME frame periods. 1 = lcd_pwr pin is high, other lcd_* pins are active 1->0 = lcd_pwr pin is low, other lcd_* pins are active, but are set low after GUARD_TIME frame periods. * GUARD_TIME Delay in frame periods between applying control signals to the LCD module and setting LCD_PWR high, and between setting LCD_PWR low and removing control signals from LCD module * LCD_BUSY Read-only field. If 1, it indicates that the LCD is busy (active and displaying data, in power on sequence or in power off sequence).
887
6249B-ATARM-14-Dec-06
43.11.25 Contrast Control Register Name: CONTRAST_CTR Access: Read/Write Reset value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 ENA 26 - 18 - 10 - 2 POL 25 - 17 - 9 - 1 PS 24 - 16 - 8 - 0
* PS This 2-bit value selects the configuration of a counter prescaler. The meaning of each combination is as follows:
PS 0 0 1 1 0 1 0 1 The counter advances at a rate of fCOUNTER = fLCDC_CLOCK. The counter advances at a rate of fCOUNTER = fLCDC_CLOC /2. The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/4. The counter advances at a rate of fCOUNTER = fLCDC_CLOCK/8.
* POL This bit defines the polarity of the output. If 1, the output pulses are high level (the output will be high whenever the value in the counter is less than the value in the compare register CONSTRAST_VAL). If 0, the output pulses are low level. * ENA When 1, this bit enables the operation of the PWM generator. When 0, the PWM counter is stopped.
888
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43.11.26 Contrast Value Register Name: CONSTRAST_VAL Access: Read/Write Reset value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CVAL 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* CVAL PWM compare value. Used to adjust the analog value obtained after an external filter to control the contrast of the display.
889
6249B-ATARM-14-Dec-06
43.11.27 LCD Interrupt Enable Register Name: LCD_IER Access: Write-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERIE 29 - 21 - 13 - 5 OWRIE 28 - 20 - 12 - 4 UFLWIE 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFIE 25 - 17 - 9 - 1 LSTLNIE 24 - 16 - 8 - 0 LNIE
* LNIE: Line interrupt enable 0: No effect 1: Enable each line interrupt * LSTLNIE: Last line interrupt enable 0: No effect 1: Enable last line interrupt * EOFIE: DMA End of frame interrupt enable 0: No effect 1: Enable End Of Frame interrupt * UFLWIE: FIFO underflow interrupt enable 0: No effect 1: Enable FIFO underflow interrupt * OWRIE: FIFO overwrite interrupt enable 0: No effect 1: Enable FIFO overwrite interrupt * MERIE: DMA memory error interrupt enable 0: No effect 1: Enable DMA memory error interrupt
890
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43.11.28 LCD Interrupt Disable Register Name: LCD_IDR Access: Write-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERID 29 - 21 - 13 - 5 OWRID 28 - 20 - 12 - 4 UFLWID 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFID 25 - 17 - 9 - 1 LSTLNID 24 - 16 - 8 - 0 LNID
* LNID: Line interrupt disable 0: No effect 1: Disable each line interrupt * LSTLNID: Last line interrupt disable 0: No effect 1: Disable last line interrupt * EOFID: DMA End of frame interrupt disable 0: No effect 1: Disable End Of Frame interrupt * UFLWID: FIFO underflow interrupt disable 0: No effect 1: Disable FIFO underflow interrupt * OWRID: FIFO overwrite interrupt disable 0: No effect 1: Disable FIFO overwrite interrupt * MERID: DMA Memory error interrupt disable 0: No effect 1: Disable DMA Memory error interrupt
891
6249B-ATARM-14-Dec-06
43.11.29 LCD Interrupt Mask Register Name: LCD_IMR Access: Read-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERIM 29 - 21 - 13 - 5 OWRIM 28 - 20 - 12 - 4 UFLWIM 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFIM 25 - 17 - 9 - 1 LSTLNIM 24 - 16 - 8 - 0 LNIM
* LNIM: Line interrupt mask 0: Line Interrupt disabled 1: Line interrupt enabled * LSTLNIM: Last line interrupt mask 0: Last Line Interrupt disabled 1: Last Line Interrupt enabled * EOFIM: DMA End of frame interrupt mask 0: End Of Frame interrupt disabled 1: End Of Frame interrupt enabled * UFLWIM: FIFO underflow interrupt mask 0: FIFO underflow interrupt disabled 1: FIFO underflow interrupt enabled * OWRIM: FIFO overwrite interrupt mask 0: FIFO overwrite interrupt disabled 1: FIFO overwrite interrupt enabled * MERIM: DMA Memory error interrupt mask 0: DMA Memory error interrupt disabled 1: DMA Memory error interrupt enabled
892
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43.11.30 LCD Interrupt Status Register Name: LCD_ISR Access: Read-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERIS 29 - 21 - 13 - 5 OWRIS 28 - 20 - 12 - 4 UFLWIS 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFIS 25 - 17 - 9 - 1 LSTLNIS 24 - 16 - 8 - 0 LNIS
* LNIS: Line interrupt status 0: Line Interrupt not active 1: Line Interrupt active * LSTLNIS: Last line interrupt status 0: Last Line Interrupt not active 1: Last Line Interrupt active * EOFIS: DMA End of frame interrupt status 0: End Of Frame interrupt not active 1: End Of Frame interrupt active * UFLWIS: FIFO underflow interrupt status 0: FIFO underflow interrupt not active 1: FIFO underflow interrupt active * OWRIS: FIFO overwrite interrupt status 0: FIFO overwrite interrupt not active 1: FIFO overwrite interrupt active * MERIS: DMA Memory error interrupt status 0: DMA Memory error interrupt not active 1: DMA Memory error interrupt active
893
6249B-ATARM-14-Dec-06
43.11.31 LCD Interrupt Clear Register Name: LCD_ICR Access: Write-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERIC 29 - 21 - 13 - 5 OWRIC 28 - 20 - 12 - 4 UFLWIC 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFIC 25 - 17 - 9 - 1 LSTLNIC 24 - 16 - 8 - 0 LNIC
* LNIC: Line interrupt clear 0: No effect 1: Clear each line interrupt * LSTLNIC: Last line interrupt clear 0: No effect 1: Clear Last line Interrupt * EOFIC: DMA End of frame interrupt clear 0: No effect 1: Clear End Of Frame interrupt * UFLWIC: FIFO underflow interrupt clear 0: No effect 1: Clear FIFO underflow interrupt * OWRIC: FIFO overwrite interrupt clear 0: No effect 1: Clear FIFO overwrite interrupt * MERIC: DMA Memory error interrupt clear 0: No effect 1: Clear DMA Memory error interrupt
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43.11.32 LCD Interrupt Test Register Name: LCD_ITR Access: Write-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERIT 29 - 21 - 13 - 5 OWRIT 28 - 20 - 12 - 4 UFLWIT 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFIT 25 - 17 - 9 - 1 LSTLNIT 24 - 16 - 8 - 0 LNIT
* LNIT: Line interrupt test 0: No effect 1: Set each line interrupt * LSTLNIT: Last line interrupt test 0: No effect 1: Set Last line interrupt * EOFIT: DMA End of frame interrupt test 0: No effect 1: Set End Of Frame interrupt * UFLWIT: FIFO underflow interrupt test 0: No effect 1: Set FIFO underflow interrupt * OWRIT: FIFO overwrite interrupt test 0: No effect 1: Set FIFO overwrite interrupt * MERIT: DMA Memory error interrupt test 0: No effect 1: Set DMA Memory error interrupt
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43.11.33 LCD Interrupt Raw Status Register Name: LCD_IRR Access: Write-only Reset value: 0x0
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 MERIR 29 - 21 - 13 - 5 OWRIR 28 - 20 - 12 - 4 UFLWIR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 EOFIR 25 - 17 - 9 - 1 LSTLNIR 24 - 16 - 8 - 0 LNIR
* LNIR: Line interrupt raw status 0: No effect 1: Line interrupt condition present * LSTLNIR: Last line interrupt raw status 0: No effect 1: Last line Interrupt condition present * EOFIR: DMA End of frame interrupt raw status 0: No effect 1: End Of Frame interrupt condition present * UFLWIR: FIFO underflow interrupt raw status 0: No effect 1: FIFO underflow interrupt condition present * OWRIR: FIFO overwrite interrupt raw status 0: No effect 1: FIFO overwrite interrupt condition present * MERIR: DMA Memory error interrupt raw status 0: No effect 1: DMA Memory error interrupt condition present
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44. 2D Graphics Controller (2DGC)
44.1 Description
The 2D Graphics Controller (2DGC) features a hardware accelerator which highly simplifies drawing tasks and graphic management operations. The hardware accelerator makes it easy to draw lines and complex polygons and to perform block transfers within the frame buffer. The 2DGC also features a draw command queue that automatically executes a more complex drawing function that is composed of several register accesses. The 2DGC supports access to both external video RAM mapped to any EBI chip selects and internal RAM (frame buffer). The external video RAM can have an 8-bit, 16-bit or 32-bit data bus. The 2DGC supports 1 bit, 2 bits, 4 bits, 8 bits, 16 bits and 24 bits per pixel. The maximum virtual memory page can be 2048 x 2048 pixels. The data written into the video RAM by draw functions can be in little endian, big endian and WinCE format. The 2DGC is connected to the AHB (Advanced High Performance Bus) in two ways: first, as a master for reading and writing pixel data, and second, as a slave for register configuration.
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44.2
Block Diagram
Figure 44-1. 2D Graphic Controller (2GDC) Block Diagram
LINE DRAW
AHB SLAVE
AHB SLAVE INTERFACE (2DGC REGISTERS)
CLIPPING
POLYGON FILL
COMMAND QUEUE CONTROL
BLOCK TRANSFER
FIFO 64 X 16 AHB MASTER INERFACE 2DGC INTERRUPT INTERRUPT GENERATOR
AHB MASTER
44.3
44.3.1
Functional Description
Hardware Acceleration The hardware acceleration performs multiple block transfers, line draw or fill commands by issuing draw commands to the controller. This technique makes it possible to get rid of complex software layers.
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44.3.1.1 Line Draw Lines can be drawn up to a specific width scalable from 1 to 16 pixels. They can also be drawn as a broken line with a pattern set by a 16-bit pattern register. The following registers need to be programmed by the software to start a line draw: * 2DGC_SBXR: Starting position in pixel units on X-axis. * 2DGC_TEXR: Ending position in pixel units on X-axis. * 2DGC_SBYR: Starting position in pixel units on Y-axis. * 2DGC_TEYR: Ending position in pixel units on Y-axis. * 2DGC_LOR: Set LOC bitfield to select logic operation MOV. * 2DGC_CSR: Set CLR[3:0] bitfield to select a color. * 2DGC_GOR: Set GOC bitfield and OP bitfields to the to select the following values. - Set GOC[7:4] to select line draw. - Set OP[0] to select a 1D or 2D line draw. - Set OP[1] to select update X & Y or no update X & Y. - Set OP[2] to select relative or absolute. - Set OP[3] to select no transformation. * 2DGC_LWR: Set LWD bitfield to select line width in pixels. * 2DGC_LPR: Set LPT bitfield to select a pattern for the line. 0xFFFF is for solid. LTB bit in 2DGC_GSR will signal the completion of the drawing operation. Line Draw Modes * Absolute Line Draw First pixel position on the line is the pixel position loaded into source/begin x and source/begin y registers. Last pixel position on the line is the pixel position loaded into target/end x and target/end y registers. Figure 44-2. Absolute Line Draw From (2,0) to (5,0)
(0,0) 2,0 3,0 X 4,0 5,0 (9,0)
Y
DISPLAY
(0,4)
(9,4)
* Relative Line Draw First pixel position on the line is the pixel position loaded into source/begin x and source/begin y registers. Last pixel position on the line is the pixel position loaded into target/end x and target/end y registers plus the start pixel position loaded into source/begin x and source/begin y
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registers. The target/end x and target/end y registers stand for the length of the line to be drawn. Figure 44-3. Relative Line Draw From (2,0) to (5,0)
(0,0) 2,0 3,0 X 4,0 5,0 6,0 7,0 (9,0)
Y
DISPLAY
(0,4)
(9,4)
Relative Line Draw with Update XY Option First pixel position is loaded into source/begin x and source/begin y registers and last pixel position is loaded into target/end x target/end y registers. After the necessary color and pattern are loaded into appropriate registers, respectively 2DGC_CSR and 2DGC_LPR, line draw is initiated with a write to 2DGC_LOR register. If the line needs to be extended, then a single write to the 2DGC_GOR register with update XY option set initiates line draw (extension). Figure 44-4. Line Draw From (0,0) to (1,0) and Update XY Four Times
(0,0) 0,0 1,0 2,0 3,0 X 4,0 5,0 (9,0)
Y
DISPLAY
(0,4)
(9,4)
1D Line Draw with Broken Pattern 0xAAAA The first pixel drawn is based on the least significant bit of the pattern register. In this example the first pixel is not drawn. After rendering each pixel, the pattern register is rotated to the right by one bit.
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Figure 44-5. 1D Line Draw From (0,0) to (5,0) with Broken Pattern 0xAAAA
(0,0) 0,0 1,0 2,0 3,0 X 4,0 5,0 (9,0)
Y
DISPLAY
(0,4) Pixel not drawn
(9,4)
2D Line Draw with Broken Pattern 0xEBBB In 2D line drawing, the bit pattern does not rotate. Each pixel rendered is based on the last two bits of its X and Y addresses as shown below. Table 44-1. 2D Line Draw Pattern
X[1:0] = 0 Y[1:0] = 0 Y[1:0] = 1 Y[1:0] = 2 Y[1:0] = 3 LPT[12] LPT[8] LPT[4] LPT[0] X[1:0] = 1 LPT[13] LPT[9] LPT[5] LPT[1] X[1:0] = 2 LPT[14] LPT[10] LPT[6] LPT[2] X[1:0] = 3 LPT[15] LPT[11] LPT[7] LPT[3]
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Figure 44-6. 2D Line Draw From (0,0) to (5,4) with Broken Pattern 0xEBBB
(0,0) 0,0 1,0 2,1 3,2 Y 4,3 5,4 X (9,0)
DISPLAY (0,7) (9,7)
Pixel not drawn
44.3.1.2
Block Transfer A rectangle (or square) shape in pixel units can be transferred between areas in the virtual memory area of the VRAM. Logical operations such as AND, OR, XOR, NOT, NOR, NAND and XNOR can be made between the pixels in the source area and the destination area and stored in the destination area. The following registers need to be programmed to perform a block transfer: * 2DGC_BTSXR: size in pixel units on X-axis. * 2DGC_BTSYR: size in pixel units on Y-axis. * 2DGC_SBXR: starting position in pixel units on X-axis. * 2DGC_TEXR: ending position in pixel units on X-axis. * 2DGC_SBYR: starting position in pixel units on Y-axis. * 2DGC_TEYR: ending position in pixel units on Y-axis. * 2DGC_LOR: set LOC bitfield to select a logic operation MOV/AND/OR/XOR/NOT/NOR/NAND/XNOR. * 2DGC_CSR: set CLR[3:0] bitfield to select a color. * 2DGC_GOR: set GOC bitfield and OP bitfields to select the following values. - Set GOC to select block transfer. - Set OP[1:0] to select no update X & Y. - Set OP[2] to select absolute. - Set OP[3] to select no transformation.
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BTB bit in 2DGC_GSR signals the completion of the block transfer operation. Absolute Block Transfer A block of data is copied (or xor/or/and/xnor/nand/not/nor/xnor) from the start position loaded into start x and start y registers to the target position loaded into target x and target y registers. The size of data is based on size x and size y registers. Figure 44-7. Absolute Block Transfer from (1,0) to (4,4) Size (4,2)
(0,0) 1,0 1,1 2,0 3,1 4,0 X (11,0)
Y 4,4 4,5 5,4 6,5 7,4
DISPLAY (0,8) (11,8)
Relative Block Transfer A block of data is copied (or xor/or/and/xnor/nand/not/nor/xnor) from the start position loaded into start x and start y registers to a position offset based on the target position loaded into target x and target y registers with respect to start position. The size of data is based on size x and size y registers.
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Figure 44-8. Relative Block Transfer From (1,0) to (4,4) Size (4,2)
(0,0) 1,0 1,1 2,0 3,1 4,0 X (11,0)
Y 5,4 5,5 6,4 7,5 8,4
DISPLAY (0,8) (11,8)
Block Transfer with Update X/Y If a drawing is rendered and needs to be duplicated along the X-axis or Y-axis, then a single write to the 2DGC_GOC will duplicate the drawing in the desired direction. This saves writing actions to startx, starty, endx, endy, color and logic operation registers and results in a faster rendering. Figure 44-9. Block Transfer with Update X Two Times
(0,0) 0,0 0,1 Y 1,0 4,0 4,1 X 5,0 8,0 8,1 9,0 (11,0)
DISPLAY (0,4) (11,4)
44.3.1.3
Polygon Fill Polygon fill supports filling of complex (convex and concave) polygons. The number of vertices in the polygon is limited to 16 and is programmed into 2DGC_VXRs and 2DGC_VYRs registers. In order to obtain a specific complex polygon, vertex registers (2DGC_VXRs and 2DGC_VYRs) must be written in a specific order: vertex registers following the first one define
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adjacent vertices. Color is selected by programming 2DGC_CSR and pattern is selected by programming 2DGC_LPR. The following registers need to be programmed to perform a polygon fill: * 2DGC_VXRs: Vertex x of all vertices, limited to 16. * 2DGC_VYRs: Vertex y of all vertices, limited to 16. * 2DGC_FCR: Set CNTL bitfield to define the number of vertices. * 2DGC_CSR: Set CLR[3:0] to select a color. * 2DGC_LOR: Set LOC bitfield to select logic operation MOV. * 2DGC_GOC: Set GOC and OP bitfields to appropriate values: - Set GOC to select polygon fill. - Set OP[0] to select 1D. - Set OP[1] to select no update X & Y. - Set OP[2] to select absolute. - Set OP[3] to select no transformation. * 2DGC_LPR: Set * LPT bitfield to select a pattern for the line. 0xFFFF is for solid. FD bitfield in 2DGC_FCR signals completion of the polygon fill operation. Convex Polygon Hardware polygon fill can render convex polygons. A convex polygon is rendered when a straight line connecting any two points inside the polygon does not intersect any polygon edge. Figure 44-10 shows a polygon of four vertices (4,2), (6,4), (4,6) and (2,4) to be loaded to vertex registers (2DGC_VXRs and 2DGC_VYRs registers) in this order.
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Figure 44-10. Convex Polygon Fill
(0,0) X (8,0)
(4,2)
Y
(2,4)
(6,4)
(4,6) DISPLAY (0,8) (8,8)
Concave Polygon Hardware polygon fill can render concave polygons. A concave polygon is rendered when there is at least a straight line connecting two points inside the polygon that intersects at least two polygon edges. Figure 44-11 shows a polygon of eight vertices (4,1), (5,3), (7,4), (5,5), (4,7), (3,5), (1,4) and (3,3) to be loaded to vertex registers (2DGC_VXRs and 2DGC_VYRs registers) in this order.
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Figure 44-11. Concave Polygon Fill
(0,0) X (8,0)
(4,1)
(3,3) (1,4)
(5,3) (7,4)
Y
(3,5)
(5,5)
(4,7) DISPLAY (0,9) (8,9)
Complex Polygon Hardware polygon fill can render complex polygons. Complex polygons are basically concave polygons with self intersecting edges. Figure 44-12 shows a complex polygon of five vertices (4,0), (6,2), (6,6), (2,6) and (2,2) to be loaded to vertex registers (2DGC_VXRs and 2DGC_VYRs registers) in this order.
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Figure 44-12. Complex Polygon Fill
(0,0) X (8,0)
(4,1)
(2,3)
(6,3)
Y
(2,7) DISPLAY (0,9)
(6,7)
(8,9)
44.3.1.4
Clipping This function disables drawing outside the selected rectangular field. The clipping x and y coordinates are defined by the values, in pixel units, programmed in four clipping vertex registers 2DGC_CXMINR, 2DGC_CXMAXR, 2DGC_CYMINR, 2DGC_CYMAXR. Clipping is enabled by setting CEN bitfield in 2DGC_CCR. Polygons filled using the hardware fill are also clipped to the selected rectangle if clipping is enabled.
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Figure 44-13. Line and Polygon Clipping
(0,0) X (17,0)
(2,1) C1(2,2)
(5,1)
(8,1) (11,2)
(12,1) (13,2)
C2(15,2) (16,3)
(12,3) (5,4) (4,5) (8,5)
Y
(1,8)
(16,8)
CLIP RECTANGLE C4(2,10) (8,11) C3(15,10)
DISPLAY (0,13) (17,13) PIXEL DRAWN PIXEL NOT DRAWN
44.3.1.5
Draw Command Queuing Multiple block transfer, line draw or fill commands can be issued to the 2DGC by writing the commands to a 64 x 16-bit wide FIFO. All drawing specific registers can be written via writes to the FIFO by writing the address, length and the register value to the command queue. Length is based on the number of consecutive register writes. All accesses to the command queue FIFO are by reading/writing to the 16-bit wide 2DGC_CQR. The pointer to the command queue is automatically incremented by the controller. FIFO command size is limited to 64 half words.
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In order to optimize the small command FIFO (64 half words) use, and due to the restriction of the APB access that has to be full word only, all 32-bit registers are split into two registers. This only affects the clipping command where the start and end coordinates of the line to be clipped could be outside the range of 2048 pixels and may need 32 bits to define line coordinates. Thus extra accesses to the FIFO must be made if the clip line coordinate has to be represented in 32 bits versus 16 bits. See the specific example of clipping command that shows the change in code as described above. Figure 44-14. Command Queuing
2DGC FIFO READ FIFO SBXR ADDRESS = 0x08 LENGTH = 9 DRAW QUEUE CONTROL WRITE TO REG SBXR 2DGC REGISTERS
SBYR
SBXR
TEXR
SBYR
TEYR
TEXR
LWR
TEYR
LPR
LWR
CSR
LPR
LOR RENDER LINE
CSR
GOR
LOR
GOR CPU WRITE
BUF END = 64
Recommended Procedure for Using the Command Queue * Load the entire queue (equal to 64) with commands. * Enable command queue buffer empty interrupt (BUFE) in 2DGC_GMR if using interrupts instead of polling.
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* Wait for Command queue buffer empty status (BUFE) in 2DGC_GIR with a five second timeout or wait for an interrupt event if interrupt is enabled (recommended). * Post an event to the graphics task when interrupt is triggered or exit the loop checking for the status when command queue buffer is empty (BUFE in 2DGC_GIR). Load the next set of commands (refer to code examples). Procedure to Switch from Command Queue Drawing to Direct Drawing * Wait for command queue buffer empty status in 2DGC_GIR. * Wait for line drawing engine bit (LTB bitfield in 2DGC_GSR) to clear if a line is being drawn. * Wait for block transfer engine bit (BTB bitfield in 2DGC_GSR) to clear if a block is being transferred. * Wait for polygon fill done bit (FD bitfield in 2DGC_FCR) to set if a polygon fill is being performed. 44.3.2 Video RAM The Video RAM type and the address generated to access it are mainly based on data bus type (8, 16 or 32 bits), on number of bits per pixel and the virtual memory size required by the system. The 2DGC supports SRAM, PSRAM and SDRAM memory chips of 8-bit, 16-bit or 32-bit data buses. Memory chips can either be external memory (connected to EBI) or internal memory. The most significant 12 bits of the 32-bit video memory address can be programmed with the required offset. The 2DGC sees the video memory as a maximum virtual page of 2048(column-x) x 2048(rows-y) pixels with a pixel resolution up to 24 bpp. Hence, the maximum video memory that 2DGC can see is 12MBytes = 2048 * 2048 * 24/8. The row size of the virtual memory can be programmed to be 256, 512, 1024 or 2048 pixels. Since the minimum row size selection is 256 pixels and the next size up is 512 pixels, some chips that are tailored for 240(column size) x 320(row size) at 8 bpp LCDs have only 80 Kbytes of internal RAM and thus do not fit in the resolution scheme defined above. In order to make the 2DGC compliant with this kind of use, a special option was added to make 320 pixel wide row at 8 bpp selection possible. However, this slows down the drawing process. For instance, when a line draw command is issued, the 2DGC calculates the row offset based on the start/end pixel coordinates of the line draw versus a predefined shift in bits for row size selections of 256, 512, 1024 and 2048 (they are all powers of 2 and hence the shift is predefined in logic). There are two suggestions to solve this problem: * If a significant amount of drawing using the 2DGC is required and 240 x 320 at 8 bpp is not mandatory, a bigger frame can be used thus taking advantage of the 2DGC drawing speed. * If there is a firm requirement for 240 x 320 at 8 bpp, then the special option can be enabled in the 2DGC that makes 240 x 340 at 8 bpp support possible but slow, or the 2DGC can be disabled and software that can be faster is used instead. However, a pixel resolution of 320(column) x 240(row) at 8 bpp can use the internal memory of 80 Kbytes if necessary, as a row size selection of 256 pixels can be used. There is however no problem with any 1/4 VGA at anything less than 8 bpp.
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44.4
44.4.1
Examples of Drawing Functions
Line Draw This function draws a thick (2 pixels wide) solid black line from start point (startx, starty) to end point (endx, endy). startx, starty, endx, endy should be in pixel units.
Void line_draw(unsigned short startx, unsigned short starty, unsigned short endx, unsigned short endy) { while(graphics_control.2DGC_GSR & 3); graphics_control.2DGC_SBXR = startx; graphics_control.2DGC_SBYR = starty; graphics_control.2DGC_TEXR = endx; graphics_control.2DGC_TEYR = endy; graphics_control.2DGC_LOR = 0x00; // Select logic operation MOV graphics_control.2DGC_CSR = 0x00; // Colour black graphics_control.2DGC_LWR = 0x02; // 2 pixels wide graphics_control.2DGC_LPR = 0xFFFF; // Solid line graphics_control.2DGC_GOR = 0xD5; // Line draw, absolute, no update, 1D pattern while(graphics_control.2DGC_GSR & 1); }
44.4.2
Block Transfer This function OR's source data (startx, starty) of size (sizex, sizey) with destination data (endx, endy) and writes it to the destination memory area. sizex, sizey, startx, starty, endx, endy should be in pixel units.
Void block_transfer(unsigned short startx, unsigned short starty, unsigned short endx, unsigned short endy, unsigned short sizex, unsigned short sizey) { while(graphics_control.2DGC_GSR & 3); graphics_control.2DGC_2DGC_BTSXR = sizex; graphics_control.2DGC_2DGC_BTSYR = sizey; graphics_control.2DGC_SBXR = startx; graphics_control.2DGC_SBYR = starty; graphics_control.2DGC_TEXR = endx; graphics_control.2DGC_TEYR = endy; graphics_control.2DGC_LOR = 0x01; // Select logic operation OR graphics_control.2DGC_GOR = 0xB4; // Selects block transfer, absolute, no update while(graphics_control.2DGC_GSR & 2); }
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44.4.3 Clipped Line Draw This function draws a thick (2 pixels wide) patterned (pixel ON,OFF, ON, OFF...) black line from start point (startx, starty) to end point (endx, endy). Only the pixels that fall on or within the clip rectangle boundary are drawn. startx, starty, endx, endy should be in pixel units.
Void clipped_line_draw(signed long int startx, signed long int starty, signed long int endx, signed long int endy) { while(graphics_control.2DGC_GSR & 3); graphics_control.2DGC_SBXR = startx; graphics_control.2DGC_SBYR = starty; graphics_control.2DGC_TEXR = endx; graphics_control.2DGC_TEYR = endy; graphics_control.2DGC_LOR = 0x00; // Select logic operation MOV graphics_control.2DGC_CSR = 0x00; // Colour black graphics_control.2DGC_LWR = 0x02; // 2 pixels wide graphics_control.2DGC_LPR = 0x5555; // Patterned line ON, OFF, ON, OFF ... // set clip rectangle boundary (4,2), (8,2), (4,4), (8,4) graphics_control.2DGC_CXMINR = 4; graphics_control.2DGC_CXMAXR = 8; graphics_control.2DGC_CYMINR = 2; graphics_control.2DGC_CYMAXR = 4; graphics_control.2DGC_CCR = 1; // Enable clipping graphics_control.2DGC_GOR = 0xD5; // Line draw, absolute, no update, 1D pattern while(graphics_control.2DGC_GSR & 1); }
44.4.4
Polygon Fill This function fills a polygon with patterned black color. The number of vertices can be a maximum of 16. x_vertices and y_vertices should be in pixel units.
Void polygon_fill(unsigned short *x_vertices, unsigned short *y_vertices, unsigned short pattern, unsigned char vertex_count) { int i; while(graphics_control.2DGC_GSR & 3); for(i = 0; i < vertex_count; i++) { graphics_control.2DGC_VXR[i] = x_vertices; graphics_control.2DGC_VYR[i] = y_vertices; x_vertices++; y_vertices++; }
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graphics_control.2DGC_FCR = vertex_count << 1; graphics_control.2DGC_LOR = 0x00; // Select logic operation MOV graphics_control.2DGC_CSR = 0x00; // Colour black graphics_control.2DGC_LWR = 0x01; // 1 pixels wide line graphics_control.2DGC_LPR = 0xAAAA; // Patterned line OFF, ON, OFF, ON ... graphics_control.2DGC_GOR = 0xF5; // Polygon fill,absolute,no update,1D pattern while(!(graphics_control.2DGC_FCR & 1)); }
44.4.5
Drawing Using Command Queue This function draws a series of lines. All commands are written into the FIFO which is automatically converted to drawing commands. startx, starty, endx and endy should be in pixel units.
void command_queue_draw(unsigned short startx, unsigned short starty, unsigned short endx) { int add_count=6; int i; add_count = 6; // number of writes to 2DGC_CQR chk_for_buffer_empty(add_count); graphics_control.2DGC_CQR register address graphics_control.2DGC_CQR to update graphics_control.2DGC_CQR graphics_control.2DGC_CQR graphics_control.2DGC_CQR graphics_control.2DGC_CQR for(i = 0;i < 320; i ++) { add_count = 7; chk_for_buffer_empty(add_cnt); graphics_control.2DGC_CQR address graphics_control.2DGC_CQR update graphics_control.2DGC_CQR graphics_control.2DGC_CQR graphics_control.2DGC_CQR graphics_control.2DGC_CQR graphics_control.2DGC_CQR } } = = = = = = = 0x14; 0x05; i; 0xFFFF; 0x04; 0x00; 0xD4; // start address, end y register // length,# of registers to // end y // line pattern // colour select // logic operation, MOV // operation, line draw = = = = = = 0x08; 0x04; 120; 160; 0; 0; // start address, start x // length, number of registers // start x // start y // end x // end y
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void chk_for_buffer_empty(int add_cnt) { // Get BUFW_CNTR from 2DGC_CQCR and see if there is enough room in FIFO if((((graphics_control.2DGC_CQCR & 0xFC0) >> 6) + add_cnt) >= 64) { if(interrupt_enabled) // Wait for buffer empty interrupt to rise which should be enabled at first place in 2DGC_GIMR. sleep_until_event_from_isr; else while(!graphics_control.2DGC_GIR); }
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44.5
2D Graphic Controller (2DGC) User Interface
2DGC Register Mapping
Register Block Transfer Size X Register Block Transfer Size Y Register Source/Begin X Register Source/Begin Y Register Target/End X Register Target/End Y Register Line Width Register Line Pattern Register Color Select Register Logic Operation Register Graphics Operation Register Extended Begin X Register Extended Begin Y Register Extended End X Register Extended End Y Register Extended Color Select Register Clip Control Register Clip Rectangle X Minimum Register Clip Rectangle X Maximum Register Clip Rectangle Y Minimum Register Clip Rectangle Y Maximum Register Graphics Status Register VRAM Size Register Fill Control Register Graphics Interrupt Register Graphics Interrupt Mask Register Bits Per Pixel Register Command Queue Count Register Command Queue Status Register Command Queue Register Vertex X Registers Vertex Y Registers VRAM Offset Register Data Format Register Reserved Name 2DGC_BTSXR 2DGC_BTSYR 2DGC_SBXR 2DGC_SBYR 2DGC_TEXR 2DGC_TEYR 2DGC_LWR 2DGC_LPR 2DGC_CSR 2DGC_LOR 2DGC_GOR 2DGC_EBXR 2DGC_EBYR 2DGC_EEXR 2DGC_EEYR 2DGC_ECSR 2DGC_CCR 2DGC_CXMINR 2DGC_CXMAXR 2DGC_CYMINR 2DGC_CYMAXR 2DGC_GSR 2DGC_VSR 2DGC_FCR 2DGC_GIR 2DGC_GIMR 2DGC_BPPR 2DGC_CQCR 2DGC_CQSR 2DGC_CQR 2DGC_VXR 2DGC_VYR 2DGC_VOR 2DGC_DFR 2DGC_RES Access Read/Write Read-only Write-only Read/Write Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write - Reset State 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -
Table 44-2.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x60 0x64 0x68 0x70 0x78 0x7C 0x80 0x90 - 0xCC 0x120 - 0x15C 0x200 0x204 0xXX - 0xFC
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44.5.1 Block Transfer Size X Register Name: 2DGC_BTSXR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 XSIZE 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 XSIZE 1 24 - 16 - 8
2
0
* XSIZE Sets size X of a bit block transfer in pixel units. 44.5.2 Block Transfer Size Y Register
Name: 2DGC_BTSYR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 YSIZE 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 YSIZE 1 24 - 16 - 8
2
0
* YSIZE Sets size Y of a bit block transfer in pixel units.
917
6249B-ATARM-14-Dec-06
44.5.3
Source/Begin X Register
Name: 2DGC_SBXR Access: Read/Write Reset Value: 0x00000000
31 30 29 28 XSRC 23 22 21 20 XSRC 15 14 13 12 XSRC 7 6 5 4 XSRC 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* XSRC XSRC[10 - 0]: Sets source X of a bit block transfer/begin point X of line draw in pixel units. XSRC[31 - 0]: Sets begin point X of clipped line draw in pixel units. 44.5.4 Source/Begin Y Register
Name: 2DGC_SBYR Access: Read/Write Reset Value: 0x00000000
31 30 29 28 YSRC 23 22 21 20 YSRC 15 14 13 12 YSRC 7 6 5 4 YSRC 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* YCOR YSRC[10 - 0]: Sets source Y of a bit block transfer/begin point Y of line draw in pixel units. YSRC[31 - 0]: Sets begin point Y of clipped line draw in pixel units.
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44.5.5 Target/End X Register Name: 2DGC_TEXR Access: Read/Write Reset Value: 0x00000000
31 30 29 28 XEND 23 22 21 20 XEND 15 14 13 12 XEND 7 6 5 4 XEND 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* XEND XEND[10 - 0]: Sets source Y of a bit block transfer/begin point Y of line draw in pixel units. XEND[31 - 0]: Sets begin point Y of clipped line draw in pixel units. 44.5.6 Target/End Y Register
Name: 2DGC_TEYR Access: Read/Write Reset Value: 0x00000000
31 30 29 28 YEND 23 22 21 20 YEND 15 14 13 12 YEND 7 6 5 4 YEND 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* YEND YEND[10 - 0]: Sets source Y of a bit block transfer/begin point Y of line draw in pixel units. YEND[31 - 0]: Sets begin point Y of clipped line draw in pixel units.
919
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44.5.7
Line Width Register
Name: 2DGC_LWR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 26 - 18 - 10 - 2 LWD 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* LWD Line width in pixel units.
920
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44.5.8 Line Pattern Register Name: 2DGC_LPR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 LPT 7 6 5 4 LPT 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* LPT: Line Pattern Sets 16-bit 1D pattern or 4 x 4-bit 2D pattern for line drawing or polygon fill. In 1D pattern drawing, LPT[0] is the starting point of the pattern. After each operation, LPT will rotate one bit to the right. In 2D pattern drawing, the bit pattern does not rotate. The operation is determined on the last 2 bits of X and Y addresses as shown below.
X[1:0]=0 Y[1:0]=0 Y[1:0]=0 Y[1:0]=0 Y[1:0]=0 LPT[12] LPT[8] LPT[4] LPT[0] X[1:0]=1 LPT[13] LPT[9] LPT[5] LPT[1] X[1:0]=2 LPT[14] LPT[10] LPT[6] LPT[2] X[1:0]=3 LPT[15] LPT[11] LPT[7] LPT[3]
921
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44.5.9
Color Select Register
Name: 2DGC_CSR Access: Read/Write Reset Value: 0x00000000
31 - 23 30 - 22 29 - 21 28 - 20 CLR 15 14 13 12 CLR 7 6 5 4 CLR 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 - 16
* CLR: Color At 1 bpp only CLR[3] is active. 0: white is selected. 1: black is selected. At 2 bpp only CLR[3:2] is active.
Values 00 01 10 11 Color white light grey dark grey black
At 4 bpp, only CLR[3:0] is active. It selects one of the 16 grey shades for monochrome displays or one of the 16 simultaneous colors available. At 8 bpp, only CLR[7:0] is active. It selects one the 256 simultaneous colors available. At 16 bpp, only CLR[15:0] is active. It selects one of the 32768 colors available. At 24 bpp CLR[23:0] is active. It selects one of the 16M colors available.
922
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44.5.10 Logic Operation Register Name: 2DGC_LOR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 26 - 18 - 10 - 2 LOC 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* LOC: Logic Operation Code Valid logic function code
LOC 0000 0001 0010 0011 0100 0101 0110 0111 Function Write (MOV) OR AND XOR NOT NOR NAND XNOR
923
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44.5.11
Graphics Operation Register
Name: 2DGC_GOR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 GOC 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 - 3 OP3 26 - 18 - 10 - 2 OP2 25 - 17 - 9 - 1 OP1 24 - 16 - 8 - 0 OP0
* GOC: Graphic Operation Code
GOC 0000 1101 1011 1111 Function No Operation Line Drawing Block Transfer Polygon Fill
* OPx: Option There are four options, each one allows each operation code to behave as shown in the tables below.
0 OP3 OP2 OP1 OP0 No Transformation Relative No Update X,Y 2D Pattern 0 OP3 OP2 OP1 OP0 Note: No Transformation Relative No Update X No Update Y 1 Transformation Absolute Update X,Y 1D Pattern 1 Transformation Absolute Update X Update
Transformation bit is reserved for future use.
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The table below gives the possible operation depending on command code = (2DGC_LOR) | (2DGC_GOR << 8)
Command Code[15:0] 0x00 0xB00 0xB10 0xB20 0xB40 0xB50 0xB60 0xB01 0xB11 0xB21 0xB41 0xB51 0xB61 0xB02 0xB12 0xB22 0xB42 0xB52 0xB62 0xB03 0xB13 0xB23 0xB43 0xB53 0xB63 0xD00 0xD10 0xD20 0xD30 0xD40 0xD50 0xD60 0xD70 Function No Operation Block Transfer, Relative, No Update, MOV Block Transfer, Relative, Update Y, MOV Block Transfer, Relative, Update X, MOV Block Transfer, Absolute, No Update, MOV Block Transfer, Absolute, Update Y, MOV Block Transfer, Absolute, Update X, MOV Block Transfer, Relative, No Update, OR Block Transfer, Relative, Update Y, OR Block Transfer, Relative, Update X, OR Block Transfer, Absolute, No Update, OR Block Transfer, Absolute, Update Y, OR Block Transfer, Absolute, Update X, OR Block Transfer, Relative, No Update, AND Block Transfer, Relative, Update Y, AND Block Transfer, Relative, Update X, AND Block Transfer, Absolute, No Update, AND Block Transfer, Absolute, Update Y, AND Block Transfer, Absolute, Update X, AND Block Transfer, Relative, No Update, XOR Block Transfer, Relative, Update Y, XOR Block Transfer, Relative, Update X, XOR Block Transfer, Absolute, No Update, XOR Block Transfer, Absolute, Update Y, XOR Block Transfer, Absolute, Update X, XOR Line Drawing, Relative, No Update, 2D Pattern Line Drawing, Relative, No Update, 1D Pattern Line Drawing, Relative, Update X and Y, 2D Pattern Line Drawing, Relative, Update X and Y, 1D Pattern Line Drawing, Absolute, No Update, 2D Pattern Line Drawing, Absolute, No Update, 1D Pattern Line Drawing, Absolute, Update X and Y, 2D Pattern Line Drawing, Absolute, Update X and Y, 1D Pattern
925
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44.5.12
Extended Begin X Register
Name: 2DGC_EBXR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 EXT_BX 7 6 5 4 EXT_BX 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* EXT_BX Sets begin point x (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:16] is written to a separate register. 44.5.13 Extended Begin Y Register
Name: 2DGC_EBYR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 EXT_BY 7 6 5 4 EXT_BY 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* EXT_BY Sets begin point y (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:16] is written to a separate register.
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44.5.14 Extended End X Register Name: 2DGC_EEXR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 EXT_EX 7 6 5 4 EXT_EX 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* EXT_EX Sets end point x (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:16] is written to a separate register. 44.5.15 Extended End Y Register
Name: 2DGC_EEYR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 EXT_BY 7 6 5 4 EXT_BY 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* EXT_EY Sets end point y (MSB[31:16]) of line draw in pixel units. This register is only for clipped line draw when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:16] is written to a separate register.
927
6249B-ATARM-14-Dec-06
44.5.16
Extended Color Select Register
Name: 2DGC_ECSR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 EXT_CSR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* EXT_CSR Sets MSB[23:16] of color selection for 24 bpp. This register is only used when in 24 bpp mode and when command queue is used for drawing. Since the interface to the command queue is only 16, the MSB[31:24] is written to a separate register.
928
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44.5.17 Clip Control Register Name: 2DGC_CCR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 CEN
* CEN 1: Enable clipping. 0: Disable clipping.
929
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44.5.18
Clip Rectangle Minimum X Register
Name: 2DGC_CXMINR Access: Read/Write Reset Value: 0x000000F0
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CXMIN 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 CXMIN 1 24 - 16 - 8
2
0
* CXMIN Minimum x-coordinate boundary of the clip rectangle. 44.5.19 Clip Rectangle Maximum X Register
Name: 2DGC_CXMAXR Access: Read/Write Reset Value: 0x000000F0
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CXMAX 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 CXMAX 1 24 - 16 - 8
2
0
* CXMAX Maximum x-coordinate boundary of the clip rectangle.
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44.5.20 Clip Rectangle Minimum Y Register Name: 2DGC_CYMINR Access: Read/Write Reset Value: 0x000000F0
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CYMIN 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 CYMIN 1 24 - 16 - 8
2
0
* CYMIN Minimum y-coordinate boundary of the clip rectangle. 44.5.21 Clip Rectangle Maximum Y Register
Name: 2DGC_CYMAXR Access: Read/Write Reset Value: 0x000000F0
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 CYMAX 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 CYMAX 1 24 - 16 - 8
2
0
* CYMAX Maximum y-coordinate boundary of the clip rectangle.
931
6249B-ATARM-14-Dec-06
44.5.22
Graphics Status Register
Name: 2DGC_GSR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 BTB 24 - 16 - 8 - 0 LTB
* LTB 1: Line drawing engine is busy. 0: Line drawing engine is available. * BTB 1: Block transfer engine busy. 0: Block transfer engine available.
932
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44.5.23 VRAM Size Register Name: 2DGC_VSR Access: Read/Write Reset Value: 0x000000001VSIZE
31 - 23 - 15 - 7 - VSIZE 0 1 2 3 4 5 6 7 8 9 A B 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - VRAM TYPE 8-bit wide Data Bus 27 - 19 - 11 - 3 26 - 18 - 10 - 2 VSIZE 25 - 17 - 9 - 1 24 - 16 - 8 - 0
ROW OFFSET (Y) 512 1024 2048 256 512 1024 2048 256 512 1024 2048 256
16-bit wide Data Bus
32-bit wide Data Bus
933
6249B-ATARM-14-Dec-06
44.5.24
Fill Control Register
Name: 2DGC_FCR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 VCNT 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0 FD
* FD 1: Indicates polygon fill done. * VCNT A minimum value of 2 (for a triangle fill) to a maximum of 16 can be loaded into this bitfield.
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44.5.25 Graphics Interrupt Register Name: 2DGC_GIR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 BUFE
* BUFE: Command queue buffer empty interrupt 1: Signals buffer empty. Writing a 1 to this bit clears the interrupt. 44.5.26 Graphics Interrupt Mask Register
Name: 2DGC_GIMR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 BUFE
* BUFE: Command queue buffer empty interrupt enable 1: Enable command queue buffer empty interrupt. 0: Disable command queue buffer empty interrupt.
935
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44.5.27
Bits Per Pixel Register
Name: 2DGC_BPPR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 25 - 17 - 9 - 1 BPP 24 - 16 - 8 - 0
* BPP: Bits per pixel
BPP 0 1 2 3 4 5 Bits per pixel 1 BPP 2 BPP 4 BPP 8 BPP 16 BPP 24 BPP
936
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44.5.28 Command Queue Count Register Name: 2DGC_CQCR Access: Read-only Reset Value: 0x00000000
31 - 23 - 15 - 7 BUFW_CNTR 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 27 - 19 - 11 26 - 18 - 10 BUFW_CNTR 3 BUFR_CNTR 2 1 0 25 - 17 - 9 24 - 16 - 8
* BUFR_CNTR Number of half words read from the FIFO by internal logic. * BUFW_CNTR Number of half words written to the FIFO by CPU. 44.5.29 Command Queue Status Register
Name: 2DGC_CQSR Access: Read-only Reset Value: 0x00000000
31 - 23 - 15 - 7 - 30 - 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 BE
* BE: Buffer Empty 1: Buffer is empty. 0: Buffer is not empty.
937
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44.5.30
Command Queue Register
Name: 2DGC_CQR Access: Write-only Reset Value: 0x00000000
31 - 23 - 15 30 - 22 - 14 29 - 21 - 13 28 - 20 - 12 Q_DATA 7 6 5 4 Q_DATA 3 2 1 0 27 - 19 - 11 26 - 18 - 10 25 - 17 - 9 24 - 16 - 8
* Q_DATA All data to be stored in the queue is written to this register.
938
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44.5.31 Vertex X Registers Name: 2DGC_VXR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FVX 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FVX 1 24 - 16 - 8
2
0
* FVX Sets adjacent X vertices for polygon fill. 44.5.32 Vertex Y Registers
Name: 2DGC_VYR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 FVY 27 - 19 - 11 - 3 26 - 18 - 10 25 - 17 - 9 FVY 1 24 - 16 - 8
2
0
* FVY Sets adjacent Y vertices for polygon fill.
939
6249B-ATARM-14-Dec-06
44.5.33
VRAM OFFSET Register
Name: 2DGC_VOR Access: Read/Write Reset Value: 0x00000000
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 OFFSET 27 - 19 - 11 26 - 18 - 10 OFFSET 3 2 1 0 25 - 17 S8 9 24 - 16 PK 8
* OFFSET .Offset into the VRAM which gives the first pixel position in the memory. * PK: Packed Mode 1: Selects the packed 24 bpp mode. * S8 1: Allows the use of 320 pixel offset for rows (y). This special mode allows the use of 80K internal RAM for frame size of 240 x 320 at 8 bpp.
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44.5.34 DATA Format Register Name: 2DGC_DFR Access: Read/Write Reset Value: 0x00000000
31 ENDIAN 23 - 15 - 7 - 30 WINCE 22 - 14 - 6 - 29 - 21 - 13 - 5 - 28 - 20 - 12 - 4 - 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 - 25 - 17 - 9 - 1 - 24 - 16 - 8 - 0 -
* ENDIAN: ENDIANESS 1: DATA format is little endian. 0: DATA format is big endian. * WINCE 1: DATA format is WINCE compliant. 0: DATA format is not WINCE compliant.
941
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45. Image Sensor Interface (ISI)
45.1 Overview
The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (See Table 45-3 on page 946). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. It supports two modes of synchronization: 1. The hardware with ISI_VSYNC and ISI_HSYNC signals 2. The International Telecommunication Union Recommendation ITU-R BT.656-4 Startof-Active-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence. Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 45-1.
Signal ISI_VSYNC ISI_HSYNC ISI_DATA[11..0] ISI_MCK ISI_PCK
I/O Description
Dir IN IN IN OUT IN Description Vertical Synchronization Horizontal Synchronization Sensor Pixel Data Master Clock Provided to the Image Sensor Pixel Clock Provided by the Image Sensor
Figure 45-1. ISI Connection Example
Image Sensor Image Sensor Interface
data[11..0] CLK PCLK VSYNC HSYNC
ISI_DATA[11..0] ISI_MCK ISI_PCK ISI_VSYNC ISI_HSYNC
943
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45.2
Block Diagram
Figure 45-2. Image Sensor Interface Block Diagram
APB bus AHB bus
Hsync/Len Vsync/Fen
Timing Signals Interface
Camera Interrupt Controller From Rx buffers
Config Registers Camera Interrupt Request Line
APB Interface
CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5
APB Clock Domain AHB Clock Domain
Camera AHB Master Interface Scatter Mode Support
Pixel Clock Domain
Frame Rate
Clipping + Color Conversion YCC to RGB
2-D Image Scaler
Pixel Formatter
Pixel Sampling Module
Rx Direct Display FIFO
Core Video Arbiter
CMOS sensor pixel clock input
Clipping + Color Conversion RGB to YCC
Packed Formatter
Rx Direct Capture FIFO
codec_on
45.3
Functional Description
The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is generally connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. The data stream may be sent on both preview path and codec path if the bit CODEC_ON in the ISI_CR1 is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In grayscale mode, the input data stream is stored in memory without any processing. The 12bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CR2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.
944
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45.3.1 Data Timing The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are shown in Figure 45-3 and Figure 45-4. In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the control register. The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface. There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. Figure 45-3. HSYNC and VSYNC Synchronization
Frame
ISI_VSYNC
1 line
ISI_HSYNC
ISI_PCK DATA[7..0]
Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr
Figure 45-4. SAV and EAV Sequence Synchronization
ISII_PCK DATA[7..0]
FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D
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45.3.2
Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 45-2.
Mode Default Mode1 Mode2 Mode3
Data Ordering in YCbCr Mode
Byte 0 Cb(i) Cr(i) Y(i) Y(i) Byte 1 Y(i) Y(i) Cb(i) Cr(i) Byte 2 Cr(i) Cb(i) Y(i+1) Y(i+1) Byte 3 Y(i+1) Y(i+1) Cr(i) Cb(i)
Table 45-3.
Mode
RGB Format in Default Mode, RGB_CFG = 00, No Swap
Byte Byte 0 Byte 1 D7 R7(i) G7(i) B7(i) R7(i+1) R4(i) G2(i) R4(i+1) G2(i+1) D6 R6(i) G6(i) B6(i) R6(i+1) R3(i) G1(i) R3(i+1) G1(i+1) D5 R5(i) G5(i) B5(i) R5(i+1) R2(i) G0(i) R2(i+1) G0(i+1) D4 R4(i) G4(i) B4(i) R4(i+1) R1(i) B4(i) R1(i+1) B4(i+1) D3 R3(i) G3(i) B3(i) R3(i+1) R0(i) B3(i) R0(i+1) B3(i+1) D2 R2(i) G2(i) B2(i) R2(i+1) G5(i) B2(i) G5(i+1) B2(i+1) D1 R1(i) G1(i) B1(i) R1(i+1) G4(i) B1(i) G4(i+1) B1(i+1) D0 R0(i) G0(i) B0(i) R0(i+1) G3(i) B0(i) G3(i+1) B0(i+1)
RGB 8:8:8 Byte 2 Byte 3 Byte 0 Byte 1 RGB 5:6:5 Byte 2 Byte 3
Table 45-4.
Mode
RGB Format, RGB_CFG = 10 (Mode 2), No Swap
Byte Byte 0 Byte 1 D7 G2(i) B4(i) G2(i+1) B4(i+1) D6 G1(i) B3(i) G1(i+1) B3(i+1) D5 G0(i) B2(i) G0(i+1) B2(i+1) D4 R4(i) B1(i) R4(i+1) B1(i+1) D3 R3(i) B0(i) R3(i+1) B0(i+1) D2 R2(i) G5(i) R2(i+1) G5(i+1) D1 R1(i) G4(i) R1(i+1) G4(i+1) D0 R0(i) G3(i) R0(i+1) G3(i+1)
RGB 5:6:5 Byte 2 Byte 3
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Table 45-5.
Mode
RGB Format in Default Mode, RGB_CFG = 00, Swap Activated
Byte Byte 0 Byte 1 D7 R0(i) G0(i) B0(i) R0(i+1) G3(i) B0(i) G3(i+1) B0(i+1) D6 R1(i) G1(i) B1(i) R1(i+1) G4(i) B1(i) G4(i+1) B1(i+1) D5 R2(i) G2(i) B2(i) R2(i+1) G5(i) B2(i) G5(i+1) B2(i+1) D4 R3(i) G3(i) B3(i) R3(i+1) R0(i) B3(i) R0(i+1) B3(i+1) D3 R4(i) G4(i) B4(i) R4(i+1) R1(i) B4(i) R1(i+1) B4(i+1) D2 R5(i) G5(i) B5(i) R5(i+1) R2(i) G0(i) R2(i+1) G0(i+1) D1 R6(i) G6(i) B6(i) R6(i+1) R3(i) G1(i) R3(i+1) G1(i+1) D0 R7(i) G7(i) B7(i) R7(i+1) R4(i) G2(i) R4(i+1) G2(i+1)
RGB 8:8:8 Byte 2 Byte 3 Byte 0 Byte 1 RGB 5:6:5 Byte 2 Byte 3
The RGB 5:6:5 input format is processed to be displayed as RGB 5:5:5 format, compliant with the 16-bit mode of the LCD controller. 45.3.3 Clocks The sensor master clock (ISI_MCK) can be generated either by the Power Management Controller (PMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embeds a power management controller, so providing the clock by the PMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the system bus clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the system clock must be faster than pixel clock.
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45.3.4 45.3.4.1
Preview Path Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden.
Table 45-6.
Dec value Dec Factor
Decimation Factor
0->15 X 16 1 17 1.063 18 1.125 19 1.188 ... ... 124 7.750 125 7.813 126 7.875 127 7.938
Table 45-7.
OUTPUT VGA 640*480 QVGA 320*240 CIF 352*288 QCIF 176*144
Decimation and Scaler Offset Values
INPUT 352*288 NA 16 16 16 640*480 16 32 26 53 800*600 20 40 33 66 1280*1024 32 64 56 113 1600*1200 40 80 66 133 2048*1536 51 102 85 170
F F F F
Example: Input 1280*1024 Output=640*480 Hratio = 1280/640 =2 Vratio = 1024/480 =2.1333 The decimation factor is 2 so 32/16.
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Figure 45-5. Resize Examples
1280 32/16 decimation 640
1024
480
1280
56/16 decimation 352
1024
288
45.3.4.2
Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable:
C0 0 C1 Y - Y off R = C 0 - C 2 - C 3 x C b - C boff G B C0 C4 0 C r - C roff
Example of programmable value to convert YCrCb to RGB:
R = 1.164 ( Y - 16 ) + 1.596 ( C r - 128 ) G = 1.164 ( Y - 16 ) - 0.813 ( C r - 128 ) - 0.392 ( C b - 128 ) B = 1.164 ( Y - 16 ) + 2.107 ( C b - 128 )
An example of programmable value to convert from YUV to RGB:
R = Y + 1.596 V G = Y - 0.394 U - 0.436 V B = Y + 2.032 U
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45.3.4.3
Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:5:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory format are supported. One mode supports 2 pixels per word, and the other mode supports 1 pixel per word. Table 45-8.
GS_MODE 0 1
Grayscale Memory Mapping Configuration for 12-bit Data
DATA[31:24] P_0[11:4] P_0[11:4] DATA[23:16] P_0[3:0], 0000 P_0[3:0], 0000 DATA[15:8] P_1[11:4] 0 DATA[7:0] P_1[3:0], 0000 0
45.3.4.4
FIFO and DMA Features Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of two words. The first one defines the current frame buffer address, and the second defines the next FBD memory location. This DMA transfer mode is only available for preview datapath and is configured in the ISI_PPFBD register that indicates the memory location of the first FBD. The primary FBD is programmed into the camera interface controller. The data to be transferred described by an FBD requires several burst access. In the example below, the use of 2 ping-pong frame buffers is described.
Example The first FBD, stored at address 0x30000, defines the location of the first frame buffer. Destination Address: frame buffer ID0 0x02A000 Next FBD address: 0x30010 Second FBD, stored at address 0x30010, defines the location of the second frame buffer. Destination Address: frame buffer ID1 0x3A000 Transfer width: 32 bit Next FBD address: 0x30000, wrapping to first FBD. Using this technique, several frame buffers can be configured through the linked list. Figure 45-6 illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space.
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Figure 45-6. Three Frame Buffers Application and Memory Mapping
Codec Request Codec Done
frame n-1
frame n
frame n+1
frame n+2
frame n+3
frame n+4
Memory Space
Frame Buffer 3
Frame Buffer 0
LCD
Frame Buffer 1
ISI config Space
4:2:2 Image Full ROI
45.3.5 45.3.5.1
Codec Path Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below:
Y Cr = Cb
Y off R C 3 - C 4 - C 5 x G + Cr off B -C6 -C7 C8 Cb off
C0 C1 C2
An example of coefficients are given below:
Y = 0.257 R + 0.504 G + 0.098 B + 16 C = 0.439 R - 0.368 G - 0.071 B + 128 r C = - 0.148 R - 0.291 G + 0.439 B + 128 b
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45.3.5.2
Memory Interface Dedicated FIFO are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported. DMA Features Unlike preview datapath, codec datapath DMA mode does not support linked list operation. Only the CODEC_DMA_ADDR register is used to configure the frame buffer base address.
45.3.5.3
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45.4 Image Sensor Interface (ISI) User Interface
ISI Registers
Register Name ISI Control 1 Register ISI Control 2 Register ISI Status Register ISI Interrupt Enable Register ISI Interrupt Disable Register ISI Interrupt Mask Register Reserved Reserved ISI Preview Size Register ISI Preview Decimation Factor Register ISI Preview Primary FBD Register ISI Codec DMA Base Address Register ISI CSC YCrCb To RGB Set 0 Register ISI CSC YCrCb To RGB Set 1 Register ISI CSC RGB To YCrCb Set 0 Register ISI CSC RGB To YCrCb Set 1 Register ISI CSC RGB To YCrCb Set 2 Register Reserved Reserved Register ISI_CR1 ISI_CR2 ISI_SR ISI_IER ISI_IDR ISI_IMR ISI_PSIZE ISI_PDECF ISI_PPFBD ISI_CDBA ISI_Y2R_SET0 ISI_Y2R_SET1 ISI_R2Y_SET0 ISI_R2Y_SET1 ISI_R2Y_SET2 - - Access Read/Write Read/Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write - - Reset Value 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000000 0x00000000 0x6832cc95 0x00007102 0x01324145 0x01245e38 0x01384a4b - -
Table 45-9.
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44-0xF8 0xFC
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45.4.1
ISI Control 1 Register
Register Name: ISI_CR1 Access Type: Read/Write Reset Value: 0x00000002
31 30 29 28 SFD 23 22 21 20 SLD 15 CODEC_ON 7 CRC_SYNC 14 THMASK 6 EMB_SYNC 5 13 12 FULL 4 PIXCLK_POL 11 3 VSYNC_POL 10 9 FRATE 1 ISI_DIS 8 19 18 17 16 27 26 25 24
2 HSYNC_POL
0 ISI_RST
* ISI_RST: Image sensor interface reset 0: No action 1: Resets the image sensor interface. * ISI_DIS: Image sensor disable: 0: Enable the image sensor interface. 1: Finish capturing the current frame and then shut down the module. * HSYNC_POL: Horizontal synchronization polarity 0: HSYNC active high 1: HSYNC active low * VSYNC_POL: Vertical synchronization polarity 0: VSYNC active high 1: VSYNC active low * PIXCLK_POL: Pixel clock polarity 0: Data is sampled on rising edge of pixel clock 1: Data is sampled on falling edge of pixel clock * EMB_SYNC: Embedded synchronization 0: Synchronization by HSYNC, VSYNC 1: Synchronization by embedded synchronization sequence SAV/EAV * CRC_SYNC: Embedded synchronization 0: No CRC correction is performed on embedded synchronization 1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in the status register. * FRATE: Frame rate [0..7] 0: All the frames are captured, else one frame every FRATE+1 is captured. * FULL: Full mode is allowed 1: Both codec and preview datapaths are working simultaneously * THMASK: Threshold mask 0: 4, 8 and 16 AHB bursts are allowed 1: 8 and 16 AHB bursts are allowed 954
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2: Only 16 AHB bursts are allowed * CODEC_ON: Enable the codec path enable bit 0: The codec path is disabled 1: The codec path is enabled and the next frame is captured * SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. * SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame.
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45.4.2
ISI Control 2 Register
Register Name: ISI_CR2 Access Type: Read/Write Reset Value: 0x0
31 RGB_CFG 23 22 21 30 29 YCC_SWAP 20 IM_HSIZE 15 COL_SPACE 7 14 RGB_SWAP 6 13 GRAYSCALE 5 12 RGB_MODE 4 IM_VSIZE 11 GS_MODE 3 10 9 IM_VSIZE 1 8 28 27 19 26 25 IM_HSIZE 17 24
18
16
2
0
* IM_VSIZE: Vertical size of the Image sensor [0..2047] Vertical size = IM_VSIZE + 1 * GS_MODE 0: 2 pixels per word 1: 1 pixel per word * RGB_MODE: RGB input mode 0: RGB 8:8:8 24 bits 1: RGB 5:6:5 16 bits * GRAYSCALE 0: Grayscale mode is disabled 1: Input image is assumed to be grayscale coded * RGB_SWAP 0: D7 -> R7 1: D0 -> R7 The RGB_SWAP has no effect when the grayscale mode is enabled. * COL_SPACE: Color space for the image data 0: YCbCr 1: RGB * IM_HSIZE: Horizontal size of the Image sensor [0..2047] Horizontal size = IM_HSIZE + 1 * YCC_SWAP: Defines the YCC image data
YCC_SWAP 00: Default 01: Mode1 10: Mode2 11: Mode3 Byte 0 Cb(i) Cr(i) Y(i) Y(i) Byte 1 Y(i) Y(i) Cb(i) Cr(i) Byte 2 Cr(i) Cb(i) Y(i+1) Y(i+1) Byte 3 Y(i+1) Y(i+1) Cr(i) Cb(i)
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* RGB_CFG: Defines RGB pattern when RGB_MODE is set to 1
RGB_CFG 00: Default 01: Mode1 10: Mode2 11: Mode3 Byte 0 R/G(MSB) B/G(MSB) G(LSB)/R G(LSB)/B Byte 1 G(LSB)/B G(LSB)/R B/G(MSB) R/G(MSB) Byte 2 R/G(MSB) B/G(MSB) G(LSB)/R G(LSB)/B Byte 3 G(LSB)/B G(LSB)/R B/G(MSB) R/G(MSB)
If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence.
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45.4.3
ISI Status Register
Register Name: ISI_SR Access Type: Read Reset Value: 0x0
31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF
* SOF: Start of frame 0: No start of frame has been detected. 1: A start of frame has been detected. * DIS: Image Sensor Interface disable 0: The image sensor interface is enabled. 1: The image sensor interface is disabled and stops capturing data. The DMA controller and the core can still read the FIFOs. * SOFTRST: Software reset 0: Software reset not asserted or not completed 1: Software reset has completed successfully * CRC_ERR: CRC synchronization error 0: No crc error in the embedded synchronization frame (SAV/EAV) 1: The CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one. * FO_C_OVF: FIFO codec overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. * FO_P_OVF: FIFO preview overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. * FO_P_EMP 0:The DMA has not finished transferring all the contents of the preview FIFO. 1:The DMA has finished transferring all the contents of the preview FIFO. * FO_C_EMP 0: The DMA has not finished transferring all the contents of the codec FIFO. 1: The DMA has finished transferring all the contents of the codec FIFO. * FR_OVR: Frame rate overrun
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0: No frame overrun. 1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs.
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45.4.4
Interrupt Enable Register
Register Name: ISI_IER Access Type: Read/Write Reset Value: 0x0
31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF
* SOF: Start of Frame 1: Enables the Start of Frame interrupt. * DIS: Image Sensor Interface disable 1: Enables the DIS interrupt. * SOFTRST: Soft Reset 1: Enables the Soft Reset Completion interrupt. * CRC_ERR: CRC synchronization error 1: Enables the CRC_SYNC interrupt. * FO_C_OVF: FIFO codec Overflow 1: Enables the codec FIFO overflow interrupt. * FO_P_OVF: FIFO preview Overflow 1: Enables the preview FIFO overflow interrupt. * FO_P_EMP 1: Enables the preview FIFO empty interrupt. * FO_C_EMP 1: Enables the codec FIFO empty interrupt. * FR_OVR: Frame overrun 1: Enables the Frame overrun interrupt.
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45.4.5 ISI Interrupt Disable Register Register Name: ISI_IDR Access Type: Read/Write Reset Value: 0x0
31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF
* SOF: Start of Frame 1: Disables the Start of Frame interrupt. * DIS: Image Sensor Interface disable 1: Disables the DIS interrupt. * SOFTRST 1: Disables the soft reset completion interrupt. * CRC_ERR: CRC synchronization error 1: Disables the CRC_SYNC interrupt. * FO_C_OVF: FIFO codec overflow 1: Disables the codec FIFO overflow interrupt. * FO_P_OVF: FIFO preview overflow 1: Disables the preview FIFO overflow interrupt. * FO_P_EMP 1: Disables the preview FIFO empty interrupt. * FO_C_EMP 1: Disables the codec FIFO empty interrupt. * FR_OVR 1: Disables frame overrun interrupt.
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45.4.6
ISI Interrupt Mask Register
Register Name: ISI_IMR Access Type: Read/Write Reset Value: 0x0
31 - 23 - 15 - 7 FO_P_EMP 30 - 22 - 14 - 6 FO_P_OVF 29 - 21 - 13 - 5 FO_C_OVF 28 - 20 - 12 - 4 CRC_ERR 27 - 19 - 11 - 3 - 26 - 18 - 10 - 2 SOFTRST 25 - 17 - 9 FR_OVR 1 DIS 24 - 16 - 8 FO_C_EMP 0 SOF
* SOF: Start of Frame 0: The Start of Frame interrupt is disabled. 1: The Start of Frame interrupt is enabled. * DIS: Image sensor interface disable 0: The DIS interrupt is disabled. 1: The DIS interrupt is enabled. * SOFTRST 0: The soft reset completion interrupt is enabled. 1: The soft reset completion interrupt is disabled. * CRC_ERR: CRC synchronization error 0: The CRC_SYNC interrupt is disabled. 1: The CRC_SYNC interrupt is enabled. * FO_C_OVF: FIFO codec overflow 0: The codec FIFO overflow interrupt is disabled. 1: The codec FIFO overflow interrupt is enabled. * FO_P_OVF: FIFO preview overflow 0: The preview FIFO overflow interrupt is disabled. 1: The preview FIFO overflow interrupt is enabled. * FO_P_EMP 0: The preview FIFO empty interrupt is disabled. 1: The preview FIFO empty interrupt is enabled. * FO_C_EMP 0: The codec FIFO empty interrupt is disabled. 1: The codec FIFO empty interrupt is enabled. * FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled.
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45.4.7 ISI Preview Register Register Name: ISI_PSIZE Access Type: Read/Write Reset Value: 0x0
31 - 23 30 - 22 29 - 21 28 - 20 PREV_HSIZE 15 - 7 14 - 6 13 - 5 12 - 4 PREV_VSIZE 11 - 3 10 - 2 9 PREV_VSIZE 1 0 8 27 - 19 26 - 18 25 PREV_HSIZE 17 16 24
* PREV_VSIZE: Vertical size for the preview path Vertical Preview size = PREV_VSIZE + 1 (480 max) * PREV_HSIZE: Horizontal size for the preview path Horizontal Preview size = PREV_HSIZE + 1 (640 max)
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45.4.8
ISI Preview Register
Register Name: ISI_PDECF Access Type: Read/Write Reset Value: 0x00000010
31 - 23 - 15 - 7 30 - 22 - 14 - 6 29 - 21 - 13 - 5 28 - 20 - 12 - 4 DEC_FACTOR 27 - 19 - 11 - 3 26 - 18 - 10 - 2 25 - 17 - 9 - 1 24 - 16 - 8 - 0
* DEC_FACTOR: Decimation factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation.
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45.4.9 ISI Preview Primary FBD Register Register Name: ISI_PPFBD Access Type: Read/Write Reset Value: 0x0
31 30 29 28 27 PREV_FBD_ADDR 20 19 PREV_FBD_ADDR 12 11 PREV_FBD_ADDR 4 3 PREV_FBD_ADDR 26 25 24
23
22
21
18
17
16
15
14
13
10
9
8
7
6
5
2
1
0
* PREV_FBD_ADDR: Base address for preview frame buffer descriptor Written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. The frame buffer is forced to word alignment.
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45.4.10
ISI Codec DMA Base Address Register
Register Name: ISI_CDBA Access Type: Read/Write Reset Value: 0x0
31 30 29 28 27 CODEC_DMA_ADDR 20 19 CODEC_DMA_ADDR 12 11 CODEC_DMA_ADDR 4 3 CODEC_DMA_ADDR 26 25 24
23
22
21
18
17
16
15
14
13
10
9
8
7
6
5
2
1
0
* CODEC_DMA_ADDR: Base address for codec DMA This register contains codec datapath start address of buffer location.
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45.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register Register Name: ISI_Y2R_SET0 Access Type: Read/Write Reset Value: 0x6832cc95
31 30 29 28 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
* C0: Color Space Conversion Matrix Coefficient C0 C0 element, default step is 1/128, ranges from 0 to 1.9921875 * C1: Color Space Conversion Matrix Coefficient C1 C1 element, default step is 1/128, ranges from 0 to 1.9921875 * C2: Color Space Conversion Matrix Coefficient C2 C2 element, default step is 1/128, ranges from 0 to 1.9921875 * C3: Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875
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45.4.12
ISI Color Space Conversion YCrCb to RGB Set 1 Register
Register Name: ISI_Y2R_SET1 Access Type: Read/Write Reset Value: 0x00007102
31 - 23 - 15 - 30 - 22 - 14 Cboff 29 - 21 - 13 Croff 28 - 20 - 12 Yoff 27 - 19 - 11 - 26 - 18 - 10 - 25 - 17 - 9 - 24 - 16 - 8 C4
C4
* C4: Color Space Conversion Matrix coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875 * Yoff: Color Space Conversion Luminance default offset 0: No offset 1: Offset = 128 * Croff: Color Space Conversion Red Chrominance default offset 0: No offset 1: Offset = 16 * Cboff: Color Space Conversion Blue Chrominance default offset 0: No offset 1: Offset = 16
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45.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register Register Name: ISI_R2Y_SET0 Access Type: Read/Write Reset Value: 0x01324145
31 - 23 30 - 22 29 - 21 28 - 20 C2 15 14 13 12 C1 7 6 5 4 C0 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 Roff 16
* C0: Color Space Conversion Matrix coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375 * C1: Color Space Conversion Matrix coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875 * C2: Color Space Conversion Matrix coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875 * Roff: Color Space Conversion Red component offset 0: No offset 1: Offset = 16
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45.4.14
ISI Color Space Conversion RGB to YCrCb Set 1 Register
Register Name: ISI_R2Y_SET1 Access Type: Read/Write Reset Value: 0x01245e38
31 - 23 30 - 22 29 - 21 28 - 20 C5 15 14 13 12 C4 7 6 5 4 C3 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 Goff 16
* C3: Color Space Conversion Matrix coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875 * C4: Color Space Conversion Matrix coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375 * C5: Color Space Conversion Matrix coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875 * Goff: Color Space Conversion Green component offset 0: No offset 1: Offset = 128
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45.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register Register Name: ISI_R2Y_SET2 Access Type: Read/Write Reset Value: 0x01384a4b
31 - 23 30 - 22 29 - 21 28 - 20 C8 15 14 13 12 C7 7 6 5 4 C6 3 2 1 0 11 10 9 8 27 - 19 26 - 18 25 - 17 24 Boff 16
* C6: Color Space Conversion Matrix coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875 * C7: Color Space Conversion Matrix coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375 * C8: Color Space Conversion Matrix coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875 * Boff: Color Space Conversion Blue component offset 0: No offset 1: Offset = 128
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46. AT91SAM9263 Electrical Characteristics
46.1 Absolute Maximum Ratings
Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 46-1.
Operating Temperature (Industrial)............ -40 C to +125 C Storage Temperature .................................. -60C to +150C Voltage on Input Pins with Respect to Ground ................................. -0.3V to +4.0V Maximum Operating Voltage (VDDCORE and VDDBU).............................................. 1.5V Maximum Operating Voltage (VDDOSC, VDDPLL, VDDIOMx and VDDIOPx)............ 4.0V Total DC Output Current on all I/O lines ................... 500 mA
46.2
DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C. Table 46-2.
Symbol VVDDCORE VVDDBU VVDDOSC VVDDPLL VVDDIOM0
DC Characteristics
Parameter DC Supply Core DC Supply Backup DC Supply Oscillator DC Supply PLL DC Supply Memory 0 I/Os DC Supply Memory 1 I/Os DC Supply Peripheral 0 I/Os DC Supply Peripheral 1 I/Os Input Low-level Voltage Input High-level Voltage Output Low-level Voltage Output High-level Voltage VVDDIO= VVDDIOM or VVDDIOP VVDDIO0.4 VVDDIO= VVDDIOM or VVDDIOP Selectable by software in Bus Matrix 3.0 1.65 Selectable by software in Bus Matrix 3.0 2.7 1.65 -0.3 2 3.6 3.6 3.6 0.8 VVDDIO+ 0.3 0.4 V V V V V V V 3.6 1.95 V V Conditions Min 1.08 1.08 3.0 3.0 1.65 Typ Max 1.32 1.32 3.6 3.6 1.95 V V V Units V
VVDDIOM1 VVDDIOP0 VVDDIOP1 VIL VIH VOL VOH
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Table 46-2.
Symbol RPULLUP IO
DC Characteristics
Parameter Pull-up Resistance Output Current Conditions PA0-PA31, PB0-PB31, PC0-PC31, PD0-PD31, PE0PE31 PA0-PA31, PB0-PB31, PC0-PC31, PD0-PD31, PE0-PE31 On VVDDCORE = 1.2V, MCK = 0 Hz All inputs driven TMS, TDI, TCK, NRST = 1 TA =25C TA =85C TA =25C TA =85C 3 A 17 240 A 3500 Min 70 Typ 100 Max 175 8 Units kOhm mA
ISC
Static Current On VVDDBU = 1.2V, Logic cells consumption All inputs driven WKUP = 0
46.3
Power Consumption
* Power consumption of power supply in four different modes: Full Speed (PCK and MCK present), Idle (only MCK present), Quasi Static (the system is running at 500 Hz), Backup (in Shutdown Mode) * Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock.
46.3.1
Power Consumption versus Modes The values in Table 46-3 and Table 46-4 on page 977 are estimated values of the power consumption with operating conditions as follows: * VDDIOM0 = VDDIOM1 = VDDIOP0 = VDDIOP1 = 3.3 V * VDDPLL = VDDOSC = 3.3V * There is no consumption on the I/Os of the device
Figure 46-1. Measures Schematics
VDDBU AMP1 VDDCORE AMP2
These figures represent the power consumption measured on the power supplies.
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Table 46-3.
Mode
Power Consumption for Different Modes
Conditions ARM Core clock is 198 MHz. MCK is 96 MHz. Dhrystone running in Icache. Consumption Unit
VDDCORE = 1.08V TA = 85 C
onto AMP2 ARM Core clock is 240 MHz. MCK is 120 MHz. Dhrystone running in Icache.
55.9
Full speed (PCK and MCK present)
VDDCORE = 1.2V TA = 85 C
onto AMP2 ARM Core clock is 240 MHz. MCK is 120 MHz. Dhrystone running in Icache.
73.3
mA
VDDCORE = 1.2V TA = 25 C
onto AMP2 MCK is 96 MHz. ARM core in idle state, waiting an interrupt. Processor clock disabled
70.9
VDDCORE = 1.08V TA = 85 C
onto AMP2 MCK is 96 MHz. ARM core in idle state, waiting an interrupt. Processor clock disabled
20.2
Idle (only MCK present)
VDDCORE = 1.2V TA = 85 C
onto AMP2 MCK is 96 MHz. ARM core in idle state, waiting an interrupt. Processor clock disabled
22.7
mA
VDDCORE = 1.2V TA = 25 C
onto AMP2
19.5
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Table 46-3.
Mode
Power Consumption for Different Modes
Conditions ARM Core clock is 500 Hz. MCK is 500 Hz Consumption Unit
VDDCORE = 1.08V TA = 85 C
onto AMP2 Quasi Static (system running at 500 Hz) ARM Core clock is 500 Hz. MCK is 500 Hz
2720
VDDCORE = 1.2V TA = 85 C
onto AMP2 ARM Core clock is 500 Hz. MCK is 500 Hz
3080
A
VDDCORE = 1.2V TA = 25 C
onto AMP2 In Shutdown Mode
248
VDDBU = 1.08V TA = 85 C
onto AMP1 Backup (in Shutdown Mode) In Shutdown Mode
14.8
VDDBU = 1.2V TA = 85 C
onto AMP1 In Shutdown Mode
16.9
A
VDDBU = 1.2V TA = 25 C
onto AMP1
3.4
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Table 46-4.
Peripheral PIO Controller A or B PIO Controller C to E USART UHP UDP TWI SPI MCI SSC Timer Counter Channels CAN PWMC EMAC LCDC Image Sensor Interface AC97
Power Consumption by Peripheral onto AMP2 (TA = 25 C, VDDCORE = 1.2V)
Consumption 5 14 13 12 9 2 9 13 A/MHz 16 8 50 7 40 45 8 13 Unit
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46.4
Clock Characteristics
These parameters are given in the specified conditions. 46.4.1 Processor Clock Characteristics Processor Clock Waveform Parameters
Parameter Processor Clock Frequency Processor Clock Frequency Conditions VDDCORE = 1.1V T = 85C VDDCORE = 1.2V T = 85C Min Max 200 240 Units MHz MHz
Table 46-5.
Symbol 1/(tCPPCK) 1/(tCPPCK)
46.4.2
XIN Clock Characteristics XIN Clock Electrical Characteristics
Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pulldown Resistor
(1) (1)
Table 46-6.
Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Notes:
Conditions
Min
Max 50.0
Units MHz ns
20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 500
pF k
1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register).
46.4.3
I/Os Criteria used to define the maximum frequency of the I/Os: * output duty cycle (40%-60%) * minimum output swing: 100 mV to VDDIO - 100 mV * Addition of rising and falling time inferior to 75% of the period
Table 46-7.
Symbol FreqMax
I/O Characteristics
Parameter VDDIOP0 powered Pins frequency Conditions 3.3V domain 3.3V domain
(1) (1)
Min
Max 100 100 91 66
Units MHz MHz MHz MHz
FreqMax
VDDIOP1 powered Pins frequency
2.5V domain (2) 1.8V domain
(3)
Notes:
1. 3.3V domain: VVDDIOP from 3.0V to 3.6V, maximum external capacitor = 40 pF 2. 2.5V domain: VVDDIOP from 2.3V to 2.7V, maximum external capacitor = 30 pF 3. 1.8V domain: VVDDIOP from 1.65V to 1.95V, maximum external capacitor = 20 pF
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46.5 Crystal Oscillator Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C and worst case of power supply, unless otherwise specified. 46.5.1 32 kHz Oscillator Characteristics 32 kHz Oscillator Characteristics
Parameter Crystal Oscillator Frequency Load Capacitance Duty Cycle tST tST Note: Startup Time Startup Time VDDOSC = 3.3V RS = 50 k, CL = 12.5 pF(1) VDDOSC = 3.3V RS = 100 k, CL = 12.5 pF(1) Crystal @ 32.768 kHz, Max external capacitor = 25 pF 6 40 Conditions Min Typ 32 768 12.5 60 900 1200 Max Unit KHz pF % ms ms
Table 46-8.
Symbol 1/(tCP32KHz) CLOAD
1. RS is the equivalent series resistance, CL is the equivalent load capacitance.
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46.5.2
Main Oscillator Characteristics Main Oscillator Characteristics
Parameter Crystal Oscillator Frequency Crystal Load Capacitance COSC = 12.5 pF(7) Conditions Min 3 12.5 Typ 16 15 15 18 22 40 VDDPLL = 3 to 3.6V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 8MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Standby mode @ 3 MHz @ 8 MHz 50 60 14.5 4 1.4 1 1 15 30 W @ 16 MHz @ 20 MHz @ 3 MHz
(3)
Table 46-9.
Symbol 1/(tCPMAIN) COSC
Max 20 17.5
Unit MHz pF pF
CEXT
External Load Capacitance
COSC = 15 pF
(7) (7)
COSC = 17.5 pF Duty Cycle
%
tST
Startup Time
ms
IDDST
Standby Current Consumption
A
PON
Drive Level 50 50 150 300 300 450 3.5 4.5 250 530
@ 8 MHz(4) IDD ON Current Dissipation @ 16 MHz
(5)
A 530 650 7 7.5 W/MHz
@ 20 MHz(6) IBYPASS Notes: 1. 3. 4. 5. 6. 7. Bypass Current Dissipation on VDDOSC on VDDCORE
CS is the shunt capacitance. RS = 100 to 200 ; CS = 2.0 to 2.5 pF; CM = 2 to 1.5 fF (typ, worst case) using 1 k serial resistor on XOUT. RS = 50 to 100 ; CS = 2.0 to 2.5 pF; CM = 4 to 3 fF (typ, worst case). RS = 25 to 50 ; CS = 2.5 to 3.0 pF; CM = 7 to 5 fF (typ, worst case). RS = 20 to 50 ; CS = 3.2 to 4.0 pF; CM = 10 to 8 fF (typ, worst case). Additional user load capacitance should be subtracted from CEXT.
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46.5.3 Crystal Characteristics Table 46-10. Crystal Characteristics
Symbol Parameter Conditions Fundamental @ 3 MHz Fundamental @ 8 MHz ESR Equivalent Series Resistor Rs Fundamental @ 16 MHz Fundamental @ 20 MHz CM CS Motional Capacitance Shunt Capacitance 80 50 8 7 fF pF Min Typ Max 200 100 Unit
46.5.4
PLL Characteristics
Table 46-11. Phase Lock Loop Characteristics
Symbol FOUT FIN IPLL Parameter Output Frequency Field OUT of CKGR_PLL is 10 Input Frequency active mode Current Consumption standby mode Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. 1 A 190 1 240 32 3 MHz MHz mA Conditions Field OUT of CKGR_PLL is 00 Min 80 Typ Max 200 Unit MHz
Note:
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46.6
46.6.1
USB Transceiver Characteristics
Electrical Characteristics
Table 46-12. Electrical Parameters
Symbol Input Levels VIL VIH VDI VCM CIN I REXT Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 k tied to 3.6V Measured with RL of 14.25 k tied to GND Measure conditions described in Figure 46-13 0.0 2.8 1.3 0.3 3.6 2.0 V V V Low Level High Level Differential Input Sensivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with 5% - 10 27 |(D+) - (D-)| 2.0 0.2 0.8 2.5 9.18 + 10 0.8 V V V V pF A Parameter Conditions Min Typ Max Unit
Pull-up and Pull-down Resistor RPUI Bus Pull-up Resistor on Upstream Port (idle bus) Bus Pull-up Resistor on Upstream Port (upstream port receiving) 0.900 1.575 kOhm
RPUA
1.425
3.090
kOhm
46.7
46.7.1
EBI Timings
Conditions and Timings Computation These timings are given for worst case process, T = 85C and V=1.08V. First column for VDDIOM in 1.8V Supply range (1.65V-1.95V) and 30pF load capacitance. Second column for VDDIOM in 3.3V Supply range (3.0V-3.6V) and 50pF load capacitance.
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46.7.1.1 External Bus Interface 0 Timings
Table 46-13. SMC Read Signals with Hold Settings
Min Symbol Parameter 1.8V Supply NRD Controlled (READ_MODE = 1) SMC1 SMC2 SMC3 SMC4 SMC5 SMC6 SMC7 Data Setup before NRD High Data Hold after NRD High NRD High to NBS0/A0 Change (1) NRD High to NBS1 Change (1) NRD High to NBS2/A1 Change (1) NRD High to NBS3 Change (1) NRD High to A2 - A25 Change (1) -2.9 -2.8 nrd hold length * tCPMCK - 0.8 nrd hold length * tCPMCK - 0.8 nrd hold length * tCPMCK - 0.8 nrd hold length * tCPMCK - 0.8 nrd hold length * tCPMCK - 1.4 (nrd hold length - ncs rd hold length) * tCPMCK - 0.1 nrd pulse length * tCPMCK - 0.2 NCS Controlled (READ_MODE = 0) SMC10 SMC11 SMC12 Data Setup before NCS High Data Hold after NCS High NCS High to NBS0/A0 Change (1) -2.7 -2.8 ncs rd hold length * tCPMCK - 1.3 ncs rd hold length * tCPMCK - 1.3 ncs rd hold length * tCPMCK - 1.3 ncs rd hold length * tCPMCK - 1.3 -2.9 -2.6 ncs rd hold length * tCPMCK - 1.0 ncs rd hold length * tCPMCK - 1.0 ncs rd hold length * tCPMCK - 1.0 ncs rd hold length * tCPMCK - 1.0 ns ns ns -3 -2.6 nrd hold length * tCPMCK - 0.6 nrd hold length * tCPMCK - 0.6 nrd hold length * tCPMCK - 0.6 nrd hold length * tCPMCK - 0.6 nrd hold length * tCPMCK - 1.5 (nrd hold length - ncs rd hold length) * tCPMCK - 0.2 nrd pulse length * tCPMCK - 0.3 ns ns ns ns ns ns ns 3.3V Supply Units
SMC8
NRD High to NCS Inactive
(1)
ns
SMC9
NRD Pulse Width
ns
SMC13
NCS High to NBS1 Change (1)
ns
SMC14
NCS High to NBS2/A1 Change (1)
ns
SMC15
NCS High to NBS3 Change(1)
ns
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Table 46-13. SMC Read Signals with Hold Settings (Continued)
Min Symbol SMC16 Parameter NCS High to A2 - A25 Change (1) 1.8V Supply ncs rd hold length * tCPMCK + 0.5 (ncs rd hold length - nrd hold length)* tCPMCK 0.4 ncs rd pulse length * tCPMCK - 0.8 3.3V Supply ncs rd hold length * tCPMCK + 0.6 (ncs rd hold length - nrd hold length)* tCPMCK - 0.4 ncs rd pulse length * tCPMCK - 1.2 Units ns
SMC17
NCS High to NRD Inactive
(1)
ns
SMC18
NCS Pulse Width
ns
Note:
1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs rd hold length" or "nrd hold length".
Table 46-14. SMC Read Signals with No Hold Settings
Min Symbol Parameter 1.8V Supply NRD Controlled (READ_MODE = 1) SMC19 SMC20 Data Setup before NRD High Data Hold after NRD High 1.8 -2.5 1.8 -2.3 ns ns 3.3V Supply Units
NCS Controlled (READ_MODE = 0) SMC21 SMC22 Data Setup before NCS High Data Hold after NCS High 1.9 -2.5 1.9 -2.3 ns ns
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Table 46-15. SMC Write Signals with Hold Settings
Min Symbol Parameter 1.8V Supply NWR Controlled (WRITE_MODE = 1) SMC23 Data Out Valid before NWR High (nwr pulse length - 1) * tCPMCK - 1.0 nwr hold length * tCPMCK - 2.5 nwr hold length * tCPMCK - 0.8 nwr hold length * tCPMCK - 0.8 nwr hold length * tCPMCK - 0.8 nwr hold length * tCPMCK - 0.8 nwr hold length * tCPMCK - 1.3 (nwr hold length ncs wr hold length)* tCPMCK nwr pulse length * tCPMCK - 0.2 NCS Controlled (WRITE_MODE = 0) SMC34 Data Out Valid before NCS High (ncs wr pulse length - 1)* tCPMCK + 0.9 ncs wr hold length * tCPMCK - 2.4 (ncs wr hold length - nwr hold length)* tCPMCK - 0.3 (ncs wr pulse length - 1)* tCPMCK + 0.9 ncs wr hold length * tCPMCK - 2.6 (ncs wr hold length - nwr hold length)* tCPMCK + 0.1 ns (nwr pulse length - 1) * tCPMCK - 1.3 nwr hold length * tCPMCK - 2.7 nwr hold length * tCPMCK - 0.5 nwr hold length * tCPMCK - 0.5 nwr hold length * tCPMCK - 0.5 nwr hold length * tCPMCK - 0.5 nwr hold length * tCPMCK - 1.5 (nwr hold length - ncs wr hold length)* tCPMCK + 0.3 nwr pulse length * tCPMCK - 0.4 ns 3.3V Supply Units
SMC24 SMC25 SMC26 SMC29 SMC30 SMC31
Data Out Valid after NWR High (1) NWR High to NBS0/A0 Change (1) NWR High to NBS1 Change (1) NWR High to NBS2/A1 Change (1) NWR High to NBS3 Change (1) NWR High to A2 - A25 Change (1)
ns ns ns ns ns ns
SMC32
NWR High to NCS Inactive
(1)
ns
SMC33
NWR Pulse Width
ns
SMC35
Data Out Valid after NCS High (1)
ns
SMC36
NCS High to NWR Inactive
(1)
ns
Note:
1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs wr hold length" or "nwr hold length".
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Table 46-16. SMC Write Signals with no Hold Settings (NWR Controlled only)
Min Symbol SMC37 SMC38 SMC39 SMC40 SMC41 SMC42 SMC43 SMC44 SMC45 Parameter NWR Rising to A2-A25 Valid NWR Rising to NBS0/A0 Valid NWR Rising to NBS1 Change NWR Rising to A1/NBS2 Change NWR Rising to NBS3 Change NWR Rising to NCS Rising Data Out Valid before NWR Rising Data Out Valid after NWR Rising NWR Pulse Width 1.8V Supply 2.1 2.4 2.4 2.4 2.4 2.5 (nwr pulse length - 1) * tCPMCK - 1.0 1.9 nwr pulse length * tCPMCK - 0.2 3.3V Supply 1.9 2.1 2.1 2.1 2.1 2.3 (nwr pulse length - 1) * tCPMCK - 1.3 1.8 nwr pulse length * tCPMCK - 0.6 Units ns ns ns ns ns ns ns ns ns
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46.7.1.2 External Bus Interface 1 Timings
Table 46-17. SMC Read Signals with Hold Settings
Min Symbol Parameter 1.8V Supply NRD Controlled (READ_MODE = 1) SMC1 SMC2 SMC3 SMC4 SMC5 SMC6 SMC7 Data Setup before NRD High Data Hold after NRD High NRD High to NBS0/A0 Change (1) NRD High to NBS1 Change (1) NRD High to NBS2/A1 Change (1) NRD High to NBS3 Change (1) NRD High to A2 - A25 Change (1) -3.3 -2.3 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 1.0 (nrd hold length - ncs rd hold length) * tCPMCK - 0.6 nrd pulse length * tCPMCK + 0.1 NCS Controlled (READ_MODE = 0) SMC10 SMC11 SMC12 Data Setup before NCS High Data Hold after NCS High NCS High to NBS0/A0 Change (1) - 3.4 - 2.3 ncs rd hold length * tCPMCK - 0.2 ncs rd hold length * tCPMCK - 0.2 ncs rd hold length * tCPMCK - 0.2 ncs rd hold length * tCPMCK - 0.2 - 3.6 - 2.1 ncs rd hold length * tCPMCK - 0.1 ncs rd hold length * tCPMCK - 0.1 ncs rd hold length * tCPMCK - 0.1 ncs rd hold length * tCPMCK - 0.1 ns ns ns -3.5 -2.2 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.4 nrd hold length * tCPMCK - 0.7 (nrd hold length - ncs rd hold length) * tCPMCK - 0.2 nrd pulse length * tCPMCK - 0.1 ns ns ns ns ns ns ns 3.3V Supply Units
SMC8
NRD High to NCS Inactive
(1)
ns
SMC9
NRD Pulse Width
ns
SMC13
NCS High to NBS1 Change (1)
ns
SMC14
NCS High to NBS2/A1 Change (1)
ns
SMC15
NCS High to NBS3 Change(1)
ns
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Table 46-17. SMC Read Signals with Hold Settings (Continued)
Min Symbol SMC16 Parameter NCS High to A2 - A25 Change (1) 1.8V Supply ncs rd hold length * tCPMCK + 0.9 (ncs rd hold length - nrd hold length)* tCPMCK + 0.1 ncs rd pulse length * tCPMCK + 0.1 3.3V Supply ncs rd hold length * tCPMCK + 1.0 (ncs rd hold length - nrd hold length)* tCPMCK + 0.1 ncs rd pulse length * tCPMCK + 0.1 Units ns
SMC17
NCS High to NRD Inactive
(1)
ns
SMC18
NCS Pulse Width
ns
Note:
1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs rd hold length" or "nrd hold length".
Table 46-18. SMC Read Signals with no Hold Settings
Min Symbol Parameter 1.8V Supply NRD Controlled (READ_MODE = 1) SMC19 SMC20 Data Setup before NRD High Data Hold after NRD High 2.0 - 2.0 2.0 - 1.9 ns ns 3.3V Supply Units
NCS Controlled (READ_MODE = 0) SMC21 SMC22 Data Setup before NCS High Data Hold after NCS High 2.0 - 2.0 1.9 - 1.9 ns ns
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Table 46-19. SMC Write Signals with Hold Settings
Min Symbol Parameter 1.8V Supply NWR Controlled (WRITE_MODE = 1) SMC23 Data Out Valid before NWR High (nwr pulse length - 1) * tCPMCK - 2.4 nwr hold length * tCPMCK - 1.3 nwr hold length * tCPMCK - 0.7 nwr hold length * tCPMCK - 0.7 nwr hold length * tCPMCK - 0.7 nwr hold length * tCPMCK - 0.7 nwr hold length * tCPMCK - 0.7 (nwr hold length - ncs wr hold length)* tCPMCK - 0.3 nwr pulse length * tCPMCK (nwr pulse length - 1) * tCPMCK - 2.7 nwr hold length * tCPMCK - 1.5 nwr hold length * tCPMCK - 0.4 nwr hold length * tCPMCK - 0.4 nwr hold length * tCPMCK - 0.4 nwr hold length * tCPMCK - 0.4 nwr hold length * tCPMCK - 0.4 (nwr hold length - ncs wr hold length)* tCPMCK + 0.1 nwr pulse length * tCPMCK - 0.2 ns 3.3V Supply Units
SMC24 SMC25 SMC26 SMC29 SMC30 SMC31
Data Out Valid after NWR High (1) NWR High to NBS0/A0 Change (1) NWR High to NBS1 Change (1) NWR High to NBS2/A1 Change (1) NWR High to NBS3 Change (1) NWR High to A2 - A25 Change (1)
ns ns ns ns ns ns
SMC32
NWR High to NCS Inactive
(1)
ns
SMC33
NWR Pulse Width
ns
NCS Controlled (WRITE_MODE = 0) SMC34 Data Out Valid before NCS High (ncs wr pulse length - 1)* tCPMCK + 0.3 ncs wr hold length * tCPMCK - 1.4 (ncs wr hold length - nwr hold length)* tCPMCK - 0.3 (ncs wr pulse length - 1)* tCPMCK + 0.2 ncs wr hold length * tCPMCK - 1.5 (ncs wr hold length - nwr hold length)* tCPMCK + 0.1 ns
SMC35
Data Out Valid after NCS High(1)
ns
SMC36
NCS High to NWR Inactive
(1)
ns
Note:
1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs wr hold length" or "nwr hold length".
989
6249B-ATARM-14-Dec-06
Table 46-20. SMC Write Signals with no Hold Settings (NWR Controlled only)
Min Symbol SMC37 SMC38 SMC39 SMC40 SMC41 SMC42 SMC43 SMC44 SMC45 Parameter NWR Rising to A2-A25 Valid NWR Rising to NBS0/A0 Valid NWR Rising to NBS1 Change NWR Rising to A1/NBS2 Change NWR Rising to NBS3 Change NWR Rising to NCS Rising Data Out Valid before NWR Rising Data Out Valid after NWR Rising NWR Pulse Width 1.8V Supply 2.0 2.2 2.2 2.2 2.2 2.1 (nwr pulse length - 1) * tCPMCK - 2.4 2.0 nwr pulse length * tCPMCK 3.3V Supply 1.9 2.0 2.0 2.0 2.0 1.9 (nwr pulse length - 1) * tCPMCK - 2.7 1.8 nwr pulse length * tCPMCK - 0.2 Units ns ns ns ns ns ns ns ns ns
Figure 46-2. SMC Signals for NCS Controlled Accesses
SMC16 SMC16 SMC16
A2-A25
SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15
A0/A1/NBS[3:0]
NRD
SMC17 SMC17
NCS
SMC18 SMC22
SMC18
SMC18
SMC21
SMC10
SMC11
SMC34
SMC35
D0 - D15
SMC36
NWR
990
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6249B-ATARM-14-Dec-06
6249B-ATARM-14-Dec-06
SMC7 SMC7 SMC37 SMC31 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 SMC25 SMC26 SMC29 SMC30 SMC42 SMC8 SMC32 SMC8 SMC9 SMC9 SMC19 SMC43 SMC44 SMC20 SMC1 SMC2 SMC23 SMC24 SMC45 SMC33
A2-A25
A0/A1/NBS[3:0]
Figure 46-3. SMC Signals for NRD and NWR Controlled Accesses
NCS
NRD
D0 - D31
NWR
AT91SAM9263 Preliminary
991
46.7.2
SDRAMC Signals Relative to SDCK
These timings are given for a 10 pF load on SDCK and 50 pF on the data bus. 46.7.2.1 External Bus Interface 0 Timings
Table 46-21. SDRAMC Clock Signal
Max Symbol 1/(tCPSDCK) Parameter SDRAM Controller Clock Frequency 1.8V Supply 100 3.3V Supply 100 Units MHz
Table 46-22. SDRAMC Signals
Min Symbol SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 SDRAMC13 SDRAMC14 SDRAMC15 SDRAMC16 SDRAMC17 SDRAMC18 SDRAMC19 SDRAMC20 SDRAMC21 SDRAMC22 SDRAMC23 SDRAMC24 SDRAMC25 Parameter SDCKE High before SDCK Rising Edge (1) SDCKE Low after SDCK Rising Edge
(1) (1)
1.8V Supply 4.4 4.8 4.5 4.8 4.4 4.3 4.1 4.9 3.9 4.8
(1)
3.3V Supply 3.1 5.4 2.8 5.2 2.8 5.2 2.4 5.3 2.6 5.3 1.2 4.8 1.1 5.1 5.1 5.0 1.1 4.7 2.4 -0.2 3.3 0.1 2.5 5.4 1.4
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SDCKE Low before SDCK Rising Edge SDCKE High after SDCK Rising Edge
(1)
SDCS Low before SDCK Rising Edge (1) SDCS High after SDCK Rising Edge (1) RAS Low before SDCK Rising Edge RAS High after SDCK Rising Edge
(1)
(1)
SDA10 Change before SDCK Rising Edge (1) SDA10 Change after SDCK Rising Edge
(1)
Address Change before SDCK Rising Edge Address Change after SDCK Rising Edge
2.9 4.4 2.8 4.7 4.7 4.6 2.8 4.3 2.3 -0.3 3.2 0 4.1 5.0 3.0
(1)
Bank Change before SDCK Rising Edge (1) Bank Change after SDCK Rising Edge (1) CAS Low before SDCK Rising Edge CAS High after SDCK Rising Edge
(1)
(1)
DQM Change before SDCK Rising Edge (1) DQM Change after SDCK Rising Edge (1) D0-D15 in Setup before SDCK Rising Edge D0-D15 in Hold after SDCK Rising Edge D16-D31 in Setup before SDCK Rising Edge D16-D31 in Hold after SDCK Rising Edge SDWE Low before SDCK Rising Edge SDWE High after SDCK Rising Edge D0-D15 Out Valid before SDCK Rising Edge
992
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Table 46-22. SDRAMC Signals (Continued)
Min Symbol SDRAMC26 SDRAMC27 SDRAMC28 Note: Parameter D0-D15 Out Valid after SDCK Rising Edge D16-D31 Out Valid before SDCK Rising Edge D16-D31 Out Valid after SDCK Rising Edge 1.8V Supply 4.0 4.1 3.6 3.3V Supply 4.6 2.4 4.5 Units ns ns ns
1. The derating factor is not to be applied to tCLMCK or tCHMCK.
993
6249B-ATARM-14-Dec-06
46.7.2.2
External Bus Interface 1 Timings
Table 46-23. SDRAMC Clock Signal
Max Symbol 1/(tCPSDCK) Parameter SDRAM Controller Clock Frequency 1.8V Supply 100 3.3V Supply 100 Units MHz
Table 46-24. SDRAMC Signals
Min Symbol SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 SDRAMC13 SDRAMC14 SDRAMC15 SDRAMC16 SDRAMC17 SDRAMC18 SDRAMC19 SDRAMC20 SDRAMC21 SDRAMC22 SDRAMC23 SDRAMC24 SDRAMC25 SDRAMC26 SDRAMC27 SDRAMC28 Note: Parameter SDCKE High before SDCK Rising Edge SDCKE Low after SDCK Rising Edge (1) SDCKE Low before SDCK Rising Edge SDCKE High after SDCK Rising Edge SDCS Low before SDCK Rising Edge
(1) (1)
1.8V Supply 3.7 4.7 3.9 4.1 3.7 4.4 4.8 3.4
(1)
3.3V Supply 2.4 5.4 2.2 5.2 2.1 5.1 3.1 4.5 2.8 5.0 1.8 4.4 1.8 4.4 3.1 4.5 1.7 4.4 0.7 0.6 2.1 -0.2 2.6 4.9 1.7 4.3 2.5 4.6
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(1) (1)
SDCS High after SDCK Rising Edge (1) RAS Low before SDCK Rising Edge RAS High after SDCK Rising Edge
(1)
(1)
SDA10 Change before SDCK Rising Edge
4.1 3.9 3.3 3.9 3.4 3.9 4.8 3.4
SDA10 Change after SDCK Rising Edge (1) Address Change before SDCK Rising Edge (1) Address Change after SDCK Rising Edge Bank Change before SDCK Rising Edge
(1)
(1)
Bank Change after SDCK Rising Edge (1) CAS Low before SDCK Rising Edge CAS High after SDCK Rising Edge
(1)
(1) (1)
DQM Change before SDCK Rising Edge
3.3 3.9 0.6 0.5 1.9 -0.3 4.3 3.8 3.3 3.2 4.0 3.6
DQM Change after SDCK Rising Edge (1) D0-D15 in Setup before SDCK Rising Edge D0-D15 in Hold after SDCK Rising Edge D16-D31 in Setup before SDCK Rising Edge D16-D31 in Hold after SDCK Rising Edge SDWE Low before SDCK Rising Edge SDWE High after SDCK Rising Edge D0-D15 Out Valid before SDCK Rising Edge D0-D15 Out Valid after SDCK Rising Edge D16-D31 Out Valid before SDCK Rising Edge D16-D31 Out Valid after SDCK Rising Edge
1. The derating factor is not to be applied to tCLMCK or tCHMCK.
994
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
Figure 46-4. SDRAMC Signals Relative to SDCK
SDCK
SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4
SDCKE
SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6
SDCS
SDRAMC7 SDRAMC8
RAS
SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16
CAS
SDRAMC23 SDRAMC24
SDWE
SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10
SDA10
SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12
A0 - A9, A11 - A13
SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14
BA0/BA1
SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18
DQM0 DQM3
SDRAMC19 SDRAMC20
D0 - D15 Read
SDRAMC21 SDRAMC22
D16 - D31 Read
SDRAMC25 SDRAMC26
D0 - D15 to Write
SDRAMC27 SDRAMC28
D16 - D31 to Write
995
6249B-ATARM-14-Dec-06
46.8
EMAC Timings
Table 46-25. EMAC Signals Relative to EMDC
Symbol EMAC1 EMAC2 EMAC3 Parameter Setup for EMDIO from EMDC rising Hold for EMDIO from EMDC rising EMDIO toggling from EMDC rising Min (ns) 15.37 0 0 3.69 Max (ns)
46.8.1
MII Mode
Table 46-26. EMAC MII Specific Signals
Symbol EMAC4 EMAC5 EMAC6 EMAC7 EMAC8 EMAC9 EMAC10 EMAC11 EMAC12 EMAC13 EMAC14 EMAC15 EMAC16 Parameter Setup for ECOL from ETXCK rising Hold for ECOL from ETXCK rising Setup for ECRS from ETXCK rising Hold for ECRS from ETXCK rising ETXER toggling from ETXCK rising ETXEN toggling from ETXCK rising ETX toggling from ETXCK rising Setup for ERX from ERXCK Hold for ERX from ERXCK Setup for ERXER from ERXCK Hold for ERXER from ERXCK Setup for ERXDV from ERXCK Hold for ERXDV from ERXCK 13.71 0 6.2 0 9.38 0 Min (ns) 4 0 6.05 0 9.28 14.93 9.61 Max (ns)
996
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6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
Figure 46-5. EMAC MII Mode
EMDC EMAC1 EMDIO EMAC4 ECOL EMAC6 ECRS EMAC7 EMAC5 EMAC2 EMAC3
ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0]
ERXCK EMAC11 ERX[3:0] EMAC13 ERXER EMAC15 ERXDV EMAC16 EMAC14 EMAC12
997
6249B-ATARM-14-Dec-06
46.8.2
RMII Mode
Table 46-27. EMAC RMII Specific Signals
Symbol EMAC21 EMAC22 EMAC23 EMAC24 EMAC25 EMAC26 EMAC27 EMAC28 Parameter ETXEN toggling from EREFCK rising ETX toggling from EREFCK rising Setup for ERX from EREFCK Hold for ERX from EREFCK Setup for ERXER from EREFCK Hold for ERXER from EREFCK Setup for ECRSDV from EREFCK Hold for ECRSDV from EREFCK Min (ns) 5.81 5.27 8.35 0 5.79 0 6.05 0 Max (ns) 14.65 9.61
Figure 46-6. EMAC RMII Mode
EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 ERX[1:0] EMAC25 ERXER EMAC27 ECRSDV EMAC28 EMAC26 EMAC24
998
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
46.9
46.9.1
Peripheral Timings
SPI Figure 46-7. SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI0 MISO
SPI1
SPI2 MOSI
Figure 46-8. SPI Master Mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI3 MISO
SPI4
SPI5 MOSI
Figure 46-9. SPI Slave Mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI6 MISO
SPI7 MOSI
SPI8
999
6249B-ATARM-14-Dec-06
Figure 46-10. SPI Slave Mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI9 MISO
SPI10 MOSI
SPI11
Table 46-28. SPI Timings
Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 Note: Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) SPCK falling to MOSI Delay (master) SPCK falling to MISO Delay (slave) MOSI Setup time before SPCK rises (slave) MOSI Hold time after SPCK rises (slave) SPCK rising to MISO Delay (slave) MOSI Setup time before SPCK falls (slave) MOSI Hold time after SPCK falls (slave) 1. Cload is 8 pF for MISO and 6 pF for SPCK and MOSI. Conditions
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
Min 5.2 4.7
Max 0
Units ns ns
0.8 10.8 10.4 -4.8 -0.4 -0.7 -0.6 -0.5 -0.8 -0.6
ns ns ns ns ns ns ns ns ns ns
1000
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6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
46.9.2 ISI Figure 46-11. ISI Timing Diagram
1
VSYNC
7
HSYNC
2 5 6
PIXCLK
DATA[7:0]
Valid Data
Valid Data
Valid Data
3
4
Table 46-29. ISI Timings
Symbol 1 2 3 4 5 6 7 Parameter VSYNC to HSYNC HSYNC to PIXCLK DATA setup time DATA hold time PIXCLK high time PIXCLK low time PIXCLK frequency Min 2.75 -1.49 5.87 -1.28 0 0 I/O Max freq See Section 46.4.3 "I/Os" on page 978 Max Units ns ns ns ns ns ns MHz
1001
6249B-ATARM-14-Dec-06
46.9.3
MCI The PDC interface block controls all data routing between the external data bus, internal MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/SD module (inner system) and the application (user programming). These timings are given for a 25 pF load, corresponding to 1 MMC/SD Card. Figure 46-12. MCI Timing Diagram
1
Bus Clock 2 CMD_DAT Input
Valid Data
3
Valid Data
6 CMD_DAT Output 4
Valid Data Valid Data
5
Table 46-30. MCI Timings
Symbol 1 2 3 4 5 Parameter CLK frequency at Data transfer Mode (PP) Input hold time Input setup time Output hold time Output setup time Min 0 15.7 -2.8 5.4 14.4 Max 51 Units MHz ns ns ns ns
1002
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
46.9.4 UDP and UHP Switching Characteristics Figure 46-13. USB Data Signal Rise and Fall Times
Rise Time VCRS 10% Differential Data Lines tR (a) REXT=39 Ohms Fosc = 6MHz/750kHz Buffer (b) Cload tF 90% 10% Fall Time
Table 46-31. In Low Speed
Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 400 pF CLOAD = 400 pF CLOAD = 400 pF Min 75 75 80 Typ Max 300 300 125 Unit ns ns %
Table 46-32. In Full Speed
Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min 4 4 90 Typ Max 20 20 111.11 Unit ns ns %
1003
6249B-ATARM-14-Dec-06
47. AT91SAM9263 Mechanical Characteristics
47.1
47.1.1
Thermal Considerations
Thermal Data Table 47-1 summarizes the thermal resistance data depending on the package. Table 47-1.
Symbol JA JC
Thermal Resistance Data
Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Package TFBGA 324 TFBGA 324 Typ 23.7 C/W 5.1 Unit
47.1.2
Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 3. 4. T J = T A + ( P D x JA )
T J = T A + ( P D x ( HEATSINK + JC ) )
where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 47-1 on page 1004. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 47-1 on page 1004. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section Section 46.3 "Power Consumption" on page 974. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C.
1004
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AT91SAM9263 Preliminary
47.2 Package Drawing
Figure 47-1. 324-ball TFBGA Package Drawing
Table 47-2.
Ball Land
Soldering Information
0.4 mm +/- 0.05 0.275 mm +/- 0.03
Soldering Mask Opening
Table 47-3.
572
Device and 324-balls TFBGA Package Maximum Weight
mg
Table 47-4.
324-balls TFBGA Package Characteristics
3
Moisture Sensitivity Level
Table 47-5.
Package Reference
MO-210 e1
JEDEC Drawing Reference JESD97 Classification
1005
6249B-ATARM-14-Dec-06
This package respects the recommendations of the NEMI User Group.
47.3
Soldering Profile
Table 47-6 gives the recommended soldering profile from J-STD-020C. Table 47-6. Soldering Profile
Green Package 3 C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260 +0 C 6 C/sec. max. 8 min. max.
Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5 C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25 C to Peak Temperature Note:
It is recommended to apply a soldering temperature higher than 250C
A maximum of three reflow passes is allowed per component.
1006
AT91SAM9263 Preliminary
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AT91SAM9263 Preliminary
48. AT91SAM9263 Ordering Information
Table 48-1. AT91SAM9263 Ordering Information
Package BGA324 Package Type Green Temperature Operating Range Industrial -40C to 85C
Ordering Code AT91SAM9263-CU
1007
6249B-ATARM-14-Dec-06
1008
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
49. AT91SAM9263 Errata
49.1 Marking
All devices are marked with the Atmel logo and the ordering code. Additional marking has the following format:
YYWW V XXXXXXXXX
where
ARM
* "YY": manufactory year * "WW": manufactory week * "V": revision * "XXXXXXXXX": lot number
1009
6249B-ATARM-14-Dec-06
49.2
AT91SAM9263 Errata - Revision "A" Parts
Refer to Section 49.1 "Marking", on page 1009.
49.2.1 49.2.1.1
AC97 Bad management of endianess conversion When the transfer size is not a multiple of bytes, the Endianess is incorrect. Problem Fix/Workaround None.
49.2.2 49.2.2.1
Bus Matrix Problem with locked transfers Locked transfers are not correctly handled by the Bus Matrix and can lead to a system freezeup. This does not concern ARM locked transfers. Problem Fix/Workaround Avoid other Bus Matrix masters locked transfers.
49.2.3 49.2.3.1
CAN Low Power Mode and Error Frame If the Low Power Mode is activated while the CAN is generating an error frame, this error frame may be shortened. Problem Fix/Workaround None
49.2.3.2
Low Power Mode and arbitration If Low Power Mode is activated when the CAN has just lost the arbitration, the frame is not resent. Problem Fix/Workaround None
49.2.3.3
Mailbox error on TX If the RX line is set at the dominant level just before a TX request, Mailbox 0 can be selected instead of the requested TX Mailbox. Thus the data of the next generated frame can be those of the Mailbox 0, whatever its state (disabled, TX, RX, etc.). Problem Fix/Workaround None
1010
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49.2.4 49.2.4.1 ECC ECC status may be wrong with external SRAM When the data bus width is different for an SRAM on any EBI NCS and the NANDFlash, the ECC status is wrong. A single error is seen as a multiple error and is not corrected.This does not occur with SDRAM. Problem Fix/Workaround None. 49.2.5 49.2.5.1 MCI Busy signal of R1b responses is not taken in account The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Additionally, for commands CMD42 and CMD56, a conflict can occur on data line 0 if the MCI sends data to the card while the card is still busy. The behavior is correct for CMD12 command (STOP_TRANSFER). Problem Fix/Workaround None 49.2.5.2 SDIO interrupt does not work for slot different from A If data bus width is 1 bit and is on other slots than Slot A, the SDIO interrupt cannot be captured. The sample is made on the bad data line. Problem Fix/Workaround None 49.2.6 49.2.6.1 ROM Code SDCard Boot is not functional SDCard Boot is not functional in this revision. Problem Fix/Workaround None. 49.2.6.2 NAND Flash Boot is not functional NAND Flash Boot is not functional in this revision. Problem Fix/Workaround None.
1011
6249B-ATARM-14-Dec-06
49.2.7 49.2.7.1
SDRAM Controller SDCLK Clock active after reset After a reset, the SDRAM clock is always active leading to overconsumption in the pad. Problem Fix/Workaround The following sequence stops the SDRAM clock: 1. Set the bit LPCB in the SDRAMC Low Power Register. 2. Write 0 in the SDRAMC Mode Register and perform a dummy write in SDRAM to complete.
49.2.7.2
Mobile SDRAM and data bus Do not let data bus float before the SDRAM initialization phase. In this case, Mobile SDRAM can be used. Problem Fix/Workaround None.
49.2.8 49.2.8.1
Serial Peripheral Interface (SPI) PDC data loss 1 byte data can be lost when PDC transmit. Problem Fix/Workaround Check data integrity via software.
49.2.8.2
Pulse Generation on SPCK In Master Mode, there is an additional pulse generated on SPCK when the SPI is configured as follows: - The Baudrate is odd and different from 1. - The Polarity is set to 1. - The Phase is set to 0 . Problem Fix/Workaround None.
49.2.8.3
Bad PDC behavior when CSAAT=1 and SCBR = 1 If the SPI2 is programmed with CSAAT = 1, SCBR(baudrate) = 1 and two transfers are performed consecutively on the same slave with an IDLE state between them, the second data is sent twice. Problem Fix/Workaround None. Do not use the combination CSAAT=1 and SCBR =1.
49.2.8.4
LASTXFER (Last Transfer) Behavior In FIXED Mode with CSAAT bit set and in PDC Mode, the Chip Select can rise depending on the data written in the SPI_TDR when the TX_EMPTY flag is set. For example, if the PDC writes a
1012
AT91SAM9263 Preliminary
6249B-ATARM-14-Dec-06
AT91SAM9263 Preliminary
"1" in bit 24 (LASTXFER bit) of the SPI_TDR, the Chip Select rises as soon as the TXEMPTY flag is set. Problem Fix/Workaround Use the CS in PIO mode when PDC Mode is required and CS has to be maintained between transfers. 49.2.8.5 Baudrate set to 1 When Baudrate is set to 1 (i.e. when serial clock frequency equals the system clock frequency), and when the fields BITS (number of bits to be transmitted) equals an ODD value (in this case 9,11,13 or 15), an additional pulse is generated on output SPCK. No such pulse occurs if BITS field equals 8,10,12,14 or 16 and Baudrate = 1. Problem Fix/Workaround None. 49.2.8.6 Software reset If the Software reset command is performed during the same clock cycle as an event for TXRDY, there is no reset. Problem Fix/Workaround Perform another a software reset. 49.2.8.7 Chip Select and fixed mode In fixed Mode, if a transfer is performed through a PDC on a Chip Select different from the Chip Select 0, the output spi_size sampled by the PDC depends on the field BITS of SPI_CSR0 register, whatever the selected Chip select may be. For example, if CSR0 is configured for a 10-bit transfer, whereas the CSR1 is configured for an 8-bit transfer, when a transfer is performed in Fixed mode through the PDC on Chip Select 1, the transfer is considered to be a half-word transfer. Problem Fix/Workaround If a PDC transfer has to be performed in 8 bits on a Chip select y (y different from 0), the field BITS of the CSR0 must be configured in 8 bits in the same way as the field BITS of the CSRy Register. 49.2.9 49.2.9.1 Serial Synchronous Controller (SSC) Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a Start Delay equal to zero. Problem Fix/Workaround None. 49.2.9.2 Periodic Transmission Limitations in Master Mode If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent. Problem Fix/Workaround
1013
6249B-ATARM-14-Dec-06
None. 49.2.10 49.2.10.1 System Controller Possible event loss when reading RTT_SR If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when RTT_SR is read, the corresponding bit may be cleared. This may lead to the loss of this event. Problem Fix/Workaround The software must handle the RTT event as an interrupt and should not poll RTT_SR.
49.2.11 49.2.11.1
Two-wire Interface (TWI) Clock Divider The value of CLDIV x 2CKDIV must be less than or equal to 8191, the value of CHDIV x 2CKDIV must be less than or equal to 8191* Problem Fix/Workaround None.
49.2.11.2
Disabling Does not Operate Correctly Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register (TWI_SR) are not reset. Problem Fix/Workaround The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts must be disabled before disabling the TWI.
49.2.11.3
Software reset When a software reset is performed during a frame and when TWCK is low, it is impossible to initiate a new transfer in READ or WRITE mode. Problem Fix/Workaround None.
49.2.11.4
STOP not generated If the sequence described as follows occurs: 1. WRITE 1 or more bytes at a given address. 2. Send a STOP. 3. Wait for TXCOMP flag. 4. READ (or WRITE) 1 or more bytes at the same address. The STOP is not generated. The line shows: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n. Problem Fix/Workaround Insert a delay of one TWI clock period before step 4.
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49.2.12 49.2.12.1 UDP Bad data in the first IN data Stage All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length Packet. The CRC is correct. Thus the HOST may only see that the size of the received data does not match the requested length. But even if performed again, the control transfer probably fails. Problem Fix/Workaround Control transfers are mainly used at device configuration. After clearing RXSETUP, the software needs to compute the setup transaction request before writing data into the FIFO if needed. This time is generally greater than the minimum safe delay required above. If not, a software wait loop after RXSETUP clear may be added at minimum cost. 49.2.13 49.2.13.1 UHP Non-ISO IN transfers Conditions: Consider the following scenario: 1. The Host controller issues an IN token. 2. The Device provides the IN data in a short packet. 3. The Host controller writes the received data to the system memory. 4. The Host controller is now supposed to do two Write transactions (TD status write and TD retirement write) to the system memory in order to complete the status update. 5. Host controller raises the request for the first write transaction. By the time the transaction is completed, a frame boundary is crossed. 6. After completing the first write transaction, the Host controller skips the second write transaction. Consequence: When this error occurs, the Host controller tries the same IN token again. Problem Fix/Workaround This problem can be avoided if the system guarantees that the status update can be completed within the same frame. 49.2.13.2 ISO OUT transfers Conditions: Consider the following scenario: 1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the system memory. 2. When the Host controller is sending the ISO OUT data, because of system latencies, remaining bytes of the packet are not available. This results in a buffer underrun condition. 3. While there is an underrun condition, if the Host controller is in the process of bit-stuffing, it causes the Host controller to hang. Consequence: After the failure condition, the Host controller stops sending the SOF. This causes the connected device to go into suspend state.
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Problem Fix/Workaround This problem can be avoided if the system can guarantee that no buffer underrun occurs during the transfer. 49.2.13.3 Remote Wakeup event Conditions: When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins to send resume signaling to the device. The Host controller should send this resume signaling for 20 ms. However, if the driver sets the HcControl.HCFS into USBOPERATIONAL state during the resume event, then the Host controller terminates sending the resume signal with an EOP to the device. Consequence: If the Device does not recognize the resume (<20 ms) event then the Device, it will remain in the suspend state. Problem Fix/Workaround Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL. 49.2.14 49.2.14.1 USART RXBRK flag error in Asynchronous Mode When timeguard is 0, RXBRK is not set when the break character is located just after the Stop Bit. FRAME (Frame Error) is set instead. Problem Fix/Workaround Timeguard should be > 0. 49.2.14.2 CTS signal in Hardware Handshake When Hardware Handshaking is used and if CTS goes low near the end of the starting bit of the transmitter, a character is lost. Problem Fix/Workaround CTS must not go low during a time slot comprised between 2 Master Clock periods before the rising edge of the starting bit and 16 Master Clock periods after the rising edge of the starting bit. 49.2.14.3 RTS not expected behavior 1. Setting the receiver to hardware handshaking mode drops RTS line to low level even if the receiver is still turned off. USART needs to be completely configured and started before setting the receiver to hardware handshaking mode. 2. Disabling the receiver during a PDC transfer while RXBUFF flag is '0' has no effect on RTS. The only way to get the RTS line to rise to high level is to reset both PDMA buffers by writing the value '0' in both counter registers. Problem Fix/Workaround None.
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50. Revision History
Table 50-1.
Revision 6249A Comments First issue. Corrected typo to IDE hard disk in Section 1. "Description", on page 3. In Section 13. "AT91SAM9263 Boot Program", on page 93, added information on NANDFlash and SDCard boot in the ROM. 6249B Corrected typo in PB range in Table 46-2, "DC Characteristics," on page 973. Updated Static Current conditions and values. Corrected ordering code in Section 48. "AT91SAM9263 Ordering Information", on page 1007. In "AT91SAM9263 Errata", added Section 49.2.6.1 "SDCard Boot is not functional", on page 1011 and Section 49.2.6.2 "NAND Flash Boot is not functional", on page 1011. 3804 3802 3804 3805 3803 Change Request Ref.
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Table of Contents
Features .........................................................................................1 1 2 3 4 Description ...................................................................................3 AT91SAM9263 Block Diagram ....................................................4 Signal Description ........................................................................5 Package and Pinout ...................................................................10
4.1 324-ball LFBGA Package Outline ........................................................... 10 4.2 324-ball BGA Package Pinout ...............................................................11
5
Power Considerations ...............................................................12
5.1 Power Supplies ....................................................................................... 12 5.2 Power Consumption ............................................................................... 13 5.3 Programmable I/O Lines Power Supplies ............................................... 13
6
I/O Line Considerations .............................................................13
6.1 JTAG Port Pins ....................................................................................... 13 6.2 Test Pin .................................................................................................. 14 6.3 Reset Pins .............................................................................................. 14 6.4 PIO Controllers ....................................................................................... 14 6.5 Shutdown Logic Pins .............................................................................. 14
7
Processor and Architecture ......................................................14
7.1 ARM926EJ-S Processor ......................................................................... 14 7.2 Bus Matrix ............................................................................................... 15 7.3 Matrix Masters ........................................................................................ 16 7.4 Matrix Slaves .......................................................................................... 16 7.5 Master to Slave Access .......................................................................... 17 7.6 Peripheral DMA Controller ...................................................................... 17 7.7 DMA Controller ....................................................................................... 18 7.8 Debug and Test Features ....................................................................... 19
8
Memories ....................................................................................20
8.1 Embedded Memories ............................................................................. 21 8.2 External Memories .................................................................................. 24
9
System Controller ......................................................................26
9.1 System Controller Block Diagram ........................................................... 27
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9.2 Reset Controller ...................................................................................... 28 9.3 Shutdown Controller ............................................................................... 28 9.4 Clock Generator ..................................................................................... 28 9.5 Power Management Controller ...............................................................29 9.6 Periodic Interval Timer ............................................................................29 9.7 Watchdog Timer ..................................................................................... 29 9.8 Real-time Timer ...................................................................................... 30 9.9 General-purpose Backup Registers ....................................................... 30 9.10 Backup Power Switch ........................................................................... 30 9.11 Advanced Interrupt Controller ...............................................................30 9.12 Debug Unit ............................................................................................ 30 9.13 Chip Identification ................................................................................. 31 9.14 PIO Controllers ..................................................................................... 31
10 Peripherals ..................................................................................32
10.1 User Interface ....................................................................................... 32 10.2 Identifiers .............................................................................................. 32 10.3 Peripherals Signals Multiplexing on I/O Lines ...................................... 33 10.4 System Resource Multiplexing ............................................................. 39 10.5 Embedded Peripherals Overview ......................................................... 40
11 ARM926EJ-S Processor Overview ...........................................45
11.1 Overview ............................................................................................... 45 11.2 Block Diagram ...................................................................................... 46 11.3 ARM9EJ-S Processor ........................................................................... 46 11.4 CP15 Coprocessor ............................................................................... 54 11.5 Memory Management Unit (MMU) ....................................................... 57 11.6 Caches and Write Buffer ...................................................................... 58 11.7 Tightly-Coupled Memory Interface ....................................................... 60 11.8 Bus Interface Unit ................................................................................. 61
12 AT91SAM9263 Debug and Test ................................................63
12.1 Description ............................................................................................ 63 12.2 Block Diagram ...................................................................................... 64 12.3 Application Examples ........................................................................... 65 12.4 Debug and Test Pin Description ........................................................... 66 12.5 Functional Description .......................................................................... 66
13 AT91SAM9263 Boot Program ...................................................93
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13.1 Description ............................................................................................ 93 13.2 Flow Diagram ....................................................................................... 93 13.3 Device Initialization ............................................................................... 95 13.4 DataFlash Boot ..................................................................................... 96 13.5 SD Card Boot ....................................................................................... 99 13.6 NANDFlash Boot .................................................................................. 99 13.7 SAM-BA Boot ....................................................................................... 99 13.8 Hardware and Software Constraints ................................................... 102
14 Reset Controller (RSTC) ..........................................................105
14.1 Description .......................................................................................... 105 14.2 Block Diagram .................................................................................... 105 14.3 Functional Description ........................................................................ 105 14.4 Reset Controller (RSTC) User Interface ............................................. 113
15 Real-time Timer (RTT) ..............................................................117
15.1 Overview ............................................................................................. 117 15.2 Block Diagram .................................................................................... 117 15.3 Functional Description ........................................................................ 117 15.4 Real-time Timer (RTT) User Interface ................................................ 119
16 Periodic Interval Timer (PIT) ...................................................123
16.1 Overview ............................................................................................. 123 16.2 Block Diagram .................................................................................... 123 16.3 Functional Description ........................................................................ 124 16.4 Periodic Interval Timer (PIT) User Interface ....................................... 126
17 Watchdog Timer (WDT) ...........................................................129
17.1 Description .......................................................................................... 129 17.2 Block Diagram .................................................................................... 129 17.3 Functional Description ........................................................................ 130 17.4 Watchdog Timer (WDT) User Interface .............................................. 132
18 Shutdown Controller (SHDWC) ...............................................137
18.1 Description .......................................................................................... 137 18.2 Block Diagram .................................................................................... 137 18.3 I/O Lines Description ..........................................................................137 18.4 Product Dependencies ....................................................................... 137 18.5 Functional Description ........................................................................ 137
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18.6 Shutdown Controller (SHDWC) User Interface .................................. 139
19 AT91SAM9263 Bus Matrix .......................................................143
19.1 Description .......................................................................................... 143 19.2 Memory Mapping ................................................................................ 143 19.3 Special Bus Granting Techniques ...................................................... 143 19.4 Arbitration ........................................................................................... 144 19.5 Bus Matrix User Interface ................................................................... 147 19.6 Chip Configuration User Interface ...................................................... 153
20 External Bus Interface (EBI) ....................................................157
20.1 Description .......................................................................................... 157 20.2 Block Diagram .................................................................................... 158 20.3 I/O Lines Description ..........................................................................160 20.4 Application Example ........................................................................... 163 20.5 Product Dependencies ....................................................................... 166 20.6 Functional Description ........................................................................ 166 20.7 Implementation Examples .................................................................. 174
21 Static Memory Controller (SMC) .............................................183
21.1 Description .......................................................................................... 183 21.2 I/O Lines Description ..........................................................................183 21.3 Multiplexed Signals ............................................................................. 183 21.4 Application Example ........................................................................... 184 21.5 Product Dependencies ....................................................................... 184 21.6 External Memory Mapping .................................................................. 185 21.7 Connection to External Devices ......................................................... 185 21.8 Standard Read and Write Protocols ................................................... 189 21.9 Automatic Wait States ........................................................................ 197 21.10 Data Float Wait States ...................................................................... 202 21.11 External Wait .................................................................................... 206 21.12 Slow Clock Mode .............................................................................. 212 21.13 Asynchronous Page Mode ............................................................... 215 21.14 Static Memory Controller (SMC) User Interface ............................... 218
22 SDRAM Controller (SDRAMC) .................................................225
22.1 Description .......................................................................................... 225 22.2 I/O Lines Description ..........................................................................225 22.3 Application Example ........................................................................... 226 iv
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22.4 Product Dependencies ....................................................................... 228 22.5 Functional Description ........................................................................ 230 22.6 SDRAM Controller User Interface ...................................................... 238
23 Error Corrected Code (ECC) Controller .................................249
23.1 Description .......................................................................................... 249 23.2 Block Diagram .................................................................................... 249 23.3 Functional Description ........................................................................ 249 23.4 Error Corrected Code (ECC) Controller User Interface ...................... 254
24 DMA Controller (DMAC) ...........................................................259
24.1 Description .......................................................................................... 259 24.2 Block Diagram .................................................................................... 259 24.3 Functional Description ........................................................................ 259 24.4 DMA Controller (DMAC) User Interface ............................................. 289
25 Peripheral DMA Controller (PDC) ...........................................319
25.1 Description .......................................................................................... 319 25.2 Block Diagram .................................................................................... 320 25.3 Functional Description ........................................................................ 321 25.4 Peripheral DMA Controller (PDC) User Interface ............................... 324
26 Clock Generator .......................................................................333
26.1 Description .......................................................................................... 333 26.2 Slow Clock Crystal Oscillator .............................................................. 333 26.3 Main Oscillator .................................................................................... 333 26.4 Divider and PLL Block ........................................................................ 335
27 Power Management Controller (PMC) ....................................338
27.1 Description .......................................................................................... 338 27.2 Master Clock Controller ...................................................................... 338 27.3 Processor Clock Controller ................................................................. 339 27.4 USB Clock Controller ..........................................................................339 27.5 Peripheral Clock Controller ................................................................. 339 27.6 Programmable Clock Output Controller .............................................. 340 27.7 Programming Sequence ..................................................................... 340 27.8 Clock Switching Details ...................................................................... 345 27.9 Power Management Controller (PMC) User Interface ....................... 349
28 Advanced Interrupt Controller (AIC) ......................................367
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28.1 Description .......................................................................................... 367 28.2 Block Diagram .................................................................................... 368 28.3 Application Block Diagram .................................................................. 368 28.4 AIC Detailed Block Diagram ............................................................... 368 28.5 I/O Line Description ............................................................................ 369 28.6 Product Dependencies ....................................................................... 369 28.7 Functional Description ........................................................................ 370 28.8 Advanced Interrupt Controller (AIC) User Interface ............................ 380
29 Debug Unit (DBGU) ..................................................................391
29.1 Description .......................................................................................... 391 29.2 Block Diagram .................................................................................... 392 29.3 Product Dependencies ....................................................................... 393 29.4 UART Operations ............................................................................... 393 29.5 Debug Unit (DBGU) User Interface ................................................... 400
30 Parallel Input/Output (PIO) Controller ....................................415
30.1 Description .......................................................................................... 415 30.2 Block Diagram .................................................................................... 416 30.3 Product Dependencies ....................................................................... 417 30.4 Functional Description ........................................................................ 418 30.5 I/O Lines Programming Example ........................................................ 423 30.6 Parallel Input/Ouput (PIO) Controller User Interface .......................... 424
31 Serial Peripheral Interface (SPI) ..............................................445
31.1 Description .......................................................................................... 445 31.2 Block Diagram .................................................................................... 446 31.3 Application Block Diagram .................................................................. 446 31.4 Signal Description .............................................................................. 447 31.5 Product Dependencies ....................................................................... 447 31.6 Functional Description ........................................................................ 448 31.7 Serial Peripheral Interface (SPI) User Interface ................................. 457
32 Two-wire Interface (TWI) ..........................................................471
32.1 Description .......................................................................................... 471 32.2 Block Diagram .................................................................................... 471 32.3 Application Block Diagram .................................................................. 471 32.4 Product Dependencies ....................................................................... 472 32.5 Functional Description ........................................................................ 473 vi
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32.6 TWI User Interface ............................................................................. 478
33 Universal Synchronous/Asynchronous Receiver/Transmitter .. 487
33.1 Description .......................................................................................... 487 33.2 Block Diagram .................................................................................... 488 33.3 Application Block Diagram .................................................................. 489 33.4 I/O Lines Description ......................................................................... 489 33.5 Product Dependencies ....................................................................... 490 33.6 Functional Description ........................................................................ 491 33.7 USART User Interface ....................................................................... 515
34 Serial Synchronous Controller (SSC) ....................................533
34.1 Description .......................................................................................... 533 34.2 Block Diagram .................................................................................... 534 34.3 Application Block Diagram .................................................................. 534 34.4 Pin Name List ..................................................................................... 535 34.5 Product Dependencies ....................................................................... 535 34.6 Functional Description ........................................................................ 535 34.7 SSC Application Examples ................................................................. 546 34.8 Synchronous Serial Controller (SSC) User Interface ......................... 548
35 AC'97 Controller (AC'97C) .......................................................573
35.1 Description .......................................................................................... 573 35.2 Block Diagram .................................................................................... 574 35.3 Pin Name List ..................................................................................... 575 35.4 Application Block Diagram .................................................................. 575 35.5 Product Dependencies ....................................................................... 576 35.6 Functional Description ........................................................................ 577 35.7 AC'97 Controller (AC97C) User Interface ........................................... 588
36 Timer Counter (TC) ..................................................................601
36.1 Description .......................................................................................... 601 36.2 Block Diagram .................................................................................... 602 36.3 Pin Name List ..................................................................................... 603 36.4 Product Dependencies ....................................................................... 603 36.5 Functional Description ........................................................................ 604 36.6 Timer Counter (TC) User Interface ..................................................... 617
37 Controller Area Network (CAN) ...............................................635
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37.1 Description .......................................................................................... 635 37.2 Block Diagram .................................................................................... 636 37.3 Application Block Diagram .................................................................. 637 37.4 I/O Lines Description ......................................................................... 637 37.5 Product Dependencies ....................................................................... 637 37.6 CAN Controller Features .................................................................... 638 37.7 Functional Description ........................................................................ 650 37.8 Controller Area Network (CAN) User Interface .................................. 663
38 Pulse Width Modulation (PWM) Controller ............................691
38.1 Description .......................................................................................... 691 38.2 Block Diagram .................................................................................... 691 38.3 I/O Lines Description ..........................................................................692 38.4 Product Dependencies ....................................................................... 692 38.5 Functional Description ........................................................................ 692 38.6 Pulse Width Modulation (PWM) Controller User Interface ................ 700
39 MultiMedia Card Interface (MCI) .............................................711
39.1 Description .......................................................................................... 711 39.2 Block Diagram .................................................................................... 712 39.3 Application Block Diagram .................................................................. 713 39.4 Pin Name List .................................................................................... 713 39.5 Product Dependencies ....................................................................... 713 39.6 Bus Topology ...................................................................................... 714 39.7 MultiMedia Card Operations ............................................................... 717 39.8 SD/SDIO Card Operations ................................................................. 726 39.9 MultiMedia Card Interface (MCI) User Interface ................................. 727
40 Ethernet MAC 10/100 (EMACB) ...............................................745
40.1 Description .......................................................................................... 745 40.2 Block Diagram .................................................................................... 745 40.3 Functional Description ........................................................................ 746 40.4 Programming Interface ....................................................................... 758 40.5 Ethernet MAC 10/100 (EMAC) User Interface .................................... 761
41 USB Host Port (UHP) ...............................................................799
41.1 Description .......................................................................................... 799 41.2 Block Diagram .................................................................................... 799 41.3 Product Dependencies ....................................................................... 800 viii
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41.4 Functional Description ........................................................................ 801 41.5 Typical Connection ............................................................................. 803
42 USB Device Port (UDP) ............................................................805
42.1 Overview ............................................................................................. 805 42.2 Block Diagram .................................................................................... 806 42.3 Product Dependencies ....................................................................... 807 42.4 Typical Connection ............................................................................. 808 42.5 Functional Description ........................................................................ 809 42.6 USB Device Port (UDP) User Interface .............................................. 823
43 LCD Controller (LCDC) ............................................................841
43.1 Description .......................................................................................... 841 43.2 Block Diagram .................................................................................... 842 43.3 I/O Lines Description ..........................................................................843 43.4 Product Dependencies ....................................................................... 843 43.5 Functional Description ........................................................................ 844 43.6 Interrupts ............................................................................................ 864 43.7 Configuration Sequence ..................................................................... 864 43.8 Double-buffer Technique .................................................................... 865 43.9 2D Memory Addressing ...................................................................... 866 43.10 Register Configuration Guide ........................................................... 868 43.11 LCD Controller (LCDC) User Interface ............................................. 869
44 2D Graphics Controller (2DGC) ..............................................897
44.1 Description .......................................................................................... 897 44.2 Block Diagram .................................................................................... 898 44.3 Functional Description ........................................................................ 898 44.4 Examples of Drawing Functions ......................................................... 912 44.5 2D Graphic Controller (2DGC) User Interface ................................... 916
45 Image Sensor Interface (ISI) ....................................................943
45.1 Overview ............................................................................................. 943 45.2 Block Diagram .................................................................................... 944 45.3 Functional Description ........................................................................ 944 45.4 Image Sensor Interface (ISI) User Interface ....................................... 953
46 AT91SAM9263 Electrical Characteristics ..............................973
46.1 Absolute Maximum Ratings ................................................................ 973
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46.2 DC Characteristics .............................................................................. 973 46.3 Power Consumption ........................................................................... 974 46.4 Clock Characteristics ..........................................................................978 46.5 Crystal Oscillator Characteristics ........................................................ 979 46.6 USB Transceiver Characteristics ........................................................ 982 46.7 EBI Timings ........................................................................................ 982 46.8 EMAC Timings .................................................................................... 996 46.9 Peripheral Timings .............................................................................. 999
47 AT91SAM9263 Mechanical Characteristics .........................1004
47.1 Thermal Considerations ................................................................... 1004 47.2 Package Drawing ............................................................................. 1005 47.3 Soldering Profile ............................................................................... 1006
48 AT91SAM9263 Ordering Information ...................................1007 49 AT91SAM9263 Errata .............................................................1009
49.1 Marking ............................................................................................. 1009 49.2 AT91SAM9263 Errata - Revision "A" Parts ...................................... 1010
50 Revision History .....................................................................1017 Table of Contents ...........................................................................i
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